[32f415d] | 1 | /* mips.h |
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[f198c63] | 2 | * |
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[aa7f8a1f] | 3 | * COPYRIGHT (c) 1989-2001. |
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[f198c63] | 4 | * On-Line Applications Research Corporation (OAR). |
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| 5 | * |
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[98e4ebf5] | 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 8 | * http://www.OARcorp.com/rtems/license.html. |
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[f198c63] | 9 | * |
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[cda277f] | 10 | * $Id$ |
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[f198c63] | 11 | */ |
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| 12 | /* @(#)mips64orion.h 08/29/96 1.3 */ |
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| 13 | |
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[fda47cd] | 14 | #ifndef _INCLUDE_MIPS_h |
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| 15 | #define _INCLUDE_MIPS_h |
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[f198c63] | 16 | |
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| 17 | #ifdef __cplusplus |
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| 18 | extern "C" { |
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| 19 | #endif |
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| 20 | |
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[1800f717] | 21 | #ifndef ASM |
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| 22 | #include <idtcpu.h> |
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| 23 | #endif |
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| 24 | |
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[16ad7ea] | 25 | /* |
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| 26 | * SR bits that enable/disable interrupts |
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| 27 | * |
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| 28 | * NOTE: XXX what about SR_ERL? |
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| 29 | */ |
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| 30 | |
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| 31 | #if __mips == 3 |
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| 32 | #ifdef ASM |
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[2e549dad] | 33 | #define SR_INTERRUPT_ENABLE_BITS 0x01 |
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[16ad7ea] | 34 | #else |
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[2e549dad] | 35 | #define SR_INTERRUPT_ENABLE_BITS SR_IE |
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[16ad7ea] | 36 | #endif |
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[2e549dad] | 37 | |
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| 38 | #elif __mips == 1 |
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[16ad7ea] | 39 | #define SR_INTERRUPT_ENABLE_BITS SR_IEC |
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[2e549dad] | 40 | |
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| 41 | #else |
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| 42 | #error "mips interrupt enable bits: unknown architecture level!" |
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[16ad7ea] | 43 | #endif |
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| 44 | |
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[f198c63] | 45 | /* |
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| 46 | * This file contains the information required to build |
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| 47 | * RTEMS for a particular member of the "no cpu" |
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| 48 | * family when executing in protected mode. It does |
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| 49 | * this by setting variables to indicate which implementation |
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| 50 | * dependent features are present in a particular member |
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| 51 | * of the family. |
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| 52 | */ |
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| 53 | |
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[fda47cd] | 54 | #if defined(__mips_soft_float) |
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| 55 | #define MIPS_HAS_FPU 0 |
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| 56 | #else |
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| 57 | #define MIPS_HAS_FPU 1 |
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| 58 | #endif |
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[f198c63] | 59 | |
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[fda47cd] | 60 | #if (__mips == 1) |
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| 61 | #define CPU_MODEL_NAME "ISA Level 1 or 2" |
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| 62 | #elif (__mips == 3) |
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| 63 | #if defined(__mips64) |
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| 64 | #define CPU_MODEL_NAME "ISA Level 4" |
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[f198c63] | 65 | #else |
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[fda47cd] | 66 | #define CPU_MODEL_NAME "ISA Level 3" |
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| 67 | #endif |
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| 68 | #else |
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| 69 | #error "Unknown MIPS ISA level" |
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[f198c63] | 70 | #endif |
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| 71 | |
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| 72 | /* |
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| 73 | * Define the name of the CPU family. |
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| 74 | */ |
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| 75 | |
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[fda47cd] | 76 | #define CPU_NAME "MIPS" |
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[f198c63] | 77 | |
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[32f415d] | 78 | /* |
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| 79 | * Some macros to access registers |
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| 80 | */ |
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| 81 | |
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| 82 | #define mips_get_sr( _x ) \ |
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| 83 | do { \ |
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[9c1dc8c] | 84 | asm volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \ |
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[32f415d] | 85 | } while (0) |
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| 86 | |
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| 87 | #define mips_set_sr( _x ) \ |
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| 88 | do { \ |
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[9c1dc8c] | 89 | register unsigned int __x = (_x); \ |
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[32f415d] | 90 | asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ |
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| 91 | } while (0) |
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| 92 | |
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[e2040ba] | 93 | |
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| 94 | |
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| 95 | |
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| 96 | |
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| 97 | #define mips_get_cause( _x ) \ |
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| 98 | do { \ |
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| 99 | asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \ |
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| 100 | } while (0) |
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| 101 | |
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| 102 | |
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| 103 | #define mips_set_cause( _x ) \ |
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| 104 | do { \ |
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| 105 | register unsigned int __x = (_x); \ |
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| 106 | asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \ |
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| 107 | } while (0) |
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| 108 | |
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| 109 | |
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| 110 | |
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| 111 | |
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| 112 | |
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| 113 | #define mips_get_fcr31( _x ) \ |
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| 114 | do { \ |
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| 115 | asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \ |
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| 116 | } while(0) |
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| 117 | |
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| 118 | |
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| 119 | #define mips_set_fcr31( _x ) \ |
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| 120 | do { \ |
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| 121 | register unsigned int __x = (_x); \ |
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| 122 | asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \ |
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| 123 | } while(0) |
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| 124 | |
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| 125 | |
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| 126 | |
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| 127 | |
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| 128 | |
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[32f415d] | 129 | /* |
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| 130 | * Manipulate interrupt mask |
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| 131 | * |
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| 132 | * mips_unmask_interrupt( _mask) |
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| 133 | * enables interrupts - mask is positioned so it only needs to be or'ed |
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| 134 | * into the status reg. This also does some other things !!!! Caution |
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| 135 | * should be used if invoking this while in the middle of a debugging |
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| 136 | * session where the client may have nested interrupts. |
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| 137 | * |
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| 138 | * mips_mask_interrupt( _mask ) |
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| 139 | * disable the interrupt - mask is the complement of the bits to be |
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| 140 | * cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff |
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| 141 | * |
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| 142 | * |
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| 143 | * NOTE: mips_mask_interrupt() used to be disable_int(). |
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| 144 | * mips_unmask_interrupt() used to be enable_int(). |
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| 145 | * |
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| 146 | */ |
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| 147 | |
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| 148 | #define mips_enable_in_interrupt_mask( _mask ) \ |
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| 149 | do { \ |
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| 150 | unsigned int _sr; \ |
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| 151 | mips_get_sr( _sr ); \ |
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[1800f717] | 152 | _sr |= (_mask); \ |
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[32f415d] | 153 | mips_set_sr( _sr ); \ |
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| 154 | } while (0) |
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| 155 | |
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| 156 | #define mips_disable_in_interrupt_mask( _mask ) \ |
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| 157 | do { \ |
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| 158 | unsigned int _sr; \ |
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| 159 | mips_get_sr( _sr ); \ |
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| 160 | _sr &= ~(_mask); \ |
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| 161 | mips_set_sr( _sr ); \ |
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| 162 | } while (0) |
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| 163 | |
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[f198c63] | 164 | #ifdef __cplusplus |
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| 165 | } |
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| 166 | #endif |
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| 167 | |
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[fda47cd] | 168 | #endif /* ! _INCLUDE_MIPS_h */ |
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[f198c63] | 169 | /* end of include file */ |
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