[32f415d] | 1 | /* mips.h |
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[f198c63] | 2 | * |
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[32f415d] | 3 | * COPYRIGHT (c) 1989-2000. |
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[f198c63] | 4 | * On-Line Applications Research Corporation (OAR). |
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| 5 | * |
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[98e4ebf5] | 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 8 | * http://www.OARcorp.com/rtems/license.html. |
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[f198c63] | 9 | * |
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[cda277f] | 10 | * $Id$ |
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[f198c63] | 11 | */ |
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| 12 | /* @(#)mips64orion.h 08/29/96 1.3 */ |
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| 13 | |
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[fda47cd] | 14 | #ifndef _INCLUDE_MIPS_h |
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| 15 | #define _INCLUDE_MIPS_h |
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[f198c63] | 16 | |
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| 17 | #ifdef __cplusplus |
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| 18 | extern "C" { |
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| 19 | #endif |
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| 20 | |
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[1800f717] | 21 | #ifndef ASM |
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| 22 | #include <idtcpu.h> |
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| 23 | #endif |
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| 24 | |
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[f198c63] | 25 | /* |
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| 26 | * This file contains the information required to build |
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| 27 | * RTEMS for a particular member of the "no cpu" |
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| 28 | * family when executing in protected mode. It does |
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| 29 | * this by setting variables to indicate which implementation |
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| 30 | * dependent features are present in a particular member |
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| 31 | * of the family. |
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| 32 | */ |
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| 33 | |
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[fda47cd] | 34 | #if defined(__mips_soft_float) |
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| 35 | #define MIPS_HAS_FPU 0 |
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| 36 | #else |
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| 37 | #define MIPS_HAS_FPU 1 |
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| 38 | #endif |
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[f198c63] | 39 | |
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[fda47cd] | 40 | #if (__mips == 1) |
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| 41 | #define CPU_MODEL_NAME "ISA Level 1 or 2" |
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| 42 | #elif (__mips == 3) |
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| 43 | #if defined(__mips64) |
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| 44 | #define CPU_MODEL_NAME "ISA Level 4" |
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[f198c63] | 45 | #else |
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[fda47cd] | 46 | #define CPU_MODEL_NAME "ISA Level 3" |
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| 47 | #endif |
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| 48 | #else |
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| 49 | #error "Unknown MIPS ISA level" |
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[f198c63] | 50 | #endif |
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| 51 | |
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| 52 | /* |
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| 53 | * Define the name of the CPU family. |
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| 54 | */ |
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| 55 | |
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[fda47cd] | 56 | #define CPU_NAME "MIPS" |
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[f198c63] | 57 | |
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[32f415d] | 58 | /* |
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| 59 | * Some macros to access registers |
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| 60 | */ |
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| 61 | |
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| 62 | #define mips_get_sr( _x ) \ |
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| 63 | do { \ |
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| 64 | asm volatile( "mfc0 %0, $12; nop" : "=g" (_x) : ); \ |
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| 65 | } while (0) |
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| 66 | |
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| 67 | #define mips_set_sr( _x ) \ |
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| 68 | do { \ |
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| 69 | unsigned int __x = (_x); \ |
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| 70 | asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ |
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| 71 | } while (0) |
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| 72 | |
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| 73 | /* |
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| 74 | * Manipulate interrupt mask |
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| 75 | * |
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| 76 | * mips_unmask_interrupt( _mask) |
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| 77 | * enables interrupts - mask is positioned so it only needs to be or'ed |
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| 78 | * into the status reg. This also does some other things !!!! Caution |
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| 79 | * should be used if invoking this while in the middle of a debugging |
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| 80 | * session where the client may have nested interrupts. |
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| 81 | * |
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| 82 | * mips_mask_interrupt( _mask ) |
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| 83 | * disable the interrupt - mask is the complement of the bits to be |
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| 84 | * cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff |
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| 85 | * |
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| 86 | * |
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| 87 | * NOTE: mips_mask_interrupt() used to be disable_int(). |
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| 88 | * mips_unmask_interrupt() used to be enable_int(). |
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| 89 | * |
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| 90 | */ |
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| 91 | |
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| 92 | #define mips_enable_in_interrupt_mask( _mask ) \ |
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| 93 | do { \ |
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| 94 | unsigned int _sr; \ |
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| 95 | mips_get_sr( _sr ); \ |
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[1800f717] | 96 | _sr |= (_mask); \ |
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[32f415d] | 97 | mips_set_sr( _sr ); \ |
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| 98 | } while (0) |
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| 99 | |
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| 100 | #define mips_disable_in_interrupt_mask( _mask ) \ |
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| 101 | do { \ |
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| 102 | unsigned int _sr; \ |
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| 103 | mips_get_sr( _sr ); \ |
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| 104 | _sr &= ~(_mask); \ |
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| 105 | mips_set_sr( _sr ); \ |
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| 106 | } while (0) |
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| 107 | |
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[f198c63] | 108 | #ifdef __cplusplus |
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| 109 | } |
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| 110 | #endif |
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| 111 | |
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[fda47cd] | 112 | #endif /* ! _INCLUDE_MIPS_h */ |
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[f198c63] | 113 | /* end of include file */ |
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