source: rtems/c/src/exec/score/cpu/mips/rtems/score/cpu.h @ aa7f8a1f

4.104.114.84.95
Last change on this file since aa7f8a1f was aa7f8a1f, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 14, 2001 at 4:43:35 PM

2001-03-14 Joel Sherrill <joel@…>

  • cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: Removed unused variable _CPU_Thread_dispatch_pointer and cleaned numerous comments.
  • Property mode set to 100644
File size: 32.8 KB
Line 
1/* 
2 *  Mips CPU Dependent Header File
3 * 
4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
5 *           Joel Sherrill <joel@OARcorp.com>.
6 * 
7 *    These changes made the code conditional on standard cpp predefines,
8 *    merged the mips1 and mips3 code sequences as much as possible,
9 *    and moved some of the assembly code to C.  Alan did much of the
10 *    initial analysis and rework.  Joel took over from there and
11 *    wrote the JMR3904 BSP so this could be tested.  Joel also
12 *    added the new interrupt vectoring support in libcpu and
13 *    tried to better support the various interrupt controllers.
14 *     
15 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
16 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
17 *
18 *    To anyone who acknowledges that this file is provided "AS IS"
19 *    without any express or implied warranty:
20 *      permission to use, copy, modify, and distribute this file
21 *      for any purpose is hereby granted without fee, provided that
22 *      the above copyright notice and this notice appears in all
23 *      copies, and that the name of Transition Networks not be used in
24 *      advertising or publicity pertaining to distribution of the
25 *      software without specific, written prior permission.
26 *      Transition Networks makes no representations about the suitability
27 *      of this software for any purpose.
28 *
29 *  COPYRIGHT (c) 1989-2001.
30 *  On-Line Applications Research Corporation (OAR).
31 *
32 *  The license and distribution terms for this file may be
33 *  found in the file LICENSE in this distribution or at
34 *  http://www.OARcorp.com/rtems/license.html.
35 *
36 *  $Id$
37 */
38
39#ifndef __CPU_h
40#define __CPU_h
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46#include <rtems/score/mips.h>       /* pick up machine definitions */
47#ifndef ASM
48#include <rtems/score/mipstypes.h>
49#endif
50
51/* conditional compilation parameters */
52
53/*
54 *  Should the calls to _Thread_Enable_dispatch be inlined?
55 *
56 *  If TRUE, then they are inlined.
57 *  If FALSE, then a subroutine call is made.
58 *
59 *  Basically this is an example of the classic trade-off of size
60 *  versus speed.  Inlining the call (TRUE) typically increases the
61 *  size of RTEMS while speeding up the enabling of dispatching.
62 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
63 *  only be 0 or 1 unless you are in an interrupt handler and that
64 *  interrupt handler invokes the executive.]  When not inlined
65 *  something calls _Thread_Enable_dispatch which in turns calls
66 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
67 *  one subroutine call is avoided entirely.]
68 */
69
70#define CPU_INLINE_ENABLE_DISPATCH       TRUE
71
72/*
73 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
74 *  be unrolled one time?  In unrolled each iteration of the loop examines
75 *  two "nodes" on the chain being searched.  Otherwise, only one node
76 *  is examined per iteration.
77 *
78 *  If TRUE, then the loops are unrolled.
79 *  If FALSE, then the loops are not unrolled.
80 *
81 *  The primary factor in making this decision is the cost of disabling
82 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
83 *  body of the loop.  On some CPUs, the flash is more expensive than
84 *  one iteration of the loop body.  In this case, it might be desirable
85 *  to unroll the loop.  It is important to note that on some CPUs, this
86 *  code is the longest interrupt disable period in RTEMS.  So it is
87 *  necessary to strike a balance when setting this parameter.
88 */
89
90#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
91
92/*
93 *  Does RTEMS manage a dedicated interrupt stack in software?
94 *
95 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
96 *  If FALSE, nothing is done.
97 *
98 *  If the CPU supports a dedicated interrupt stack in hardware,
99 *  then it is generally the responsibility of the BSP to allocate it
100 *  and set it up.
101 *
102 *  If the CPU does not support a dedicated interrupt stack, then
103 *  the porter has two options: (1) execute interrupts on the
104 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
105 *  interrupt stack.
106 *
107 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
108 *
109 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
110 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
111 *  possible that both are FALSE for a particular CPU.  Although it
112 *  is unclear what that would imply about the interrupt processing
113 *  procedure on that CPU.
114 */
115
116#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
117
118/*
119 *  Does this CPU have hardware support for a dedicated interrupt stack?
120 *
121 *  If TRUE, then it must be installed during initialization.
122 *  If FALSE, then no installation is performed.
123 *
124 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
125 *
126 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
127 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
128 *  possible that both are FALSE for a particular CPU.  Although it
129 *  is unclear what that would imply about the interrupt processing
130 *  procedure on that CPU.
131 */
132
133#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
134
135/*
136 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
137 *
138 *  If TRUE, then the memory is allocated during initialization.
139 *  If FALSE, then the memory is allocated during initialization.
140 *
141 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
142 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
143 */
144
145#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
146
147/*
148 *  Does the RTEMS invoke the user's ISR with the vector number and
149 *  a pointer to the saved interrupt frame (1) or just the vector
150 *  number (0)?
151 */
152
153#define CPU_ISR_PASSES_FRAME_POINTER 0
154
155/*
156 *  Does the CPU have hardware floating point?
157 *
158 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
159 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
160 *
161 *  If there is a FP coprocessor such as the i387 or mc68881, then
162 *  the answer is TRUE.
163 *
164 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
165 *  It indicates whether or not this CPU model has FP support.  For
166 *  example, it would be possible to have an i386_nofp CPU model
167 *  which set this to false to indicate that you have an i386 without
168 *  an i387 and wish to leave floating point support out of RTEMS.
169 */
170
171#if ( MIPS_HAS_FPU == 1 )
172#define CPU_HARDWARE_FP     TRUE
173#else
174#define CPU_HARDWARE_FP     FALSE
175#endif
176
177/*
178 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
179 *
180 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
181 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
182 *
183 *  So far, the only CPU in which this option has been used is the
184 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
185 *  floating point registers to perform integer multiplies.  If
186 *  a function which you would not think utilize the FP unit DOES,
187 *  then one can not easily predict which tasks will use the FP hardware.
188 *  In this case, this option should be TRUE.
189 *
190 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
191 */
192
193#define CPU_ALL_TASKS_ARE_FP    FALSE
194
195/*
196 *  Should the IDLE task have a floating point context?
197 *
198 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
199 *  and it has a floating point context which is switched in and out.
200 *  If FALSE, then the IDLE task does not have a floating point context.
201 *
202 *  Setting this to TRUE negatively impacts the time required to preempt
203 *  the IDLE task from an interrupt because the floating point context
204 *  must be saved as part of the preemption.
205 */
206
207#define CPU_IDLE_TASK_IS_FP      FALSE
208
209/*
210 *  Should the saving of the floating point registers be deferred
211 *  until a context switch is made to another different floating point
212 *  task?
213 *
214 *  If TRUE, then the floating point context will not be stored until
215 *  necessary.  It will remain in the floating point registers and not
216 *  disturned until another floating point task is switched to.
217 *
218 *  If FALSE, then the floating point context is saved when a floating
219 *  point task is switched out and restored when the next floating point
220 *  task is restored.  The state of the floating point registers between
221 *  those two operations is not specified.
222 *
223 *  If the floating point context does NOT have to be saved as part of
224 *  interrupt dispatching, then it should be safe to set this to TRUE.
225 *
226 *  Setting this flag to TRUE results in using a different algorithm
227 *  for deciding when to save and restore the floating point context.
228 *  The deferred FP switch algorithm minimizes the number of times
229 *  the FP context is saved and restored.  The FP context is not saved
230 *  until a context switch is made to another, different FP task.
231 *  Thus in a system with only one FP task, the FP context will never
232 *  be saved or restored.
233 */
234
235#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
236
237/*
238 *  Does this port provide a CPU dependent IDLE task implementation?
239 *
240 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
241 *  must be provided and is the default IDLE thread body instead of
242 *  _Internal_threads_Idle_thread_body.
243 *
244 *  If FALSE, then use the generic IDLE thread body if the BSP does
245 *  not provide one.
246 *
247 *  This is intended to allow for supporting processors which have
248 *  a low power or idle mode.  When the IDLE thread is executed, then
249 *  the CPU can be powered down.
250 *
251 *  The order of precedence for selecting the IDLE thread body is:
252 *
253 *    1.  BSP provided
254 *    2.  CPU dependent (if provided)
255 *    3.  generic (if no BSP and no CPU dependent)
256 */
257
258/* we can use the low power wait instruction for the IDLE thread */
259#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
260
261/*
262 *  Does the stack grow up (toward higher addresses) or down
263 *  (toward lower addresses)?
264 *
265 *  If TRUE, then the grows upward.
266 *  If FALSE, then the grows toward smaller addresses.
267 */
268
269/* our stack grows down */
270#define CPU_STACK_GROWS_UP               FALSE
271
272/*
273 *  The following is the variable attribute used to force alignment
274 *  of critical RTEMS structures.  On some processors it may make
275 *  sense to have these aligned on tighter boundaries than
276 *  the minimum requirements of the compiler in order to have as
277 *  much of the critical data area as possible in a cache line.
278 *
279 *  The placement of this macro in the declaration of the variables
280 *  is based on the syntactically requirements of the GNU C
281 *  "__attribute__" extension.  For example with GNU C, use
282 *  the following to force a structures to a 32 byte boundary.
283 *
284 *      __attribute__ ((aligned (32)))
285 *
286 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
287 *         To benefit from using this, the data must be heavily
288 *         used so it will stay in the cache and used frequently enough
289 *         in the executive to justify turning this on.
290 */
291
292/* our cache line size is 16 bytes */
293#if __GNUC__
294#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
295#else
296#define CPU_STRUCTURE_ALIGNMENT
297#endif
298
299/*
300 *  Define what is required to specify how the network to host conversion
301 *  routines are handled.
302 */
303
304#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
305#define CPU_BIG_ENDIAN                           TRUE
306#define CPU_LITTLE_ENDIAN                        FALSE
307
308/*
309 *  The following defines the number of bits actually used in the
310 *  interrupt field of the task mode.  How those bits map to the
311 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
312 */
313
314#define CPU_MODES_INTERRUPT_MASK   0x00000001
315
316/*
317 *  Processor defined structures
318 *
319 *  Examples structures include the descriptor tables from the i386
320 *  and the processor control structure on the i960ca.
321 */
322
323/* may need to put some structures here.  */
324
325/*
326 * Contexts
327 *
328 *  Generally there are 2 types of context to save.
329 *     1. Interrupt registers to save
330 *     2. Task level registers to save
331 *
332 *  This means we have the following 3 context items:
333 *     1. task level context stuff::  Context_Control
334 *     2. floating point task stuff:: Context_Control_fp
335 *     3. special interrupt level context :: Context_Control_interrupt
336 *
337 *  On some processors, it is cost-effective to save only the callee
338 *  preserved registers during a task context switch.  This means
339 *  that the ISR code needs to save those registers which do not
340 *  persist across function calls.  It is not mandatory to make this
341 *  distinctions between the caller/callee saves registers for the
342 *  purpose of minimizing context saved during task switch and on interrupts.
343 *  If the cost of saving extra registers is minimal, simplicity is the
344 *  choice.  Save the same context on interrupt entry as for tasks in
345 *  this case.
346 *
347 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
348 *  care should be used in designing the context area.
349 *
350 *  On some CPUs with hardware floating point support, the Context_Control_fp
351 *  structure will not be used or it simply consist of an array of a
352 *  fixed number of bytes.   This is done when the floating point context
353 *  is dumped by a "FP save context" type instruction and the format
354 *  is not really defined by the CPU.  In this case, there is no need
355 *  to figure out the exact format -- only the size.  Of course, although
356 *  this is enough information for RTEMS, it is probably not enough for
357 *  a debugger such as gdb.  But that is another problem.
358 */
359
360/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
361#if __mips == 1
362#define __MIPS_REGISTER_TYPE     unsigned32
363#define __MIPS_FPU_REGISTER_TYPE unsigned32
364#elif __mips == 3
365#define __MIPS_REGISTER_TYPE     unsigned64
366#define __MIPS_FPU_REGISTER_TYPE unsigned64
367#else
368#error "mips register size: unknown architecture level!!"
369#endif
370typedef struct {
371    __MIPS_REGISTER_TYPE s0;
372    __MIPS_REGISTER_TYPE s1;
373    __MIPS_REGISTER_TYPE s2;
374    __MIPS_REGISTER_TYPE s3;
375    __MIPS_REGISTER_TYPE s4;
376    __MIPS_REGISTER_TYPE s5;
377    __MIPS_REGISTER_TYPE s6;
378    __MIPS_REGISTER_TYPE s7;
379    __MIPS_REGISTER_TYPE sp;
380    __MIPS_REGISTER_TYPE fp;
381    __MIPS_REGISTER_TYPE ra;
382    __MIPS_REGISTER_TYPE c0_sr;
383    __MIPS_REGISTER_TYPE c0_epc;
384} Context_Control;
385
386/* WARNING: If this structure is modified, the constants in cpu.h
387 *          must also be updated.
388 */
389
390typedef struct {
391#if ( CPU_HARDWARE_FP == TRUE )
392    __MIPS_FPU_REGISTER_TYPE fp0;
393    __MIPS_FPU_REGISTER_TYPE fp1;
394    __MIPS_FPU_REGISTER_TYPE fp2;
395    __MIPS_FPU_REGISTER_TYPE fp3;
396    __MIPS_FPU_REGISTER_TYPE fp4;
397    __MIPS_FPU_REGISTER_TYPE fp5;
398    __MIPS_FPU_REGISTER_TYPE fp6;
399    __MIPS_FPU_REGISTER_TYPE fp7;
400    __MIPS_FPU_REGISTER_TYPE fp8;
401    __MIPS_FPU_REGISTER_TYPE fp9;
402    __MIPS_FPU_REGISTER_TYPE fp10;
403    __MIPS_FPU_REGISTER_TYPE fp11;
404    __MIPS_FPU_REGISTER_TYPE fp12;
405    __MIPS_FPU_REGISTER_TYPE fp13;
406    __MIPS_FPU_REGISTER_TYPE fp14;
407    __MIPS_FPU_REGISTER_TYPE fp15;
408    __MIPS_FPU_REGISTER_TYPE fp16;
409    __MIPS_FPU_REGISTER_TYPE fp17;
410    __MIPS_FPU_REGISTER_TYPE fp18;
411    __MIPS_FPU_REGISTER_TYPE fp19;
412    __MIPS_FPU_REGISTER_TYPE fp20;
413    __MIPS_FPU_REGISTER_TYPE fp21;
414    __MIPS_FPU_REGISTER_TYPE fp22;
415    __MIPS_FPU_REGISTER_TYPE fp23;
416    __MIPS_FPU_REGISTER_TYPE fp24;
417    __MIPS_FPU_REGISTER_TYPE fp25;
418    __MIPS_FPU_REGISTER_TYPE fp26;
419    __MIPS_FPU_REGISTER_TYPE fp27;
420    __MIPS_FPU_REGISTER_TYPE fp28;
421    __MIPS_FPU_REGISTER_TYPE fp29;
422    __MIPS_FPU_REGISTER_TYPE fp30;
423    __MIPS_FPU_REGISTER_TYPE fp31;
424#endif
425} Context_Control_fp;
426
427typedef struct {
428    unsigned32 special_interrupt_register;
429} CPU_Interrupt_frame;
430
431
432/*
433 *  The following table contains the information required to configure
434 *  the mips processor specific parameters.
435 */
436
437typedef struct {
438  void       (*pretasking_hook)( void );
439  void       (*predriver_hook)( void );
440  void       (*postdriver_hook)( void );
441  void       (*idle_task)( void );
442  boolean      do_zero_of_workspace;
443  unsigned32   idle_task_stack_size;
444  unsigned32   interrupt_stack_size;
445  unsigned32   extra_mpci_receive_server_stack;
446  void *     (*stack_allocate_hook)( unsigned32 );
447  void       (*stack_free_hook)( void* );
448  /* end of fields required on all CPUs */
449
450  unsigned32   clicks_per_microsecond;
451}   rtems_cpu_table;
452
453/*
454 *  Macros to access required entires in the CPU Table are in
455 *  the file rtems/system.h.
456 */
457
458/*
459 *  Macros to access MIPS specific additions to the CPU Table
460 */
461
462#define rtems_cpu_configuration_get_clicks_per_microsecond() \
463   (_CPU_Table.clicks_per_microsecond)
464
465/*
466 *  This variable is optional.  It is used on CPUs on which it is difficult
467 *  to generate an "uninitialized" FP context.  It is filled in by
468 *  _CPU_Initialize and copied into the task's FP context area during
469 *  _CPU_Context_Initialize.
470 */
471
472SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
473
474/*
475 *  On some CPUs, RTEMS supports a software managed interrupt stack.
476 *  This stack is allocated by the Interrupt Manager and the switch
477 *  is performed in _ISR_Handler.  These variables contain pointers
478 *  to the lowest and highest addresses in the chunk of memory allocated
479 *  for the interrupt stack.  Since it is unknown whether the stack
480 *  grows up or down (in general), this give the CPU dependent
481 *  code the option of picking the version it wants to use.
482 *
483 *  NOTE: These two variables are required if the macro
484 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
485 */
486
487SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
488SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
489
490/*
491 *  With some compilation systems, it is difficult if not impossible to
492 *  call a high-level language routine from assembly language.  This
493 *  is especially true of commercial Ada compilers and name mangling
494 *  C++ ones.  This variable can be optionally defined by the CPU porter
495 *  and contains the address of the routine _Thread_Dispatch.  This
496 *  can make it easier to invoke that routine at the end of the interrupt
497 *  sequence (if a dispatch is necessary).
498 *
499
500SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
501 *
502 *  NOTE: Not needed on this port.
503 */
504
505/*
506 *  Nothing prevents the porter from declaring more CPU specific variables.
507 */
508
509/* XXX: if needed, put more variables here */
510
511/*
512 *  The size of the floating point context area.  On some CPUs this
513 *  will not be a "sizeof" because the format of the floating point
514 *  area is not defined -- only the size is.  This is usually on
515 *  CPUs with a "floating point save context" instruction.
516 */
517
518#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
519
520/*
521 *  Amount of extra stack (above minimum stack size) required by
522 *  system initialization thread.  Remember that in a multiprocessor
523 *  system the system intialization thread becomes the MP server thread.
524 */
525
526#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
527
528/*
529 *  This defines the number of entries in the ISR_Vector_table managed
530 *  by RTEMS.
531 */
532
533extern unsigned int mips_interrupt_number_of_vectors;
534#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
535#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
536
537/*
538 *  Should be large enough to run all RTEMS tests.  This insures
539 *  that a "reasonable" small application should not have any problems.
540 */
541
542#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
543
544/*
545 *  CPU's worst alignment requirement for data types on a byte boundary.  This
546 *  alignment does not take into account the requirements for the stack.
547 */
548
549#define CPU_ALIGNMENT              8
550
551/*
552 *  This number corresponds to the byte alignment requirement for the
553 *  heap handler.  This alignment requirement may be stricter than that
554 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
555 *  common for the heap to follow the same alignment requirement as
556 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
557 *  then this should be set to CPU_ALIGNMENT.
558 *
559 *  NOTE:  This does not have to be a power of 2.  It does have to
560 *         be greater or equal to than CPU_ALIGNMENT.
561 */
562
563#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
564
565/*
566 *  This number corresponds to the byte alignment requirement for memory
567 *  buffers allocated by the partition manager.  This alignment requirement
568 *  may be stricter than that for the data types alignment specified by
569 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
570 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
571 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
572 *
573 *  NOTE:  This does not have to be a power of 2.  It does have to
574 *         be greater or equal to than CPU_ALIGNMENT.
575 */
576
577#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
578
579/*
580 *  This number corresponds to the byte alignment requirement for the
581 *  stack.  This alignment requirement may be stricter than that for the
582 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
583 *  is strict enough for the stack, then this should be set to 0.
584 *
585 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
586 */
587
588#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
589
590/*
591 *  ISR handler macros
592 */
593
594/*
595 *  Support routine to initialize the RTEMS vector table after it is allocated.
596 */
597
598#define _CPU_Initialize_vectors()
599
600/*
601 *  Disable all interrupts for an RTEMS critical section.  The previous
602 *  level is returned in _level.
603 */
604
605#define _CPU_ISR_Disable( _level ) \
606  do { \
607    mips_get_sr( _level ); \
608    mips_set_sr( (_level) & ~SR_INTERRUPT_ENABLE_BITS ); \
609  } while(0)
610
611/*
612 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
613 *  This indicates the end of an RTEMS critical section.  The parameter
614 *  _level is not modified.
615 */
616
617#define _CPU_ISR_Enable( _level )  \
618  do { \
619    mips_set_sr(_level); \
620  } while(0)
621
622/*
623 *  This temporarily restores the interrupt to _level before immediately
624 *  disabling them again.  This is used to divide long RTEMS critical
625 *  sections into two or more parts.  The parameter _level is not
626 * modified.
627 */
628
629#define _CPU_ISR_Flash( _xlevel ) \
630  do { \
631    unsigned int _scratch; \
632    _CPU_ISR_Enable( _xlevel ); \
633    _CPU_ISR_Disable( _scratch ); \
634  } while(0)
635
636/*
637 *  Map interrupt level in task mode onto the hardware that the CPU
638 *  actually provides.  Currently, interrupt levels which do not
639 *  map onto the CPU in a generic fashion are undefined.  Someday,
640 *  it would be nice if these were "mapped" by the application
641 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
642 *  8 - 255 would be available for bsp/application specific meaning.
643 *  This could be used to manage a programmable interrupt controller
644 *  via the rtems_task_mode directive.
645 *
646 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
647 *  manipulates the IEC.
648 */
649
650unsigned32 _CPU_ISR_Get_level( void );  /* in cpu.c */
651
652void _CPU_ISR_Set_level( unsigned32 );  /* in cpu.c */
653
654/* end of ISR handler macros */
655
656/* Context handler macros */
657
658/*
659 *  Initialize the context to a state suitable for starting a
660 *  task after a context restore operation.  Generally, this
661 *  involves:
662 *
663 *     - setting a starting address
664 *     - preparing the stack
665 *     - preparing the stack and frame pointers
666 *     - setting the proper interrupt level in the context
667 *     - initializing the floating point context
668 *
669 *  This routine generally does not set any unnecessary register
670 *  in the context.  The state of the "general data" registers is
671 *  undefined at task start time.
672 *
673 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
674 *        point thread.  This is typically only used on CPUs where the
675 *        FPU may be easily disabled by software such as on the SPARC
676 *        where the PSR contains an enable FPU bit.
677 */
678
679#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
680                                 _isr, _entry_point, _is_fp ) \
681  { \
682        unsigned32 _stack_tmp = \
683           (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
684        _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
685        (_the_context)->sp = _stack_tmp; \
686        (_the_context)->fp = _stack_tmp; \
687        (_the_context)->ra = (unsigned64)_entry_point; \
688        if (_isr) (_the_context)->c0_sr = 0xff00; \
689        else      (_the_context)->c0_sr = 0xff01; \
690  }
691
692/*
693 *  This routine is responsible for somehow restarting the currently
694 *  executing task.  If you are lucky, then all that is necessary
695 *  is restoring the context.  Otherwise, there will need to be
696 *  a special assembly routine which does something special in this
697 *  case.  Context_Restore should work most of the time.  It will
698 *  not work if restarting self conflicts with the stack frame
699 *  assumptions of restoring a context.
700 */
701
702#define _CPU_Context_Restart_self( _the_context ) \
703   _CPU_Context_restore( (_the_context) );
704
705/*
706 *  The purpose of this macro is to allow the initial pointer into
707 *  A floating point context area (used to save the floating point
708 *  context) to be at an arbitrary place in the floating point
709 *  context area.
710 *
711 *  This is necessary because some FP units are designed to have
712 *  their context saved as a stack which grows into lower addresses.
713 *  Other FP units can be saved by simply moving registers into offsets
714 *  from the base of the context area.  Finally some FP units provide
715 *  a "dump context" instruction which could fill in from high to low
716 *  or low to high based on the whim of the CPU designers.
717 */
718
719#define _CPU_Context_Fp_start( _base, _offset ) \
720   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
721
722/*
723 *  This routine initializes the FP context area passed to it to.
724 *  There are a few standard ways in which to initialize the
725 *  floating point context.  The code included for this macro assumes
726 *  that this is a CPU in which a "initial" FP context was saved into
727 *  _CPU_Null_fp_context and it simply copies it to the destination
728 *  context passed to it.
729 *
730 *  Other models include (1) not doing anything, and (2) putting
731 *  a "null FP status word" in the correct place in the FP context.
732 */
733
734#if ( CPU_HARDWARE_FP == TRUE )
735#define _CPU_Context_Initialize_fp( _destination ) \
736  { \
737   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
738  }
739#endif
740
741/* end of Context handler macros */
742
743/* Fatal Error manager macros */
744
745/*
746 *  This routine copies _error into a known place -- typically a stack
747 *  location or a register, optionally disables interrupts, and
748 *  halts/stops the CPU.
749 */
750
751#define _CPU_Fatal_halt( _error ) \
752  do { \
753    unsigned int _level; \
754    _CPU_ISR_Disable(_level); \
755    loop: goto loop; \
756  } while (0)
757
758
759extern void mips_break( int error );
760
761/* Bitfield handler macros */
762
763/*
764 *  This routine sets _output to the bit number of the first bit
765 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
766 *  This type may be either 16 or 32 bits wide although only the 16
767 *  least significant bits will be used.
768 *
769 *  There are a number of variables in using a "find first bit" type
770 *  instruction.
771 *
772 *    (1) What happens when run on a value of zero?
773 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
774 *    (3) The numbering may be zero or one based.
775 *    (4) The "find first bit" instruction may search from MSB or LSB.
776 *
777 *  RTEMS guarantees that (1) will never happen so it is not a concern.
778 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
779 *  _CPU_Priority_bits_index().  These three form a set of routines
780 *  which must logically operate together.  Bits in the _value are
781 *  set and cleared based on masks built by _CPU_Priority_mask().
782 *  The basic major and minor values calculated by _Priority_Major()
783 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
784 *  to properly range between the values returned by the "find first bit"
785 *  instruction.  This makes it possible for _Priority_Get_highest() to
786 *  calculate the major and directly index into the minor table.
787 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
788 *  is the first bit found.
789 *
790 *  This entire "find first bit" and mapping process depends heavily
791 *  on the manner in which a priority is broken into a major and minor
792 *  components with the major being the 4 MSB of a priority and minor
793 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
794 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
795 *  to the lowest priority.
796 *
797 *  If your CPU does not have a "find first bit" instruction, then
798 *  there are ways to make do without it.  Here are a handful of ways
799 *  to implement this in software:
800 *
801 *    - a series of 16 bit test instructions
802 *    - a "binary search using if's"
803 *    - _number = 0
804 *      if _value > 0x00ff
805 *        _value >>=8
806 *        _number = 8;
807 *
808 *      if _value > 0x0000f
809 *        _value >=8
810 *        _number += 4
811 *
812 *      _number += bit_set_table[ _value ]
813 *
814 *    where bit_set_table[ 16 ] has values which indicate the first
815 *      bit set
816 */
817
818#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
819#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
820
821#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
822
823#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
824  { \
825    (_output) = 0;   /* do something to prevent warnings */ \
826  }
827
828#endif
829
830/* end of Bitfield handler macros */
831
832/*
833 *  This routine builds the mask which corresponds to the bit fields
834 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
835 *  for that routine.
836 */
837
838#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
839
840#define _CPU_Priority_Mask( _bit_number ) \
841  ( 1 << (_bit_number) )
842
843#endif
844
845/*
846 *  This routine translates the bit numbers returned by
847 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
848 *  a major or minor component of a priority.  See the discussion
849 *  for that routine.
850 */
851
852#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
853
854#define _CPU_Priority_bits_index( _priority ) \
855  (_priority)
856
857#endif
858
859/* end of Priority handler macros */
860
861/* functions */
862
863/*
864 *  _CPU_Initialize
865 *
866 *  This routine performs CPU dependent initialization.
867 */
868
869void _CPU_Initialize(
870  rtems_cpu_table  *cpu_table,
871  void      (*thread_dispatch)
872);
873
874/*
875 *  _CPU_ISR_install_raw_handler
876 *
877 *  This routine installs a "raw" interrupt handler directly into the
878 *  processor's vector table.
879 */
880 
881void _CPU_ISR_install_raw_handler(
882  unsigned32  vector,
883  proc_ptr    new_handler,
884  proc_ptr   *old_handler
885);
886
887/*
888 *  _CPU_ISR_install_vector
889 *
890 *  This routine installs an interrupt vector.
891 */
892
893void _CPU_ISR_install_vector(
894  unsigned32  vector,
895  proc_ptr    new_handler,
896  proc_ptr   *old_handler
897);
898
899/*
900 *  _CPU_Install_interrupt_stack
901 *
902 *  This routine installs the hardware interrupt stack pointer.
903 *
904 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
905 *         is TRUE.
906 */
907
908void _CPU_Install_interrupt_stack( void );
909
910/*
911 *  _CPU_Internal_threads_Idle_thread_body
912 *
913 *  This routine is the CPU dependent IDLE thread body.
914 *
915 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
916 *         is TRUE.
917 */
918
919void _CPU_Thread_Idle_body( void );
920
921/*
922 *  _CPU_Context_switch
923 *
924 *  This routine switches from the run context to the heir context.
925 */
926
927void _CPU_Context_switch(
928  Context_Control  *run,
929  Context_Control  *heir
930);
931
932/*
933 *  _CPU_Context_restore
934 *
935 *  This routine is generally used only to restart self in an
936 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
937 *
938 *  NOTE: May be unnecessary to reload some registers.
939 */
940
941void _CPU_Context_restore(
942  Context_Control *new_context
943);
944
945/*
946 *  _CPU_Context_save_fp
947 *
948 *  This routine saves the floating point context passed to it.
949 */
950
951void _CPU_Context_save_fp(
952  void **fp_context_ptr
953);
954
955/*
956 *  _CPU_Context_restore_fp
957 *
958 *  This routine restores the floating point context passed to it.
959 */
960
961void _CPU_Context_restore_fp(
962  void **fp_context_ptr
963);
964
965/*  The following routine swaps the endian format of an unsigned int.
966 *  It must be static because it is referenced indirectly.
967 *
968 *  This version will work on any processor, but if there is a better
969 *  way for your CPU PLEASE use it.  The most common way to do this is to:
970 *
971 *     swap least significant two bytes with 16-bit rotate
972 *     swap upper and lower 16-bits
973 *     swap most significant two bytes with 16-bit rotate
974 *
975 *  Some CPUs have special instructions which swap a 32-bit quantity in
976 *  a single instruction (e.g. i486).  It is probably best to avoid
977 *  an "endian swapping control bit" in the CPU.  One good reason is
978 *  that interrupts would probably have to be disabled to insure that
979 *  an interrupt does not try to access the same "chunk" with the wrong
980 *  endian.  Another good reason is that on some CPUs, the endian bit
981 *  endianness for ALL fetches -- both code and data -- so the code
982 *  will be fetched incorrectly.
983 */
984 
985static inline unsigned int CPU_swap_u32(
986  unsigned int value
987)
988{
989  unsigned32 byte1, byte2, byte3, byte4, swapped;
990 
991  byte4 = (value >> 24) & 0xff;
992  byte3 = (value >> 16) & 0xff;
993  byte2 = (value >> 8)  & 0xff;
994  byte1 =  value        & 0xff;
995 
996  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
997  return( swapped );
998}
999
1000#define CPU_swap_u16( value ) \
1001  (((value&0xff) << 8) | ((value >> 8)&0xff))
1002
1003#ifdef __cplusplus
1004}
1005#endif
1006
1007#endif
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