source: rtems/c/src/exec/score/cpu/mips/rtems/score/cpu.h @ 9fd4f5c5

4.104.114.84.95
Last change on this file since 9fd4f5c5 was 9fd4f5c5, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 3, 2001 at 4:35:08 PM

2001-01-03 Joel Sherrill <joel@…>

  • rtems/score/cpu.h: Added _CPU_Initialize_vectors().
  • cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
  • Property mode set to 100644
File size: 32.2 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the IDT 4650
4 *  processor.
5 *
6 *  Author:     Craig Lebakken <craigl@transition.com>
7 *
8 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of Transition Networks not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      Transition Networks makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
22 *
23 *  COPYRIGHT (c) 1989-1999.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.OARcorp.com/rtems/license.html.
29 *
30 *  $Id$
31 */
32/* @(#)cpu.h       08/29/96     1.7 */
33
34#ifndef __CPU_h
35#define __CPU_h
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41#include <rtems/score/mips.h>       /* pick up machine definitions */
42#ifndef ASM
43#include <idtcpu.h>
44#include <rtems/score/mipstypes.h>
45#endif
46
47/* conditional compilation parameters */
48
49/*
50 *  Should the calls to _Thread_Enable_dispatch be inlined?
51 *
52 *  If TRUE, then they are inlined.
53 *  If FALSE, then a subroutine call is made.
54 *
55 *  Basically this is an example of the classic trade-off of size
56 *  versus speed.  Inlining the call (TRUE) typically increases the
57 *  size of RTEMS while speeding up the enabling of dispatching.
58 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
59 *  only be 0 or 1 unless you are in an interrupt handler and that
60 *  interrupt handler invokes the executive.]  When not inlined
61 *  something calls _Thread_Enable_dispatch which in turns calls
62 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
63 *  one subroutine call is avoided entirely.]
64 */
65
66#define CPU_INLINE_ENABLE_DISPATCH       TRUE
67
68/*
69 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
70 *  be unrolled one time?  In unrolled each iteration of the loop examines
71 *  two "nodes" on the chain being searched.  Otherwise, only one node
72 *  is examined per iteration.
73 *
74 *  If TRUE, then the loops are unrolled.
75 *  If FALSE, then the loops are not unrolled.
76 *
77 *  The primary factor in making this decision is the cost of disabling
78 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
79 *  body of the loop.  On some CPUs, the flash is more expensive than
80 *  one iteration of the loop body.  In this case, it might be desirable
81 *  to unroll the loop.  It is important to note that on some CPUs, this
82 *  code is the longest interrupt disable period in RTEMS.  So it is
83 *  necessary to strike a balance when setting this parameter.
84 */
85
86#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
87
88/*
89 *  Does RTEMS manage a dedicated interrupt stack in software?
90 *
91 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
92 *  If FALSE, nothing is done.
93 *
94 *  If the CPU supports a dedicated interrupt stack in hardware,
95 *  then it is generally the responsibility of the BSP to allocate it
96 *  and set it up.
97 *
98 *  If the CPU does not support a dedicated interrupt stack, then
99 *  the porter has two options: (1) execute interrupts on the
100 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
101 *  interrupt stack.
102 *
103 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
104 *
105 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
106 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
107 *  possible that both are FALSE for a particular CPU.  Although it
108 *  is unclear what that would imply about the interrupt processing
109 *  procedure on that CPU.
110 */
111
112#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
113
114/*
115 *  Does this CPU have hardware support for a dedicated interrupt stack?
116 *
117 *  If TRUE, then it must be installed during initialization.
118 *  If FALSE, then no installation is performed.
119 *
120 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
121 *
122 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
123 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
124 *  possible that both are FALSE for a particular CPU.  Although it
125 *  is unclear what that would imply about the interrupt processing
126 *  procedure on that CPU.
127 */
128
129#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
130
131/*
132 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
133 *
134 *  If TRUE, then the memory is allocated during initialization.
135 *  If FALSE, then the memory is allocated during initialization.
136 *
137 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
138 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
139 */
140
141#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
142
143/*
144 *  Does the RTEMS invoke the user's ISR with the vector number and
145 *  a pointer to the saved interrupt frame (1) or just the vector
146 *  number (0)?
147 */
148
149#define CPU_ISR_PASSES_FRAME_POINTER 0
150
151/*
152 *  Does the CPU have hardware floating point?
153 *
154 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
155 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
156 *
157 *  If there is a FP coprocessor such as the i387 or mc68881, then
158 *  the answer is TRUE.
159 *
160 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
161 *  It indicates whether or not this CPU model has FP support.  For
162 *  example, it would be possible to have an i386_nofp CPU model
163 *  which set this to false to indicate that you have an i386 without
164 *  an i387 and wish to leave floating point support out of RTEMS.
165 */
166
167#if ( MIPS_HAS_FPU == 1 )
168#define CPU_HARDWARE_FP     TRUE
169#else
170#define CPU_HARDWARE_FP     FALSE
171#endif
172
173/*
174 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
175 *
176 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
177 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
178 *
179 *  So far, the only CPU in which this option has been used is the
180 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
181 *  floating point registers to perform integer multiplies.  If
182 *  a function which you would not think utilize the FP unit DOES,
183 *  then one can not easily predict which tasks will use the FP hardware.
184 *  In this case, this option should be TRUE.
185 *
186 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
187 */
188
189#define CPU_ALL_TASKS_ARE_FP    FALSE
190
191/*
192 *  Should the IDLE task have a floating point context?
193 *
194 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
195 *  and it has a floating point context which is switched in and out.
196 *  If FALSE, then the IDLE task does not have a floating point context.
197 *
198 *  Setting this to TRUE negatively impacts the time required to preempt
199 *  the IDLE task from an interrupt because the floating point context
200 *  must be saved as part of the preemption.
201 */
202
203#define CPU_IDLE_TASK_IS_FP      FALSE
204
205/*
206 *  Should the saving of the floating point registers be deferred
207 *  until a context switch is made to another different floating point
208 *  task?
209 *
210 *  If TRUE, then the floating point context will not be stored until
211 *  necessary.  It will remain in the floating point registers and not
212 *  disturned until another floating point task is switched to.
213 *
214 *  If FALSE, then the floating point context is saved when a floating
215 *  point task is switched out and restored when the next floating point
216 *  task is restored.  The state of the floating point registers between
217 *  those two operations is not specified.
218 *
219 *  If the floating point context does NOT have to be saved as part of
220 *  interrupt dispatching, then it should be safe to set this to TRUE.
221 *
222 *  Setting this flag to TRUE results in using a different algorithm
223 *  for deciding when to save and restore the floating point context.
224 *  The deferred FP switch algorithm minimizes the number of times
225 *  the FP context is saved and restored.  The FP context is not saved
226 *  until a context switch is made to another, different FP task.
227 *  Thus in a system with only one FP task, the FP context will never
228 *  be saved or restored.
229 */
230
231#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
232
233/*
234 *  Does this port provide a CPU dependent IDLE task implementation?
235 *
236 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
237 *  must be provided and is the default IDLE thread body instead of
238 *  _Internal_threads_Idle_thread_body.
239 *
240 *  If FALSE, then use the generic IDLE thread body if the BSP does
241 *  not provide one.
242 *
243 *  This is intended to allow for supporting processors which have
244 *  a low power or idle mode.  When the IDLE thread is executed, then
245 *  the CPU can be powered down.
246 *
247 *  The order of precedence for selecting the IDLE thread body is:
248 *
249 *    1.  BSP provided
250 *    2.  CPU dependent (if provided)
251 *    3.  generic (if no BSP and no CPU dependent)
252 */
253
254/* we can use the low power wait instruction for the IDLE thread */
255#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
256
257/*
258 *  Does the stack grow up (toward higher addresses) or down
259 *  (toward lower addresses)?
260 *
261 *  If TRUE, then the grows upward.
262 *  If FALSE, then the grows toward smaller addresses.
263 */
264
265/* our stack grows down */
266#define CPU_STACK_GROWS_UP               FALSE
267
268/*
269 *  The following is the variable attribute used to force alignment
270 *  of critical RTEMS structures.  On some processors it may make
271 *  sense to have these aligned on tighter boundaries than
272 *  the minimum requirements of the compiler in order to have as
273 *  much of the critical data area as possible in a cache line.
274 *
275 *  The placement of this macro in the declaration of the variables
276 *  is based on the syntactically requirements of the GNU C
277 *  "__attribute__" extension.  For example with GNU C, use
278 *  the following to force a structures to a 32 byte boundary.
279 *
280 *      __attribute__ ((aligned (32)))
281 *
282 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
283 *         To benefit from using this, the data must be heavily
284 *         used so it will stay in the cache and used frequently enough
285 *         in the executive to justify turning this on.
286 */
287
288/* our cache line size is 16 bytes */
289#if __GNUC__
290#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
291#else
292#define CPU_STRUCTURE_ALIGNMENT
293#endif
294
295/*
296 *  Define what is required to specify how the network to host conversion
297 *  routines are handled.
298 */
299
300#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
301#define CPU_BIG_ENDIAN                           TRUE
302#define CPU_LITTLE_ENDIAN                        FALSE
303
304/*
305 *  The following defines the number of bits actually used in the
306 *  interrupt field of the task mode.  How those bits map to the
307 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
308 */
309
310#define CPU_MODES_INTERRUPT_MASK   0x00000001
311
312/*
313 *  Processor defined structures
314 *
315 *  Examples structures include the descriptor tables from the i386
316 *  and the processor control structure on the i960ca.
317 */
318
319/* may need to put some structures here.  */
320
321/*
322 * Contexts
323 *
324 *  Generally there are 2 types of context to save.
325 *     1. Interrupt registers to save
326 *     2. Task level registers to save
327 *
328 *  This means we have the following 3 context items:
329 *     1. task level context stuff::  Context_Control
330 *     2. floating point task stuff:: Context_Control_fp
331 *     3. special interrupt level context :: Context_Control_interrupt
332 *
333 *  On some processors, it is cost-effective to save only the callee
334 *  preserved registers during a task context switch.  This means
335 *  that the ISR code needs to save those registers which do not
336 *  persist across function calls.  It is not mandatory to make this
337 *  distinctions between the caller/callee saves registers for the
338 *  purpose of minimizing context saved during task switch and on interrupts.
339 *  If the cost of saving extra registers is minimal, simplicity is the
340 *  choice.  Save the same context on interrupt entry as for tasks in
341 *  this case.
342 *
343 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
344 *  care should be used in designing the context area.
345 *
346 *  On some CPUs with hardware floating point support, the Context_Control_fp
347 *  structure will not be used or it simply consist of an array of a
348 *  fixed number of bytes.   This is done when the floating point context
349 *  is dumped by a "FP save context" type instruction and the format
350 *  is not really defined by the CPU.  In this case, there is no need
351 *  to figure out the exact format -- only the size.  Of course, although
352 *  this is enough information for RTEMS, it is probably not enough for
353 *  a debugger such as gdb.  But that is another problem.
354 */
355
356/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
357typedef struct {
358#if __mips == 1
359    unsigned32 s0;
360    unsigned32 s1;
361    unsigned32 s2;
362    unsigned32 s3;
363    unsigned32 s4;
364    unsigned32 s5;
365    unsigned32 s6;
366    unsigned32 s7;
367    unsigned32 sp;
368    unsigned32 fp;
369    unsigned32 ra;
370    unsigned32 c0_sr;
371    unsigned32 c0_epc;
372#else
373    unsigned64 s0;
374    unsigned64 s1;
375    unsigned64 s2;
376    unsigned64 s3;
377    unsigned64 s4;
378    unsigned64 s5;
379    unsigned64 s6;
380    unsigned64 s7;
381    unsigned64 sp;
382    unsigned64 fp;
383    unsigned64 ra;
384    unsigned64 c0_sr;
385    unsigned64 c0_epc;
386#endif
387} Context_Control;
388
389/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
390typedef struct {
391    unsigned32      fp0;
392    unsigned32      fp1;
393    unsigned32      fp2;
394    unsigned32      fp3;
395    unsigned32      fp4;
396    unsigned32      fp5;
397    unsigned32      fp6;
398    unsigned32      fp7;
399    unsigned32      fp8;
400    unsigned32      fp9;
401    unsigned32      fp10;
402    unsigned32      fp11;
403    unsigned32      fp12;
404    unsigned32      fp13;
405    unsigned32      fp14;
406    unsigned32      fp15;
407    unsigned32      fp16;
408    unsigned32      fp17;
409    unsigned32      fp18;
410    unsigned32      fp19;
411    unsigned32      fp20;
412    unsigned32      fp21;
413    unsigned32      fp22;
414    unsigned32      fp23;
415    unsigned32      fp24;
416    unsigned32      fp25;
417    unsigned32      fp26;
418    unsigned32      fp27;
419    unsigned32      fp28;
420    unsigned32      fp29;
421    unsigned32      fp30;
422    unsigned32      fp31;
423} Context_Control_fp;
424
425typedef struct {
426    unsigned32 special_interrupt_register;
427} CPU_Interrupt_frame;
428
429
430/*
431 *  The following table contains the information required to configure
432 *  the mips processor specific parameters.
433 */
434
435typedef struct {
436  void       (*pretasking_hook)( void );
437  void       (*predriver_hook)( void );
438  void       (*postdriver_hook)( void );
439  void       (*idle_task)( void );
440  boolean      do_zero_of_workspace;
441  unsigned32   idle_task_stack_size;
442  unsigned32   interrupt_stack_size;
443  unsigned32   extra_mpci_receive_server_stack;
444  void *     (*stack_allocate_hook)( unsigned32 );
445  void       (*stack_free_hook)( void* );
446  /* end of fields required on all CPUs */
447
448  unsigned32   clicks_per_microsecond;
449}   rtems_cpu_table;
450
451/*
452 *  Macros to access required entires in the CPU Table are in
453 *  the file rtems/system.h.
454 */
455
456/*
457 *  Macros to access MIPS specific additions to the CPU Table
458 */
459
460#define rtems_cpu_configuration_get_clicks_per_microsecond() \
461   (_CPU_Table.clicks_per_microsecond)
462
463/*
464 *  This variable is optional.  It is used on CPUs on which it is difficult
465 *  to generate an "uninitialized" FP context.  It is filled in by
466 *  _CPU_Initialize and copied into the task's FP context area during
467 *  _CPU_Context_Initialize.
468 */
469
470SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
471
472/*
473 *  On some CPUs, RTEMS supports a software managed interrupt stack.
474 *  This stack is allocated by the Interrupt Manager and the switch
475 *  is performed in _ISR_Handler.  These variables contain pointers
476 *  to the lowest and highest addresses in the chunk of memory allocated
477 *  for the interrupt stack.  Since it is unknown whether the stack
478 *  grows up or down (in general), this give the CPU dependent
479 *  code the option of picking the version it wants to use.
480 *
481 *  NOTE: These two variables are required if the macro
482 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
483 */
484
485SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
486SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
487
488/*
489 *  With some compilation systems, it is difficult if not impossible to
490 *  call a high-level language routine from assembly language.  This
491 *  is especially true of commercial Ada compilers and name mangling
492 *  C++ ones.  This variable can be optionally defined by the CPU porter
493 *  and contains the address of the routine _Thread_Dispatch.  This
494 *  can make it easier to invoke that routine at the end of the interrupt
495 *  sequence (if a dispatch is necessary).
496 */
497
498SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
499
500/*
501 *  Nothing prevents the porter from declaring more CPU specific variables.
502 */
503
504/* XXX: if needed, put more variables here */
505
506/*
507 *  The size of the floating point context area.  On some CPUs this
508 *  will not be a "sizeof" because the format of the floating point
509 *  area is not defined -- only the size is.  This is usually on
510 *  CPUs with a "floating point save context" instruction.
511 */
512
513#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
514
515/*
516 *  Amount of extra stack (above minimum stack size) required by
517 *  system initialization thread.  Remember that in a multiprocessor
518 *  system the system intialization thread becomes the MP server thread.
519 */
520
521#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
522
523/*
524 *  This defines the number of entries in the ISR_Vector_table managed
525 *  by RTEMS.
526 */
527
528extern unsigned int mips_interrupt_number_of_vectors;
529#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
530#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
531
532/*
533 *  Should be large enough to run all RTEMS tests.  This insures
534 *  that a "reasonable" small application should not have any problems.
535 */
536
537#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
538
539/*
540 *  CPU's worst alignment requirement for data types on a byte boundary.  This
541 *  alignment does not take into account the requirements for the stack.
542 */
543
544#define CPU_ALIGNMENT              8
545
546/*
547 *  This number corresponds to the byte alignment requirement for the
548 *  heap handler.  This alignment requirement may be stricter than that
549 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
550 *  common for the heap to follow the same alignment requirement as
551 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
552 *  then this should be set to CPU_ALIGNMENT.
553 *
554 *  NOTE:  This does not have to be a power of 2.  It does have to
555 *         be greater or equal to than CPU_ALIGNMENT.
556 */
557
558#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
559
560/*
561 *  This number corresponds to the byte alignment requirement for memory
562 *  buffers allocated by the partition manager.  This alignment requirement
563 *  may be stricter than that for the data types alignment specified by
564 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
565 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
566 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
567 *
568 *  NOTE:  This does not have to be a power of 2.  It does have to
569 *         be greater or equal to than CPU_ALIGNMENT.
570 */
571
572#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
573
574/*
575 *  This number corresponds to the byte alignment requirement for the
576 *  stack.  This alignment requirement may be stricter than that for the
577 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
578 *  is strict enough for the stack, then this should be set to 0.
579 *
580 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
581 */
582
583#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
584
585/*
586 *  ISR handler macros
587 */
588
589/*
590 *  Support routine to initialize the RTEMS vector table after it is allocated.
591 */
592
593#define _CPU_Initialize_vectors()
594
595/*
596 *  Disable all interrupts for an RTEMS critical section.  The previous
597 *  level is returned in _level.
598 */
599
600#define _CPU_ISR_Disable( _level ) \
601  do { \
602    mips_get_sr( _level ); \
603    mips_set_sr( (_level) & ~SR_IEC ); \
604  } while(0)
605
606/*
607 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
608 *  This indicates the end of an RTEMS critical section.  The parameter
609 *  _level is not modified.
610 */
611
612#define _CPU_ISR_Enable( _level )  \
613  do { \
614    mips_set_sr(_level); \
615  } while(0)
616
617/*
618 *  This temporarily restores the interrupt to _level before immediately
619 *  disabling them again.  This is used to divide long RTEMS critical
620 *  sections into two or more parts.  The parameter _level is not
621 * modified.
622 */
623
624#define _CPU_ISR_Flash( _xlevel ) \
625  do { \
626    unsigned int _scratch; \
627    _CPU_ISR_Enable( _xlevel ); \
628    _CPU_ISR_Disable( _scratch ); \
629  } while(0)
630
631/*
632 *  Map interrupt level in task mode onto the hardware that the CPU
633 *  actually provides.  Currently, interrupt levels which do not
634 *  map onto the CPU in a generic fashion are undefined.  Someday,
635 *  it would be nice if these were "mapped" by the application
636 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
637 *  8 - 255 would be available for bsp/application specific meaning.
638 *  This could be used to manage a programmable interrupt controller
639 *  via the rtems_task_mode directive.
640 *
641 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
642 *  manipulates the IEC.
643 */
644
645#if __mips == 3
646extern void _CPU_ISR_Set_level( unsigned32 _new_level );
647
648unsigned32 _CPU_ISR_Get_level( void ); /* in cpu_asm.S */
649#elif __mips == 1
650
651#define _CPU_ISR_Set_level( _new_level ) \
652  do { \
653    unsigned int _sr; \
654    mips_get_sr(_sr); \
655    (_sr) &= ~SR_IEC;                    /* clear the IEC bit */ \
656    if ( !(_new_level) ) (_sr) |= SR_IEC; /* enable interrupts */ \
657    mips_set_sr(_sr); \
658  } while (0)
659
660unsigned32 _CPU_ISR_Get_level( void );  /* in cpu.c */
661#else
662#error "CPU ISR level: unknown MIPS level for SR handling"
663#endif
664
665/* end of ISR handler macros */
666
667/* Context handler macros */
668
669/*
670 *  Initialize the context to a state suitable for starting a
671 *  task after a context restore operation.  Generally, this
672 *  involves:
673 *
674 *     - setting a starting address
675 *     - preparing the stack
676 *     - preparing the stack and frame pointers
677 *     - setting the proper interrupt level in the context
678 *     - initializing the floating point context
679 *
680 *  This routine generally does not set any unnecessary register
681 *  in the context.  The state of the "general data" registers is
682 *  undefined at task start time.
683 *
684 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
685 *        point thread.  This is typically only used on CPUs where the
686 *        FPU may be easily disabled by software such as on the SPARC
687 *        where the PSR contains an enable FPU bit.
688 */
689
690#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
691                                 _isr, _entry_point, _is_fp ) \
692  { \
693        unsigned32 _stack_tmp = (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
694        _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
695        (_the_context)->sp = _stack_tmp; \
696        (_the_context)->fp = _stack_tmp; \
697        (_the_context)->ra = (unsigned64)_entry_point; \
698        if (_isr) (_the_context)->c0_sr = 0xff00; \
699        else      (_the_context)->c0_sr = 0xff01; \
700  }
701
702/*
703 *  This routine is responsible for somehow restarting the currently
704 *  executing task.  If you are lucky, then all that is necessary
705 *  is restoring the context.  Otherwise, there will need to be
706 *  a special assembly routine which does something special in this
707 *  case.  Context_Restore should work most of the time.  It will
708 *  not work if restarting self conflicts with the stack frame
709 *  assumptions of restoring a context.
710 */
711
712#define _CPU_Context_Restart_self( _the_context ) \
713   _CPU_Context_restore( (_the_context) );
714
715/*
716 *  The purpose of this macro is to allow the initial pointer into
717 *  A floating point context area (used to save the floating point
718 *  context) to be at an arbitrary place in the floating point
719 *  context area.
720 *
721 *  This is necessary because some FP units are designed to have
722 *  their context saved as a stack which grows into lower addresses.
723 *  Other FP units can be saved by simply moving registers into offsets
724 *  from the base of the context area.  Finally some FP units provide
725 *  a "dump context" instruction which could fill in from high to low
726 *  or low to high based on the whim of the CPU designers.
727 */
728
729#define _CPU_Context_Fp_start( _base, _offset ) \
730   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
731
732/*
733 *  This routine initializes the FP context area passed to it to.
734 *  There are a few standard ways in which to initialize the
735 *  floating point context.  The code included for this macro assumes
736 *  that this is a CPU in which a "initial" FP context was saved into
737 *  _CPU_Null_fp_context and it simply copies it to the destination
738 *  context passed to it.
739 *
740 *  Other models include (1) not doing anything, and (2) putting
741 *  a "null FP status word" in the correct place in the FP context.
742 */
743
744#define _CPU_Context_Initialize_fp( _destination ) \
745  { \
746   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
747  }
748
749/* end of Context handler macros */
750
751/* Fatal Error manager macros */
752
753/*
754 *  This routine copies _error into a known place -- typically a stack
755 *  location or a register, optionally disables interrupts, and
756 *  halts/stops the CPU.
757 */
758
759void mips_fatal_error ( int error );
760
761#define _CPU_Fatal_halt( _error ) \
762  do { \
763    unsigned int _level; \
764    _CPU_ISR_Disable(_level); \
765    mips_fatal_error(_error); \
766  } while (0)
767
768/* end of Fatal Error manager macros */
769
770/* Bitfield handler macros */
771
772/*
773 *  This routine sets _output to the bit number of the first bit
774 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
775 *  This type may be either 16 or 32 bits wide although only the 16
776 *  least significant bits will be used.
777 *
778 *  There are a number of variables in using a "find first bit" type
779 *  instruction.
780 *
781 *    (1) What happens when run on a value of zero?
782 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
783 *    (3) The numbering may be zero or one based.
784 *    (4) The "find first bit" instruction may search from MSB or LSB.
785 *
786 *  RTEMS guarantees that (1) will never happen so it is not a concern.
787 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
788 *  _CPU_Priority_bits_index().  These three form a set of routines
789 *  which must logically operate together.  Bits in the _value are
790 *  set and cleared based on masks built by _CPU_Priority_mask().
791 *  The basic major and minor values calculated by _Priority_Major()
792 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
793 *  to properly range between the values returned by the "find first bit"
794 *  instruction.  This makes it possible for _Priority_Get_highest() to
795 *  calculate the major and directly index into the minor table.
796 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
797 *  is the first bit found.
798 *
799 *  This entire "find first bit" and mapping process depends heavily
800 *  on the manner in which a priority is broken into a major and minor
801 *  components with the major being the 4 MSB of a priority and minor
802 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
803 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
804 *  to the lowest priority.
805 *
806 *  If your CPU does not have a "find first bit" instruction, then
807 *  there are ways to make do without it.  Here are a handful of ways
808 *  to implement this in software:
809 *
810 *    - a series of 16 bit test instructions
811 *    - a "binary search using if's"
812 *    - _number = 0
813 *      if _value > 0x00ff
814 *        _value >>=8
815 *        _number = 8;
816 *
817 *      if _value > 0x0000f
818 *        _value >=8
819 *        _number += 4
820 *
821 *      _number += bit_set_table[ _value ]
822 *
823 *    where bit_set_table[ 16 ] has values which indicate the first
824 *      bit set
825 */
826
827#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
828#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
829
830#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
831
832#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
833  { \
834    (_output) = 0;   /* do something to prevent warnings */ \
835  }
836
837#endif
838
839/* end of Bitfield handler macros */
840
841/*
842 *  This routine builds the mask which corresponds to the bit fields
843 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
844 *  for that routine.
845 */
846
847#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
848
849#define _CPU_Priority_Mask( _bit_number ) \
850  ( 1 << (_bit_number) )
851
852#endif
853
854/*
855 *  This routine translates the bit numbers returned by
856 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
857 *  a major or minor component of a priority.  See the discussion
858 *  for that routine.
859 */
860
861#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
862
863#define _CPU_Priority_bits_index( _priority ) \
864  (_priority)
865
866#endif
867
868/* end of Priority handler macros */
869
870/* functions */
871
872/*
873 *  _CPU_Initialize
874 *
875 *  This routine performs CPU dependent initialization.
876 */
877
878void _CPU_Initialize(
879  rtems_cpu_table  *cpu_table,
880  void      (*thread_dispatch)
881);
882
883/*
884 *  _CPU_ISR_install_raw_handler
885 *
886 *  This routine installs a "raw" interrupt handler directly into the
887 *  processor's vector table.
888 */
889 
890void _CPU_ISR_install_raw_handler(
891  unsigned32  vector,
892  proc_ptr    new_handler,
893  proc_ptr   *old_handler
894);
895
896/*
897 *  _CPU_ISR_install_vector
898 *
899 *  This routine installs an interrupt vector.
900 */
901
902void _CPU_ISR_install_vector(
903  unsigned32  vector,
904  proc_ptr    new_handler,
905  proc_ptr   *old_handler
906);
907
908/*
909 *  _CPU_Install_interrupt_stack
910 *
911 *  This routine installs the hardware interrupt stack pointer.
912 *
913 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
914 *         is TRUE.
915 */
916
917void _CPU_Install_interrupt_stack( void );
918
919/*
920 *  _CPU_Internal_threads_Idle_thread_body
921 *
922 *  This routine is the CPU dependent IDLE thread body.
923 *
924 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
925 *         is TRUE.
926 */
927
928void _CPU_Thread_Idle_body( void );
929
930/*
931 *  _CPU_Context_switch
932 *
933 *  This routine switches from the run context to the heir context.
934 */
935
936void _CPU_Context_switch(
937  Context_Control  *run,
938  Context_Control  *heir
939);
940
941/*
942 *  _CPU_Context_restore
943 *
944 *  This routine is generally used only to restart self in an
945 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
946 *
947 *  NOTE: May be unnecessary to reload some registers.
948 */
949
950void _CPU_Context_restore(
951  Context_Control *new_context
952);
953
954/*
955 *  _CPU_Context_save_fp
956 *
957 *  This routine saves the floating point context passed to it.
958 */
959
960void _CPU_Context_save_fp(
961  void **fp_context_ptr
962);
963
964/*
965 *  _CPU_Context_restore_fp
966 *
967 *  This routine restores the floating point context passed to it.
968 */
969
970void _CPU_Context_restore_fp(
971  void **fp_context_ptr
972);
973
974/*  The following routine swaps the endian format of an unsigned int.
975 *  It must be static because it is referenced indirectly.
976 *
977 *  This version will work on any processor, but if there is a better
978 *  way for your CPU PLEASE use it.  The most common way to do this is to:
979 *
980 *     swap least significant two bytes with 16-bit rotate
981 *     swap upper and lower 16-bits
982 *     swap most significant two bytes with 16-bit rotate
983 *
984 *  Some CPUs have special instructions which swap a 32-bit quantity in
985 *  a single instruction (e.g. i486).  It is probably best to avoid
986 *  an "endian swapping control bit" in the CPU.  One good reason is
987 *  that interrupts would probably have to be disabled to insure that
988 *  an interrupt does not try to access the same "chunk" with the wrong
989 *  endian.  Another good reason is that on some CPUs, the endian bit
990 *  endianness for ALL fetches -- both code and data -- so the code
991 *  will be fetched incorrectly.
992 */
993 
994static inline unsigned int CPU_swap_u32(
995  unsigned int value
996)
997{
998  unsigned32 byte1, byte2, byte3, byte4, swapped;
999 
1000  byte4 = (value >> 24) & 0xff;
1001  byte3 = (value >> 16) & 0xff;
1002  byte2 = (value >> 8)  & 0xff;
1003  byte1 =  value        & 0xff;
1004 
1005  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1006  return( swapped );
1007}
1008
1009#define CPU_swap_u16( value ) \
1010  (((value&0xff) << 8) | ((value >> 8)&0xff))
1011
1012#ifdef __cplusplus
1013}
1014#endif
1015
1016#endif
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