source: rtems/c/src/exec/score/cpu/mips/rtems/score/cpu.h @ 1800f717

4.104.114.84.95
Last change on this file since 1800f717 was 1800f717, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 8, 2001 at 6:16:51 PM

2001-01-08 Joel Sherrill <joel@…>

  • idtcpu.h: Commented out definition of "wait". It was stupid to use such a common word as a macro.
  • rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
  • rtems/score/mips.h: Added include of <idtcpu.h>.
  • rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
  • Property mode set to 100644
File size: 32.2 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the IDT 4650
4 *  processor.
5 *
6 *  Author:     Craig Lebakken <craigl@transition.com>
7 *
8 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of Transition Networks not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      Transition Networks makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
22 *
23 *  COPYRIGHT (c) 1989-1999.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.OARcorp.com/rtems/license.html.
29 *
30 *  $Id$
31 */
32/* @(#)cpu.h       08/29/96     1.7 */
33
34#ifndef __CPU_h
35#define __CPU_h
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41#include <rtems/score/mips.h>       /* pick up machine definitions */
42#ifndef ASM
43#include <rtems/score/mipstypes.h>
44#endif
45
46/* conditional compilation parameters */
47
48/*
49 *  Should the calls to _Thread_Enable_dispatch be inlined?
50 *
51 *  If TRUE, then they are inlined.
52 *  If FALSE, then a subroutine call is made.
53 *
54 *  Basically this is an example of the classic trade-off of size
55 *  versus speed.  Inlining the call (TRUE) typically increases the
56 *  size of RTEMS while speeding up the enabling of dispatching.
57 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
58 *  only be 0 or 1 unless you are in an interrupt handler and that
59 *  interrupt handler invokes the executive.]  When not inlined
60 *  something calls _Thread_Enable_dispatch which in turns calls
61 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
62 *  one subroutine call is avoided entirely.]
63 */
64
65#define CPU_INLINE_ENABLE_DISPATCH       TRUE
66
67/*
68 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
69 *  be unrolled one time?  In unrolled each iteration of the loop examines
70 *  two "nodes" on the chain being searched.  Otherwise, only one node
71 *  is examined per iteration.
72 *
73 *  If TRUE, then the loops are unrolled.
74 *  If FALSE, then the loops are not unrolled.
75 *
76 *  The primary factor in making this decision is the cost of disabling
77 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
78 *  body of the loop.  On some CPUs, the flash is more expensive than
79 *  one iteration of the loop body.  In this case, it might be desirable
80 *  to unroll the loop.  It is important to note that on some CPUs, this
81 *  code is the longest interrupt disable period in RTEMS.  So it is
82 *  necessary to strike a balance when setting this parameter.
83 */
84
85#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
86
87/*
88 *  Does RTEMS manage a dedicated interrupt stack in software?
89 *
90 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
91 *  If FALSE, nothing is done.
92 *
93 *  If the CPU supports a dedicated interrupt stack in hardware,
94 *  then it is generally the responsibility of the BSP to allocate it
95 *  and set it up.
96 *
97 *  If the CPU does not support a dedicated interrupt stack, then
98 *  the porter has two options: (1) execute interrupts on the
99 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
100 *  interrupt stack.
101 *
102 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
103 *
104 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
105 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
106 *  possible that both are FALSE for a particular CPU.  Although it
107 *  is unclear what that would imply about the interrupt processing
108 *  procedure on that CPU.
109 */
110
111#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
112
113/*
114 *  Does this CPU have hardware support for a dedicated interrupt stack?
115 *
116 *  If TRUE, then it must be installed during initialization.
117 *  If FALSE, then no installation is performed.
118 *
119 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
120 *
121 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
122 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
123 *  possible that both are FALSE for a particular CPU.  Although it
124 *  is unclear what that would imply about the interrupt processing
125 *  procedure on that CPU.
126 */
127
128#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
129
130/*
131 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
132 *
133 *  If TRUE, then the memory is allocated during initialization.
134 *  If FALSE, then the memory is allocated during initialization.
135 *
136 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
137 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
138 */
139
140#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
141
142/*
143 *  Does the RTEMS invoke the user's ISR with the vector number and
144 *  a pointer to the saved interrupt frame (1) or just the vector
145 *  number (0)?
146 */
147
148#define CPU_ISR_PASSES_FRAME_POINTER 0
149
150/*
151 *  Does the CPU have hardware floating point?
152 *
153 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
154 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
155 *
156 *  If there is a FP coprocessor such as the i387 or mc68881, then
157 *  the answer is TRUE.
158 *
159 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
160 *  It indicates whether or not this CPU model has FP support.  For
161 *  example, it would be possible to have an i386_nofp CPU model
162 *  which set this to false to indicate that you have an i386 without
163 *  an i387 and wish to leave floating point support out of RTEMS.
164 */
165
166#if ( MIPS_HAS_FPU == 1 )
167#define CPU_HARDWARE_FP     TRUE
168#else
169#define CPU_HARDWARE_FP     FALSE
170#endif
171
172/*
173 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
174 *
175 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
176 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
177 *
178 *  So far, the only CPU in which this option has been used is the
179 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
180 *  floating point registers to perform integer multiplies.  If
181 *  a function which you would not think utilize the FP unit DOES,
182 *  then one can not easily predict which tasks will use the FP hardware.
183 *  In this case, this option should be TRUE.
184 *
185 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
186 */
187
188#define CPU_ALL_TASKS_ARE_FP    FALSE
189
190/*
191 *  Should the IDLE task have a floating point context?
192 *
193 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
194 *  and it has a floating point context which is switched in and out.
195 *  If FALSE, then the IDLE task does not have a floating point context.
196 *
197 *  Setting this to TRUE negatively impacts the time required to preempt
198 *  the IDLE task from an interrupt because the floating point context
199 *  must be saved as part of the preemption.
200 */
201
202#define CPU_IDLE_TASK_IS_FP      FALSE
203
204/*
205 *  Should the saving of the floating point registers be deferred
206 *  until a context switch is made to another different floating point
207 *  task?
208 *
209 *  If TRUE, then the floating point context will not be stored until
210 *  necessary.  It will remain in the floating point registers and not
211 *  disturned until another floating point task is switched to.
212 *
213 *  If FALSE, then the floating point context is saved when a floating
214 *  point task is switched out and restored when the next floating point
215 *  task is restored.  The state of the floating point registers between
216 *  those two operations is not specified.
217 *
218 *  If the floating point context does NOT have to be saved as part of
219 *  interrupt dispatching, then it should be safe to set this to TRUE.
220 *
221 *  Setting this flag to TRUE results in using a different algorithm
222 *  for deciding when to save and restore the floating point context.
223 *  The deferred FP switch algorithm minimizes the number of times
224 *  the FP context is saved and restored.  The FP context is not saved
225 *  until a context switch is made to another, different FP task.
226 *  Thus in a system with only one FP task, the FP context will never
227 *  be saved or restored.
228 */
229
230#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
231
232/*
233 *  Does this port provide a CPU dependent IDLE task implementation?
234 *
235 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
236 *  must be provided and is the default IDLE thread body instead of
237 *  _Internal_threads_Idle_thread_body.
238 *
239 *  If FALSE, then use the generic IDLE thread body if the BSP does
240 *  not provide one.
241 *
242 *  This is intended to allow for supporting processors which have
243 *  a low power or idle mode.  When the IDLE thread is executed, then
244 *  the CPU can be powered down.
245 *
246 *  The order of precedence for selecting the IDLE thread body is:
247 *
248 *    1.  BSP provided
249 *    2.  CPU dependent (if provided)
250 *    3.  generic (if no BSP and no CPU dependent)
251 */
252
253/* we can use the low power wait instruction for the IDLE thread */
254#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
255
256/*
257 *  Does the stack grow up (toward higher addresses) or down
258 *  (toward lower addresses)?
259 *
260 *  If TRUE, then the grows upward.
261 *  If FALSE, then the grows toward smaller addresses.
262 */
263
264/* our stack grows down */
265#define CPU_STACK_GROWS_UP               FALSE
266
267/*
268 *  The following is the variable attribute used to force alignment
269 *  of critical RTEMS structures.  On some processors it may make
270 *  sense to have these aligned on tighter boundaries than
271 *  the minimum requirements of the compiler in order to have as
272 *  much of the critical data area as possible in a cache line.
273 *
274 *  The placement of this macro in the declaration of the variables
275 *  is based on the syntactically requirements of the GNU C
276 *  "__attribute__" extension.  For example with GNU C, use
277 *  the following to force a structures to a 32 byte boundary.
278 *
279 *      __attribute__ ((aligned (32)))
280 *
281 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
282 *         To benefit from using this, the data must be heavily
283 *         used so it will stay in the cache and used frequently enough
284 *         in the executive to justify turning this on.
285 */
286
287/* our cache line size is 16 bytes */
288#if __GNUC__
289#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
290#else
291#define CPU_STRUCTURE_ALIGNMENT
292#endif
293
294/*
295 *  Define what is required to specify how the network to host conversion
296 *  routines are handled.
297 */
298
299#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
300#define CPU_BIG_ENDIAN                           TRUE
301#define CPU_LITTLE_ENDIAN                        FALSE
302
303/*
304 *  The following defines the number of bits actually used in the
305 *  interrupt field of the task mode.  How those bits map to the
306 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
307 */
308
309#define CPU_MODES_INTERRUPT_MASK   0x00000001
310
311/*
312 *  Processor defined structures
313 *
314 *  Examples structures include the descriptor tables from the i386
315 *  and the processor control structure on the i960ca.
316 */
317
318/* may need to put some structures here.  */
319
320/*
321 * Contexts
322 *
323 *  Generally there are 2 types of context to save.
324 *     1. Interrupt registers to save
325 *     2. Task level registers to save
326 *
327 *  This means we have the following 3 context items:
328 *     1. task level context stuff::  Context_Control
329 *     2. floating point task stuff:: Context_Control_fp
330 *     3. special interrupt level context :: Context_Control_interrupt
331 *
332 *  On some processors, it is cost-effective to save only the callee
333 *  preserved registers during a task context switch.  This means
334 *  that the ISR code needs to save those registers which do not
335 *  persist across function calls.  It is not mandatory to make this
336 *  distinctions between the caller/callee saves registers for the
337 *  purpose of minimizing context saved during task switch and on interrupts.
338 *  If the cost of saving extra registers is minimal, simplicity is the
339 *  choice.  Save the same context on interrupt entry as for tasks in
340 *  this case.
341 *
342 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
343 *  care should be used in designing the context area.
344 *
345 *  On some CPUs with hardware floating point support, the Context_Control_fp
346 *  structure will not be used or it simply consist of an array of a
347 *  fixed number of bytes.   This is done when the floating point context
348 *  is dumped by a "FP save context" type instruction and the format
349 *  is not really defined by the CPU.  In this case, there is no need
350 *  to figure out the exact format -- only the size.  Of course, although
351 *  this is enough information for RTEMS, it is probably not enough for
352 *  a debugger such as gdb.  But that is another problem.
353 */
354
355/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
356typedef struct {
357#if __mips == 1
358    unsigned32 s0;
359    unsigned32 s1;
360    unsigned32 s2;
361    unsigned32 s3;
362    unsigned32 s4;
363    unsigned32 s5;
364    unsigned32 s6;
365    unsigned32 s7;
366    unsigned32 sp;
367    unsigned32 fp;
368    unsigned32 ra;
369    unsigned32 c0_sr;
370    unsigned32 c0_epc;
371#else
372    unsigned64 s0;
373    unsigned64 s1;
374    unsigned64 s2;
375    unsigned64 s3;
376    unsigned64 s4;
377    unsigned64 s5;
378    unsigned64 s6;
379    unsigned64 s7;
380    unsigned64 sp;
381    unsigned64 fp;
382    unsigned64 ra;
383    unsigned64 c0_sr;
384    unsigned64 c0_epc;
385#endif
386} Context_Control;
387
388/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
389typedef struct {
390    unsigned32      fp0;
391    unsigned32      fp1;
392    unsigned32      fp2;
393    unsigned32      fp3;
394    unsigned32      fp4;
395    unsigned32      fp5;
396    unsigned32      fp6;
397    unsigned32      fp7;
398    unsigned32      fp8;
399    unsigned32      fp9;
400    unsigned32      fp10;
401    unsigned32      fp11;
402    unsigned32      fp12;
403    unsigned32      fp13;
404    unsigned32      fp14;
405    unsigned32      fp15;
406    unsigned32      fp16;
407    unsigned32      fp17;
408    unsigned32      fp18;
409    unsigned32      fp19;
410    unsigned32      fp20;
411    unsigned32      fp21;
412    unsigned32      fp22;
413    unsigned32      fp23;
414    unsigned32      fp24;
415    unsigned32      fp25;
416    unsigned32      fp26;
417    unsigned32      fp27;
418    unsigned32      fp28;
419    unsigned32      fp29;
420    unsigned32      fp30;
421    unsigned32      fp31;
422} Context_Control_fp;
423
424typedef struct {
425    unsigned32 special_interrupt_register;
426} CPU_Interrupt_frame;
427
428
429/*
430 *  The following table contains the information required to configure
431 *  the mips processor specific parameters.
432 */
433
434typedef struct {
435  void       (*pretasking_hook)( void );
436  void       (*predriver_hook)( void );
437  void       (*postdriver_hook)( void );
438  void       (*idle_task)( void );
439  boolean      do_zero_of_workspace;
440  unsigned32   idle_task_stack_size;
441  unsigned32   interrupt_stack_size;
442  unsigned32   extra_mpci_receive_server_stack;
443  void *     (*stack_allocate_hook)( unsigned32 );
444  void       (*stack_free_hook)( void* );
445  /* end of fields required on all CPUs */
446
447  unsigned32   clicks_per_microsecond;
448}   rtems_cpu_table;
449
450/*
451 *  Macros to access required entires in the CPU Table are in
452 *  the file rtems/system.h.
453 */
454
455/*
456 *  Macros to access MIPS specific additions to the CPU Table
457 */
458
459#define rtems_cpu_configuration_get_clicks_per_microsecond() \
460   (_CPU_Table.clicks_per_microsecond)
461
462/*
463 *  This variable is optional.  It is used on CPUs on which it is difficult
464 *  to generate an "uninitialized" FP context.  It is filled in by
465 *  _CPU_Initialize and copied into the task's FP context area during
466 *  _CPU_Context_Initialize.
467 */
468
469SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
470
471/*
472 *  On some CPUs, RTEMS supports a software managed interrupt stack.
473 *  This stack is allocated by the Interrupt Manager and the switch
474 *  is performed in _ISR_Handler.  These variables contain pointers
475 *  to the lowest and highest addresses in the chunk of memory allocated
476 *  for the interrupt stack.  Since it is unknown whether the stack
477 *  grows up or down (in general), this give the CPU dependent
478 *  code the option of picking the version it wants to use.
479 *
480 *  NOTE: These two variables are required if the macro
481 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
482 */
483
484SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
485SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
486
487/*
488 *  With some compilation systems, it is difficult if not impossible to
489 *  call a high-level language routine from assembly language.  This
490 *  is especially true of commercial Ada compilers and name mangling
491 *  C++ ones.  This variable can be optionally defined by the CPU porter
492 *  and contains the address of the routine _Thread_Dispatch.  This
493 *  can make it easier to invoke that routine at the end of the interrupt
494 *  sequence (if a dispatch is necessary).
495 */
496
497SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
498
499/*
500 *  Nothing prevents the porter from declaring more CPU specific variables.
501 */
502
503/* XXX: if needed, put more variables here */
504
505/*
506 *  The size of the floating point context area.  On some CPUs this
507 *  will not be a "sizeof" because the format of the floating point
508 *  area is not defined -- only the size is.  This is usually on
509 *  CPUs with a "floating point save context" instruction.
510 */
511
512#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
513
514/*
515 *  Amount of extra stack (above minimum stack size) required by
516 *  system initialization thread.  Remember that in a multiprocessor
517 *  system the system intialization thread becomes the MP server thread.
518 */
519
520#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
521
522/*
523 *  This defines the number of entries in the ISR_Vector_table managed
524 *  by RTEMS.
525 */
526
527extern unsigned int mips_interrupt_number_of_vectors;
528#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
529#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
530
531/*
532 *  Should be large enough to run all RTEMS tests.  This insures
533 *  that a "reasonable" small application should not have any problems.
534 */
535
536#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
537
538/*
539 *  CPU's worst alignment requirement for data types on a byte boundary.  This
540 *  alignment does not take into account the requirements for the stack.
541 */
542
543#define CPU_ALIGNMENT              8
544
545/*
546 *  This number corresponds to the byte alignment requirement for the
547 *  heap handler.  This alignment requirement may be stricter than that
548 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
549 *  common for the heap to follow the same alignment requirement as
550 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
551 *  then this should be set to CPU_ALIGNMENT.
552 *
553 *  NOTE:  This does not have to be a power of 2.  It does have to
554 *         be greater or equal to than CPU_ALIGNMENT.
555 */
556
557#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
558
559/*
560 *  This number corresponds to the byte alignment requirement for memory
561 *  buffers allocated by the partition manager.  This alignment requirement
562 *  may be stricter than that for the data types alignment specified by
563 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
564 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
565 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
566 *
567 *  NOTE:  This does not have to be a power of 2.  It does have to
568 *         be greater or equal to than CPU_ALIGNMENT.
569 */
570
571#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
572
573/*
574 *  This number corresponds to the byte alignment requirement for the
575 *  stack.  This alignment requirement may be stricter than that for the
576 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
577 *  is strict enough for the stack, then this should be set to 0.
578 *
579 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
580 */
581
582#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
583
584/*
585 *  ISR handler macros
586 */
587
588/*
589 *  Support routine to initialize the RTEMS vector table after it is allocated.
590 */
591
592#define _CPU_Initialize_vectors()
593
594/*
595 *  Disable all interrupts for an RTEMS critical section.  The previous
596 *  level is returned in _level.
597 */
598
599#define _CPU_ISR_Disable( _level ) \
600  do { \
601    mips_get_sr( _level ); \
602    mips_set_sr( (_level) & ~SR_IMASK ); \
603  } while(0)
604
605/*
606 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
607 *  This indicates the end of an RTEMS critical section.  The parameter
608 *  _level is not modified.
609 */
610
611#define _CPU_ISR_Enable( _level )  \
612  do { \
613    mips_set_sr(_level); \
614  } while(0)
615
616/*
617 *  This temporarily restores the interrupt to _level before immediately
618 *  disabling them again.  This is used to divide long RTEMS critical
619 *  sections into two or more parts.  The parameter _level is not
620 * modified.
621 */
622
623#define _CPU_ISR_Flash( _xlevel ) \
624  do { \
625    unsigned int _scratch; \
626    _CPU_ISR_Enable( _xlevel ); \
627    _CPU_ISR_Disable( _scratch ); \
628  } while(0)
629
630/*
631 *  Map interrupt level in task mode onto the hardware that the CPU
632 *  actually provides.  Currently, interrupt levels which do not
633 *  map onto the CPU in a generic fashion are undefined.  Someday,
634 *  it would be nice if these were "mapped" by the application
635 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
636 *  8 - 255 would be available for bsp/application specific meaning.
637 *  This could be used to manage a programmable interrupt controller
638 *  via the rtems_task_mode directive.
639 *
640 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
641 *  manipulates the IEC.
642 */
643
644#if __mips == 3
645extern void _CPU_ISR_Set_level( unsigned32 _new_level );
646
647unsigned32 _CPU_ISR_Get_level( void ); /* in cpu_asm.S */
648#elif __mips == 1
649
650#define _CPU_ISR_Set_level( _new_level ) \
651  do { \
652    unsigned int _sr; \
653    mips_get_sr(_sr); \
654    (_sr) &= ~SR_IEC;                    /* clear the IEC bit */ \
655    if ( !(_new_level) ) (_sr) |= SR_IEC; /* enable interrupts */ \
656    mips_set_sr(_sr); \
657  } while (0)
658
659unsigned32 _CPU_ISR_Get_level( void );  /* in cpu.c */
660#else
661#error "CPU ISR level: unknown MIPS level for SR handling"
662#endif
663
664/* end of ISR handler macros */
665
666/* Context handler macros */
667
668/*
669 *  Initialize the context to a state suitable for starting a
670 *  task after a context restore operation.  Generally, this
671 *  involves:
672 *
673 *     - setting a starting address
674 *     - preparing the stack
675 *     - preparing the stack and frame pointers
676 *     - setting the proper interrupt level in the context
677 *     - initializing the floating point context
678 *
679 *  This routine generally does not set any unnecessary register
680 *  in the context.  The state of the "general data" registers is
681 *  undefined at task start time.
682 *
683 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
684 *        point thread.  This is typically only used on CPUs where the
685 *        FPU may be easily disabled by software such as on the SPARC
686 *        where the PSR contains an enable FPU bit.
687 */
688
689#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
690                                 _isr, _entry_point, _is_fp ) \
691  { \
692        unsigned32 _stack_tmp = (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
693        _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
694        (_the_context)->sp = _stack_tmp; \
695        (_the_context)->fp = _stack_tmp; \
696        (_the_context)->ra = (unsigned64)_entry_point; \
697        if (_isr) (_the_context)->c0_sr = 0xff00; \
698        else      (_the_context)->c0_sr = 0xff01; \
699  }
700
701/*
702 *  This routine is responsible for somehow restarting the currently
703 *  executing task.  If you are lucky, then all that is necessary
704 *  is restoring the context.  Otherwise, there will need to be
705 *  a special assembly routine which does something special in this
706 *  case.  Context_Restore should work most of the time.  It will
707 *  not work if restarting self conflicts with the stack frame
708 *  assumptions of restoring a context.
709 */
710
711#define _CPU_Context_Restart_self( _the_context ) \
712   _CPU_Context_restore( (_the_context) );
713
714/*
715 *  The purpose of this macro is to allow the initial pointer into
716 *  A floating point context area (used to save the floating point
717 *  context) to be at an arbitrary place in the floating point
718 *  context area.
719 *
720 *  This is necessary because some FP units are designed to have
721 *  their context saved as a stack which grows into lower addresses.
722 *  Other FP units can be saved by simply moving registers into offsets
723 *  from the base of the context area.  Finally some FP units provide
724 *  a "dump context" instruction which could fill in from high to low
725 *  or low to high based on the whim of the CPU designers.
726 */
727
728#define _CPU_Context_Fp_start( _base, _offset ) \
729   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
730
731/*
732 *  This routine initializes the FP context area passed to it to.
733 *  There are a few standard ways in which to initialize the
734 *  floating point context.  The code included for this macro assumes
735 *  that this is a CPU in which a "initial" FP context was saved into
736 *  _CPU_Null_fp_context and it simply copies it to the destination
737 *  context passed to it.
738 *
739 *  Other models include (1) not doing anything, and (2) putting
740 *  a "null FP status word" in the correct place in the FP context.
741 */
742
743#define _CPU_Context_Initialize_fp( _destination ) \
744  { \
745   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
746  }
747
748/* end of Context handler macros */
749
750/* Fatal Error manager macros */
751
752/*
753 *  This routine copies _error into a known place -- typically a stack
754 *  location or a register, optionally disables interrupts, and
755 *  halts/stops the CPU.
756 */
757
758void mips_fatal_error ( int error );
759
760#define _CPU_Fatal_halt( _error ) \
761  do { \
762    unsigned int _level; \
763    _CPU_ISR_Disable(_level); \
764    mips_fatal_error(_error); \
765  } while (0)
766
767/* end of Fatal Error manager macros */
768
769/* Bitfield handler macros */
770
771/*
772 *  This routine sets _output to the bit number of the first bit
773 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
774 *  This type may be either 16 or 32 bits wide although only the 16
775 *  least significant bits will be used.
776 *
777 *  There are a number of variables in using a "find first bit" type
778 *  instruction.
779 *
780 *    (1) What happens when run on a value of zero?
781 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
782 *    (3) The numbering may be zero or one based.
783 *    (4) The "find first bit" instruction may search from MSB or LSB.
784 *
785 *  RTEMS guarantees that (1) will never happen so it is not a concern.
786 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
787 *  _CPU_Priority_bits_index().  These three form a set of routines
788 *  which must logically operate together.  Bits in the _value are
789 *  set and cleared based on masks built by _CPU_Priority_mask().
790 *  The basic major and minor values calculated by _Priority_Major()
791 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
792 *  to properly range between the values returned by the "find first bit"
793 *  instruction.  This makes it possible for _Priority_Get_highest() to
794 *  calculate the major and directly index into the minor table.
795 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
796 *  is the first bit found.
797 *
798 *  This entire "find first bit" and mapping process depends heavily
799 *  on the manner in which a priority is broken into a major and minor
800 *  components with the major being the 4 MSB of a priority and minor
801 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
802 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
803 *  to the lowest priority.
804 *
805 *  If your CPU does not have a "find first bit" instruction, then
806 *  there are ways to make do without it.  Here are a handful of ways
807 *  to implement this in software:
808 *
809 *    - a series of 16 bit test instructions
810 *    - a "binary search using if's"
811 *    - _number = 0
812 *      if _value > 0x00ff
813 *        _value >>=8
814 *        _number = 8;
815 *
816 *      if _value > 0x0000f
817 *        _value >=8
818 *        _number += 4
819 *
820 *      _number += bit_set_table[ _value ]
821 *
822 *    where bit_set_table[ 16 ] has values which indicate the first
823 *      bit set
824 */
825
826#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
827#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
828
829#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
830
831#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
832  { \
833    (_output) = 0;   /* do something to prevent warnings */ \
834  }
835
836#endif
837
838/* end of Bitfield handler macros */
839
840/*
841 *  This routine builds the mask which corresponds to the bit fields
842 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
843 *  for that routine.
844 */
845
846#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
847
848#define _CPU_Priority_Mask( _bit_number ) \
849  ( 1 << (_bit_number) )
850
851#endif
852
853/*
854 *  This routine translates the bit numbers returned by
855 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
856 *  a major or minor component of a priority.  See the discussion
857 *  for that routine.
858 */
859
860#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
861
862#define _CPU_Priority_bits_index( _priority ) \
863  (_priority)
864
865#endif
866
867/* end of Priority handler macros */
868
869/* functions */
870
871/*
872 *  _CPU_Initialize
873 *
874 *  This routine performs CPU dependent initialization.
875 */
876
877void _CPU_Initialize(
878  rtems_cpu_table  *cpu_table,
879  void      (*thread_dispatch)
880);
881
882/*
883 *  _CPU_ISR_install_raw_handler
884 *
885 *  This routine installs a "raw" interrupt handler directly into the
886 *  processor's vector table.
887 */
888 
889void _CPU_ISR_install_raw_handler(
890  unsigned32  vector,
891  proc_ptr    new_handler,
892  proc_ptr   *old_handler
893);
894
895/*
896 *  _CPU_ISR_install_vector
897 *
898 *  This routine installs an interrupt vector.
899 */
900
901void _CPU_ISR_install_vector(
902  unsigned32  vector,
903  proc_ptr    new_handler,
904  proc_ptr   *old_handler
905);
906
907/*
908 *  _CPU_Install_interrupt_stack
909 *
910 *  This routine installs the hardware interrupt stack pointer.
911 *
912 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
913 *         is TRUE.
914 */
915
916void _CPU_Install_interrupt_stack( void );
917
918/*
919 *  _CPU_Internal_threads_Idle_thread_body
920 *
921 *  This routine is the CPU dependent IDLE thread body.
922 *
923 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
924 *         is TRUE.
925 */
926
927void _CPU_Thread_Idle_body( void );
928
929/*
930 *  _CPU_Context_switch
931 *
932 *  This routine switches from the run context to the heir context.
933 */
934
935void _CPU_Context_switch(
936  Context_Control  *run,
937  Context_Control  *heir
938);
939
940/*
941 *  _CPU_Context_restore
942 *
943 *  This routine is generally used only to restart self in an
944 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
945 *
946 *  NOTE: May be unnecessary to reload some registers.
947 */
948
949void _CPU_Context_restore(
950  Context_Control *new_context
951);
952
953/*
954 *  _CPU_Context_save_fp
955 *
956 *  This routine saves the floating point context passed to it.
957 */
958
959void _CPU_Context_save_fp(
960  void **fp_context_ptr
961);
962
963/*
964 *  _CPU_Context_restore_fp
965 *
966 *  This routine restores the floating point context passed to it.
967 */
968
969void _CPU_Context_restore_fp(
970  void **fp_context_ptr
971);
972
973/*  The following routine swaps the endian format of an unsigned int.
974 *  It must be static because it is referenced indirectly.
975 *
976 *  This version will work on any processor, but if there is a better
977 *  way for your CPU PLEASE use it.  The most common way to do this is to:
978 *
979 *     swap least significant two bytes with 16-bit rotate
980 *     swap upper and lower 16-bits
981 *     swap most significant two bytes with 16-bit rotate
982 *
983 *  Some CPUs have special instructions which swap a 32-bit quantity in
984 *  a single instruction (e.g. i486).  It is probably best to avoid
985 *  an "endian swapping control bit" in the CPU.  One good reason is
986 *  that interrupts would probably have to be disabled to insure that
987 *  an interrupt does not try to access the same "chunk" with the wrong
988 *  endian.  Another good reason is that on some CPUs, the endian bit
989 *  endianness for ALL fetches -- both code and data -- so the code
990 *  will be fetched incorrectly.
991 */
992 
993static inline unsigned int CPU_swap_u32(
994  unsigned int value
995)
996{
997  unsigned32 byte1, byte2, byte3, byte4, swapped;
998 
999  byte4 = (value >> 24) & 0xff;
1000  byte3 = (value >> 16) & 0xff;
1001  byte2 = (value >> 8)  & 0xff;
1002  byte1 =  value        & 0xff;
1003 
1004  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1005  return( swapped );
1006}
1007
1008#define CPU_swap_u16( value ) \
1009  (((value&0xff) << 8) | ((value >> 8)&0xff))
1010
1011#ifdef __cplusplus
1012}
1013#endif
1014
1015#endif
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