[e2040ba] | 1 | /* |
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[aa7f8a1f] | 2 | * Mips CPU Dependent Header File |
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[e2040ba] | 3 | * |
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[aa7f8a1f] | 4 | * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and |
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| 5 | * Joel Sherrill <joel@OARcorp.com>. |
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[e2040ba] | 6 | * |
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[aa7f8a1f] | 7 | * These changes made the code conditional on standard cpp predefines, |
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| 8 | * merged the mips1 and mips3 code sequences as much as possible, |
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| 9 | * and moved some of the assembly code to C. Alan did much of the |
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| 10 | * initial analysis and rework. Joel took over from there and |
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| 11 | * wrote the JMR3904 BSP so this could be tested. Joel also |
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| 12 | * added the new interrupt vectoring support in libcpu and |
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| 13 | * tried to better support the various interrupt controllers. |
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[e2040ba] | 14 | * |
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[aa7f8a1f] | 15 | * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> |
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[e2040ba] | 16 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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[aa7f8a1f] | 17 | * |
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| 18 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 19 | * without any express or implied warranty: |
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[7908ba5b] | 20 | * permission to use, copy, modify, and distribute this file |
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| 21 | * for any purpose is hereby granted without fee, provided that |
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| 22 | * the above copyright notice and this notice appears in all |
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| 23 | * copies, and that the name of Transition Networks not be used in |
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| 24 | * advertising or publicity pertaining to distribution of the |
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| 25 | * software without specific, written prior permission. |
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| 26 | * Transition Networks makes no representations about the suitability |
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| 27 | * of this software for any purpose. |
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| 28 | * |
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[aa7f8a1f] | 29 | * COPYRIGHT (c) 1989-2001. |
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[7908ba5b] | 30 | * On-Line Applications Research Corporation (OAR). |
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| 31 | * |
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| 32 | * The license and distribution terms for this file may be |
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| 33 | * found in the file LICENSE in this distribution or at |
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| 34 | * http://www.OARcorp.com/rtems/license.html. |
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| 35 | * |
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| 36 | * $Id$ |
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| 37 | */ |
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| 38 | |
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| 39 | #ifndef __CPU_h |
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| 40 | #define __CPU_h |
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| 41 | |
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| 42 | #ifdef __cplusplus |
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| 43 | extern "C" { |
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| 44 | #endif |
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| 45 | |
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[32f415d] | 46 | #include <rtems/score/mips.h> /* pick up machine definitions */ |
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[7908ba5b] | 47 | #ifndef ASM |
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| 48 | #include <rtems/score/mipstypes.h> |
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| 49 | #endif |
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| 50 | |
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| 51 | /* conditional compilation parameters */ |
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| 52 | |
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| 53 | /* |
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| 54 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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| 55 | * |
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| 56 | * If TRUE, then they are inlined. |
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| 57 | * If FALSE, then a subroutine call is made. |
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| 58 | * |
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| 59 | * Basically this is an example of the classic trade-off of size |
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| 60 | * versus speed. Inlining the call (TRUE) typically increases the |
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| 61 | * size of RTEMS while speeding up the enabling of dispatching. |
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| 62 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
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| 63 | * only be 0 or 1 unless you are in an interrupt handler and that |
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| 64 | * interrupt handler invokes the executive.] When not inlined |
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| 65 | * something calls _Thread_Enable_dispatch which in turns calls |
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| 66 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
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| 67 | * one subroutine call is avoided entirely.] |
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| 68 | */ |
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| 69 | |
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| 70 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 71 | |
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| 72 | /* |
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| 73 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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| 74 | * be unrolled one time? In unrolled each iteration of the loop examines |
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| 75 | * two "nodes" on the chain being searched. Otherwise, only one node |
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| 76 | * is examined per iteration. |
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| 77 | * |
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| 78 | * If TRUE, then the loops are unrolled. |
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| 79 | * If FALSE, then the loops are not unrolled. |
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| 80 | * |
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| 81 | * The primary factor in making this decision is the cost of disabling |
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| 82 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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| 83 | * body of the loop. On some CPUs, the flash is more expensive than |
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| 84 | * one iteration of the loop body. In this case, it might be desirable |
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| 85 | * to unroll the loop. It is important to note that on some CPUs, this |
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| 86 | * code is the longest interrupt disable period in RTEMS. So it is |
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| 87 | * necessary to strike a balance when setting this parameter. |
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| 88 | */ |
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| 89 | |
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| 90 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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| 91 | |
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| 92 | /* |
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| 93 | * Does RTEMS manage a dedicated interrupt stack in software? |
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| 94 | * |
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[fda47cd] | 95 | * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. |
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[7908ba5b] | 96 | * If FALSE, nothing is done. |
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| 97 | * |
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| 98 | * If the CPU supports a dedicated interrupt stack in hardware, |
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| 99 | * then it is generally the responsibility of the BSP to allocate it |
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| 100 | * and set it up. |
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| 101 | * |
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| 102 | * If the CPU does not support a dedicated interrupt stack, then |
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| 103 | * the porter has two options: (1) execute interrupts on the |
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| 104 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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| 105 | * interrupt stack. |
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| 106 | * |
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| 107 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 108 | * |
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| 109 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 110 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 111 | * possible that both are FALSE for a particular CPU. Although it |
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| 112 | * is unclear what that would imply about the interrupt processing |
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| 113 | * procedure on that CPU. |
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| 114 | */ |
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| 115 | |
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| 116 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 117 | |
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| 118 | /* |
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| 119 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 120 | * |
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| 121 | * If TRUE, then it must be installed during initialization. |
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| 122 | * If FALSE, then no installation is performed. |
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| 123 | * |
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| 124 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 125 | * |
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| 126 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 127 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 128 | * possible that both are FALSE for a particular CPU. Although it |
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| 129 | * is unclear what that would imply about the interrupt processing |
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| 130 | * procedure on that CPU. |
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| 131 | */ |
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| 132 | |
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| 133 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 134 | |
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| 135 | /* |
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| 136 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 137 | * |
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| 138 | * If TRUE, then the memory is allocated during initialization. |
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| 139 | * If FALSE, then the memory is allocated during initialization. |
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| 140 | * |
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| 141 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE |
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| 142 | * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. |
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| 143 | */ |
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| 144 | |
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| 145 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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| 146 | |
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| 147 | /* |
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| 148 | * Does the RTEMS invoke the user's ISR with the vector number and |
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[e2040ba] | 149 | * a pointer to the saved interrupt frame (1) or just the vector |
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[7908ba5b] | 150 | * number (0)? |
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[e2040ba] | 151 | * |
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[7908ba5b] | 152 | */ |
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| 153 | |
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[e2040ba] | 154 | #define CPU_ISR_PASSES_FRAME_POINTER 1 |
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| 155 | |
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| 156 | |
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[7908ba5b] | 157 | |
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| 158 | /* |
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| 159 | * Does the CPU have hardware floating point? |
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| 160 | * |
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| 161 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 162 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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| 163 | * |
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| 164 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 165 | * the answer is TRUE. |
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| 166 | * |
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[fda47cd] | 167 | * The macro name "MIPS_HAS_FPU" should be made CPU specific. |
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[7908ba5b] | 168 | * It indicates whether or not this CPU model has FP support. For |
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| 169 | * example, it would be possible to have an i386_nofp CPU model |
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| 170 | * which set this to false to indicate that you have an i386 without |
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| 171 | * an i387 and wish to leave floating point support out of RTEMS. |
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| 172 | */ |
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| 173 | |
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[fda47cd] | 174 | #if ( MIPS_HAS_FPU == 1 ) |
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[7908ba5b] | 175 | #define CPU_HARDWARE_FP TRUE |
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| 176 | #else |
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| 177 | #define CPU_HARDWARE_FP FALSE |
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| 178 | #endif |
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| 179 | |
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| 180 | /* |
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| 181 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 182 | * |
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| 183 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 184 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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| 185 | * |
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| 186 | * So far, the only CPU in which this option has been used is the |
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| 187 | * HP PA-RISC. The HP C compiler and gcc both implicitly use the |
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| 188 | * floating point registers to perform integer multiplies. If |
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| 189 | * a function which you would not think utilize the FP unit DOES, |
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| 190 | * then one can not easily predict which tasks will use the FP hardware. |
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| 191 | * In this case, this option should be TRUE. |
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| 192 | * |
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| 193 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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| 194 | */ |
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| 195 | |
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| 196 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 197 | |
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| 198 | /* |
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| 199 | * Should the IDLE task have a floating point context? |
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| 200 | * |
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| 201 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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| 202 | * and it has a floating point context which is switched in and out. |
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| 203 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 204 | * |
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| 205 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 206 | * the IDLE task from an interrupt because the floating point context |
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| 207 | * must be saved as part of the preemption. |
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| 208 | */ |
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| 209 | |
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| 210 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 211 | |
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| 212 | /* |
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| 213 | * Should the saving of the floating point registers be deferred |
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| 214 | * until a context switch is made to another different floating point |
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| 215 | * task? |
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| 216 | * |
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| 217 | * If TRUE, then the floating point context will not be stored until |
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| 218 | * necessary. It will remain in the floating point registers and not |
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| 219 | * disturned until another floating point task is switched to. |
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| 220 | * |
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| 221 | * If FALSE, then the floating point context is saved when a floating |
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| 222 | * point task is switched out and restored when the next floating point |
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| 223 | * task is restored. The state of the floating point registers between |
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| 224 | * those two operations is not specified. |
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| 225 | * |
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| 226 | * If the floating point context does NOT have to be saved as part of |
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| 227 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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| 228 | * |
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| 229 | * Setting this flag to TRUE results in using a different algorithm |
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| 230 | * for deciding when to save and restore the floating point context. |
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| 231 | * The deferred FP switch algorithm minimizes the number of times |
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| 232 | * the FP context is saved and restored. The FP context is not saved |
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| 233 | * until a context switch is made to another, different FP task. |
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| 234 | * Thus in a system with only one FP task, the FP context will never |
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| 235 | * be saved or restored. |
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| 236 | */ |
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| 237 | |
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| 238 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 239 | |
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| 240 | /* |
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| 241 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 242 | * |
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| 243 | * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body |
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| 244 | * must be provided and is the default IDLE thread body instead of |
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| 245 | * _Internal_threads_Idle_thread_body. |
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| 246 | * |
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| 247 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 248 | * not provide one. |
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| 249 | * |
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| 250 | * This is intended to allow for supporting processors which have |
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| 251 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 252 | * the CPU can be powered down. |
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| 253 | * |
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| 254 | * The order of precedence for selecting the IDLE thread body is: |
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| 255 | * |
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| 256 | * 1. BSP provided |
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| 257 | * 2. CPU dependent (if provided) |
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| 258 | * 3. generic (if no BSP and no CPU dependent) |
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| 259 | */ |
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| 260 | |
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| 261 | /* we can use the low power wait instruction for the IDLE thread */ |
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[e2040ba] | 262 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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[7908ba5b] | 263 | |
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| 264 | /* |
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| 265 | * Does the stack grow up (toward higher addresses) or down |
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| 266 | * (toward lower addresses)? |
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| 267 | * |
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| 268 | * If TRUE, then the grows upward. |
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| 269 | * If FALSE, then the grows toward smaller addresses. |
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| 270 | */ |
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| 271 | |
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| 272 | /* our stack grows down */ |
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| 273 | #define CPU_STACK_GROWS_UP FALSE |
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| 274 | |
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| 275 | /* |
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| 276 | * The following is the variable attribute used to force alignment |
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| 277 | * of critical RTEMS structures. On some processors it may make |
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| 278 | * sense to have these aligned on tighter boundaries than |
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| 279 | * the minimum requirements of the compiler in order to have as |
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| 280 | * much of the critical data area as possible in a cache line. |
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| 281 | * |
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| 282 | * The placement of this macro in the declaration of the variables |
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| 283 | * is based on the syntactically requirements of the GNU C |
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| 284 | * "__attribute__" extension. For example with GNU C, use |
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| 285 | * the following to force a structures to a 32 byte boundary. |
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| 286 | * |
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| 287 | * __attribute__ ((aligned (32))) |
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| 288 | * |
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| 289 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
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| 290 | * To benefit from using this, the data must be heavily |
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| 291 | * used so it will stay in the cache and used frequently enough |
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| 292 | * in the executive to justify turning this on. |
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| 293 | */ |
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| 294 | |
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| 295 | /* our cache line size is 16 bytes */ |
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| 296 | #if __GNUC__ |
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| 297 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) |
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| 298 | #else |
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[e2040ba] | 299 | #define CPU_STRUCTURE_ALIGNMENT |
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[7908ba5b] | 300 | #endif |
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| 301 | |
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| 302 | /* |
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| 303 | * Define what is required to specify how the network to host conversion |
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| 304 | * routines are handled. |
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| 305 | */ |
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| 306 | |
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[6805640e] | 307 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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[7908ba5b] | 308 | #define CPU_BIG_ENDIAN TRUE |
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| 309 | #define CPU_LITTLE_ENDIAN FALSE |
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| 310 | |
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| 311 | /* |
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| 312 | * The following defines the number of bits actually used in the |
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| 313 | * interrupt field of the task mode. How those bits map to the |
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| 314 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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| 315 | */ |
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| 316 | |
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| 317 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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| 318 | |
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| 319 | /* |
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| 320 | * Processor defined structures |
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| 321 | * |
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| 322 | * Examples structures include the descriptor tables from the i386 |
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| 323 | * and the processor control structure on the i960ca. |
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| 324 | */ |
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| 325 | |
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| 326 | /* may need to put some structures here. */ |
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| 327 | |
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| 328 | /* |
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| 329 | * Contexts |
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| 330 | * |
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| 331 | * Generally there are 2 types of context to save. |
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| 332 | * 1. Interrupt registers to save |
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| 333 | * 2. Task level registers to save |
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| 334 | * |
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| 335 | * This means we have the following 3 context items: |
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| 336 | * 1. task level context stuff:: Context_Control |
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| 337 | * 2. floating point task stuff:: Context_Control_fp |
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| 338 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 339 | * |
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| 340 | * On some processors, it is cost-effective to save only the callee |
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| 341 | * preserved registers during a task context switch. This means |
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| 342 | * that the ISR code needs to save those registers which do not |
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| 343 | * persist across function calls. It is not mandatory to make this |
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| 344 | * distinctions between the caller/callee saves registers for the |
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| 345 | * purpose of minimizing context saved during task switch and on interrupts. |
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| 346 | * If the cost of saving extra registers is minimal, simplicity is the |
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| 347 | * choice. Save the same context on interrupt entry as for tasks in |
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| 348 | * this case. |
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| 349 | * |
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| 350 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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| 351 | * care should be used in designing the context area. |
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| 352 | * |
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| 353 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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| 354 | * structure will not be used or it simply consist of an array of a |
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| 355 | * fixed number of bytes. This is done when the floating point context |
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| 356 | * is dumped by a "FP save context" type instruction and the format |
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| 357 | * is not really defined by the CPU. In this case, there is no need |
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| 358 | * to figure out the exact format -- only the size. Of course, although |
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| 359 | * this is enough information for RTEMS, it is probably not enough for |
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| 360 | * a debugger such as gdb. But that is another problem. |
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| 361 | */ |
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| 362 | |
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| 363 | /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ |
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[5d7bfce3] | 364 | #if __mips == 1 |
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[2e549dad] | 365 | #define __MIPS_REGISTER_TYPE unsigned32 |
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| 366 | #define __MIPS_FPU_REGISTER_TYPE unsigned32 |
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| 367 | #elif __mips == 3 |
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| 368 | #define __MIPS_REGISTER_TYPE unsigned64 |
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| 369 | #define __MIPS_FPU_REGISTER_TYPE unsigned64 |
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[5d7bfce3] | 370 | #else |
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[2e549dad] | 371 | #error "mips register size: unknown architecture level!!" |
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[5d7bfce3] | 372 | #endif |
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[2e549dad] | 373 | typedef struct { |
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| 374 | __MIPS_REGISTER_TYPE s0; |
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| 375 | __MIPS_REGISTER_TYPE s1; |
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| 376 | __MIPS_REGISTER_TYPE s2; |
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| 377 | __MIPS_REGISTER_TYPE s3; |
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| 378 | __MIPS_REGISTER_TYPE s4; |
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| 379 | __MIPS_REGISTER_TYPE s5; |
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| 380 | __MIPS_REGISTER_TYPE s6; |
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| 381 | __MIPS_REGISTER_TYPE s7; |
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| 382 | __MIPS_REGISTER_TYPE sp; |
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| 383 | __MIPS_REGISTER_TYPE fp; |
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| 384 | __MIPS_REGISTER_TYPE ra; |
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| 385 | __MIPS_REGISTER_TYPE c0_sr; |
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[e2040ba] | 386 | /* __MIPS_REGISTER_TYPE c0_epc; */ |
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[7908ba5b] | 387 | } Context_Control; |
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| 388 | |
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[2e549dad] | 389 | /* WARNING: If this structure is modified, the constants in cpu.h |
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| 390 | * must also be updated. |
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| 391 | */ |
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| 392 | |
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[7908ba5b] | 393 | typedef struct { |
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[2e549dad] | 394 | #if ( CPU_HARDWARE_FP == TRUE ) |
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| 395 | __MIPS_FPU_REGISTER_TYPE fp0; |
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| 396 | __MIPS_FPU_REGISTER_TYPE fp1; |
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| 397 | __MIPS_FPU_REGISTER_TYPE fp2; |
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| 398 | __MIPS_FPU_REGISTER_TYPE fp3; |
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| 399 | __MIPS_FPU_REGISTER_TYPE fp4; |
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| 400 | __MIPS_FPU_REGISTER_TYPE fp5; |
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| 401 | __MIPS_FPU_REGISTER_TYPE fp6; |
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| 402 | __MIPS_FPU_REGISTER_TYPE fp7; |
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| 403 | __MIPS_FPU_REGISTER_TYPE fp8; |
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| 404 | __MIPS_FPU_REGISTER_TYPE fp9; |
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| 405 | __MIPS_FPU_REGISTER_TYPE fp10; |
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| 406 | __MIPS_FPU_REGISTER_TYPE fp11; |
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| 407 | __MIPS_FPU_REGISTER_TYPE fp12; |
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| 408 | __MIPS_FPU_REGISTER_TYPE fp13; |
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| 409 | __MIPS_FPU_REGISTER_TYPE fp14; |
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| 410 | __MIPS_FPU_REGISTER_TYPE fp15; |
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| 411 | __MIPS_FPU_REGISTER_TYPE fp16; |
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| 412 | __MIPS_FPU_REGISTER_TYPE fp17; |
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| 413 | __MIPS_FPU_REGISTER_TYPE fp18; |
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| 414 | __MIPS_FPU_REGISTER_TYPE fp19; |
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| 415 | __MIPS_FPU_REGISTER_TYPE fp20; |
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| 416 | __MIPS_FPU_REGISTER_TYPE fp21; |
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| 417 | __MIPS_FPU_REGISTER_TYPE fp22; |
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| 418 | __MIPS_FPU_REGISTER_TYPE fp23; |
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| 419 | __MIPS_FPU_REGISTER_TYPE fp24; |
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| 420 | __MIPS_FPU_REGISTER_TYPE fp25; |
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| 421 | __MIPS_FPU_REGISTER_TYPE fp26; |
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| 422 | __MIPS_FPU_REGISTER_TYPE fp27; |
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| 423 | __MIPS_FPU_REGISTER_TYPE fp28; |
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| 424 | __MIPS_FPU_REGISTER_TYPE fp29; |
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| 425 | __MIPS_FPU_REGISTER_TYPE fp30; |
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| 426 | __MIPS_FPU_REGISTER_TYPE fp31; |
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| 427 | #endif |
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[7908ba5b] | 428 | } Context_Control_fp; |
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| 429 | |
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[e2040ba] | 430 | |
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| 431 | |
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| 432 | |
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| 433 | |
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| 434 | /* |
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| 435 | This struct reflects the stack frame employed in ISR_Handler. Note |
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| 436 | that the ISR routine doesn't save all registers to this frame, so |
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| 437 | cpu_asm.S should be consulted to see if the registers you're |
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| 438 | interested in are actually there. |
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| 439 | */ |
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| 440 | |
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| 441 | typedef struct |
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| 442 | { |
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| 443 | #if __mips == 1 |
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| 444 | unsigned int regs[80]; |
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| 445 | #endif |
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| 446 | #if __mips == 3 |
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| 447 | unsigned int regs[94]; |
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| 448 | #endif |
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[7908ba5b] | 449 | } CPU_Interrupt_frame; |
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| 450 | |
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| 451 | |
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| 452 | /* |
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| 453 | * The following table contains the information required to configure |
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| 454 | * the mips processor specific parameters. |
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| 455 | */ |
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| 456 | |
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| 457 | typedef struct { |
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| 458 | void (*pretasking_hook)( void ); |
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| 459 | void (*predriver_hook)( void ); |
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| 460 | void (*postdriver_hook)( void ); |
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| 461 | void (*idle_task)( void ); |
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| 462 | boolean do_zero_of_workspace; |
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| 463 | unsigned32 idle_task_stack_size; |
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| 464 | unsigned32 interrupt_stack_size; |
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| 465 | unsigned32 extra_mpci_receive_server_stack; |
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| 466 | void * (*stack_allocate_hook)( unsigned32 ); |
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| 467 | void (*stack_free_hook)( void* ); |
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| 468 | /* end of fields required on all CPUs */ |
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| 469 | |
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[f817b02] | 470 | unsigned32 clicks_per_microsecond; |
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[7908ba5b] | 471 | } rtems_cpu_table; |
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| 472 | |
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[458bd34] | 473 | /* |
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[e2040ba] | 474 | * Macros to access required entires in the CPU Table are in |
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[458bd34] | 475 | * the file rtems/system.h. |
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| 476 | */ |
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| 477 | |
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| 478 | /* |
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[fda47cd] | 479 | * Macros to access MIPS specific additions to the CPU Table |
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[458bd34] | 480 | */ |
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| 481 | |
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[f817b02] | 482 | #define rtems_cpu_configuration_get_clicks_per_microsecond() \ |
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| 483 | (_CPU_Table.clicks_per_microsecond) |
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| 484 | |
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[7908ba5b] | 485 | /* |
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| 486 | * This variable is optional. It is used on CPUs on which it is difficult |
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| 487 | * to generate an "uninitialized" FP context. It is filled in by |
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| 488 | * _CPU_Initialize and copied into the task's FP context area during |
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| 489 | * _CPU_Context_Initialize. |
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| 490 | */ |
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| 491 | |
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| 492 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
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| 493 | |
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| 494 | /* |
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| 495 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
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| 496 | * This stack is allocated by the Interrupt Manager and the switch |
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| 497 | * is performed in _ISR_Handler. These variables contain pointers |
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| 498 | * to the lowest and highest addresses in the chunk of memory allocated |
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| 499 | * for the interrupt stack. Since it is unknown whether the stack |
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| 500 | * grows up or down (in general), this give the CPU dependent |
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| 501 | * code the option of picking the version it wants to use. |
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| 502 | * |
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| 503 | * NOTE: These two variables are required if the macro |
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| 504 | * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
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| 505 | */ |
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| 506 | |
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| 507 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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| 508 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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| 509 | |
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| 510 | /* |
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| 511 | * With some compilation systems, it is difficult if not impossible to |
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| 512 | * call a high-level language routine from assembly language. This |
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| 513 | * is especially true of commercial Ada compilers and name mangling |
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| 514 | * C++ ones. This variable can be optionally defined by the CPU porter |
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| 515 | * and contains the address of the routine _Thread_Dispatch. This |
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| 516 | * can make it easier to invoke that routine at the end of the interrupt |
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| 517 | * sequence (if a dispatch is necessary). |
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[aa7f8a1f] | 518 | * |
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[7908ba5b] | 519 | |
---|
| 520 | SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); |
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[aa7f8a1f] | 521 | * |
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| 522 | * NOTE: Not needed on this port. |
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| 523 | */ |
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[7908ba5b] | 524 | |
---|
| 525 | /* |
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| 526 | * Nothing prevents the porter from declaring more CPU specific variables. |
---|
| 527 | */ |
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| 528 | |
---|
| 529 | /* XXX: if needed, put more variables here */ |
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| 530 | |
---|
| 531 | /* |
---|
| 532 | * The size of the floating point context area. On some CPUs this |
---|
| 533 | * will not be a "sizeof" because the format of the floating point |
---|
| 534 | * area is not defined -- only the size is. This is usually on |
---|
| 535 | * CPUs with a "floating point save context" instruction. |
---|
| 536 | */ |
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| 537 | |
---|
| 538 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 539 | |
---|
| 540 | /* |
---|
| 541 | * Amount of extra stack (above minimum stack size) required by |
---|
| 542 | * system initialization thread. Remember that in a multiprocessor |
---|
| 543 | * system the system intialization thread becomes the MP server thread. |
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| 544 | */ |
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| 545 | |
---|
| 546 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
| 547 | |
---|
| 548 | /* |
---|
| 549 | * This defines the number of entries in the ISR_Vector_table managed |
---|
| 550 | * by RTEMS. |
---|
| 551 | */ |
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| 552 | |
---|
[32f415d] | 553 | extern unsigned int mips_interrupt_number_of_vectors; |
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[797d88ba] | 554 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS (mips_interrupt_number_of_vectors) |
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[7908ba5b] | 555 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
---|
| 556 | |
---|
| 557 | /* |
---|
| 558 | * Should be large enough to run all RTEMS tests. This insures |
---|
| 559 | * that a "reasonable" small application should not have any problems. |
---|
| 560 | */ |
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| 561 | |
---|
| 562 | #define CPU_STACK_MINIMUM_SIZE (2048*sizeof(unsigned32)) |
---|
| 563 | |
---|
| 564 | /* |
---|
| 565 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 566 | * alignment does not take into account the requirements for the stack. |
---|
| 567 | */ |
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| 568 | |
---|
| 569 | #define CPU_ALIGNMENT 8 |
---|
| 570 | |
---|
| 571 | /* |
---|
| 572 | * This number corresponds to the byte alignment requirement for the |
---|
| 573 | * heap handler. This alignment requirement may be stricter than that |
---|
| 574 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 575 | * common for the heap to follow the same alignment requirement as |
---|
| 576 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 577 | * then this should be set to CPU_ALIGNMENT. |
---|
| 578 | * |
---|
| 579 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 580 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 581 | */ |
---|
| 582 | |
---|
| 583 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
| 584 | |
---|
| 585 | /* |
---|
| 586 | * This number corresponds to the byte alignment requirement for memory |
---|
| 587 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 588 | * may be stricter than that for the data types alignment specified by |
---|
| 589 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 590 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 591 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
| 592 | * |
---|
| 593 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 594 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 595 | */ |
---|
| 596 | |
---|
| 597 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 598 | |
---|
| 599 | /* |
---|
| 600 | * This number corresponds to the byte alignment requirement for the |
---|
| 601 | * stack. This alignment requirement may be stricter than that for the |
---|
| 602 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 603 | * is strict enough for the stack, then this should be set to 0. |
---|
| 604 | * |
---|
| 605 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 606 | */ |
---|
| 607 | |
---|
| 608 | #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
---|
| 609 | |
---|
[9fd4f5c5] | 610 | /* |
---|
| 611 | * ISR handler macros |
---|
| 612 | */ |
---|
| 613 | |
---|
| 614 | /* |
---|
| 615 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
| 616 | */ |
---|
| 617 | |
---|
| 618 | #define _CPU_Initialize_vectors() |
---|
[7908ba5b] | 619 | |
---|
| 620 | /* |
---|
| 621 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 622 | * level is returned in _level. |
---|
| 623 | */ |
---|
| 624 | |
---|
[32f415d] | 625 | #define _CPU_ISR_Disable( _level ) \ |
---|
| 626 | do { \ |
---|
| 627 | mips_get_sr( _level ); \ |
---|
[16ad7ea] | 628 | mips_set_sr( (_level) & ~SR_INTERRUPT_ENABLE_BITS ); \ |
---|
[32f415d] | 629 | } while(0) |
---|
[7908ba5b] | 630 | |
---|
| 631 | /* |
---|
| 632 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 633 | * This indicates the end of an RTEMS critical section. The parameter |
---|
| 634 | * _level is not modified. |
---|
| 635 | */ |
---|
| 636 | |
---|
| 637 | #define _CPU_ISR_Enable( _level ) \ |
---|
[32f415d] | 638 | do { \ |
---|
| 639 | mips_set_sr(_level); \ |
---|
| 640 | } while(0) |
---|
[7908ba5b] | 641 | |
---|
| 642 | /* |
---|
| 643 | * This temporarily restores the interrupt to _level before immediately |
---|
| 644 | * disabling them again. This is used to divide long RTEMS critical |
---|
| 645 | * sections into two or more parts. The parameter _level is not |
---|
| 646 | * modified. |
---|
| 647 | */ |
---|
| 648 | |
---|
| 649 | #define _CPU_ISR_Flash( _xlevel ) \ |
---|
[32f415d] | 650 | do { \ |
---|
| 651 | unsigned int _scratch; \ |
---|
| 652 | _CPU_ISR_Enable( _xlevel ); \ |
---|
| 653 | _CPU_ISR_Disable( _scratch ); \ |
---|
| 654 | } while(0) |
---|
[7908ba5b] | 655 | |
---|
| 656 | /* |
---|
| 657 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
| 658 | * actually provides. Currently, interrupt levels which do not |
---|
| 659 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 660 | * it would be nice if these were "mapped" by the application |
---|
| 661 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 662 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 663 | * This could be used to manage a programmable interrupt controller |
---|
| 664 | * via the rtems_task_mode directive. |
---|
[32f415d] | 665 | * |
---|
[e2040ba] | 666 | * On the MIPS, 0 is all on. Non-zero is all off. This only |
---|
[32f415d] | 667 | * manipulates the IEC. |
---|
[7908ba5b] | 668 | */ |
---|
[32f415d] | 669 | |
---|
| 670 | unsigned32 _CPU_ISR_Get_level( void ); /* in cpu.c */ |
---|
[2e549dad] | 671 | |
---|
| 672 | void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */ |
---|
[7908ba5b] | 673 | |
---|
| 674 | /* end of ISR handler macros */ |
---|
| 675 | |
---|
| 676 | /* Context handler macros */ |
---|
| 677 | |
---|
| 678 | /* |
---|
| 679 | * Initialize the context to a state suitable for starting a |
---|
| 680 | * task after a context restore operation. Generally, this |
---|
| 681 | * involves: |
---|
| 682 | * |
---|
| 683 | * - setting a starting address |
---|
| 684 | * - preparing the stack |
---|
| 685 | * - preparing the stack and frame pointers |
---|
| 686 | * - setting the proper interrupt level in the context |
---|
| 687 | * - initializing the floating point context |
---|
| 688 | * |
---|
| 689 | * This routine generally does not set any unnecessary register |
---|
| 690 | * in the context. The state of the "general data" registers is |
---|
| 691 | * undefined at task start time. |
---|
| 692 | * |
---|
| 693 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
---|
| 694 | * point thread. This is typically only used on CPUs where the |
---|
| 695 | * FPU may be easily disabled by software such as on the SPARC |
---|
| 696 | * where the PSR contains an enable FPU bit. |
---|
| 697 | */ |
---|
| 698 | |
---|
| 699 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
---|
| 700 | _isr, _entry_point, _is_fp ) \ |
---|
| 701 | { \ |
---|
[2e549dad] | 702 | unsigned32 _stack_tmp = \ |
---|
| 703 | (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \ |
---|
[7908ba5b] | 704 | _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \ |
---|
| 705 | (_the_context)->sp = _stack_tmp; \ |
---|
| 706 | (_the_context)->fp = _stack_tmp; \ |
---|
| 707 | (_the_context)->ra = (unsigned64)_entry_point; \ |
---|
[e2040ba] | 708 | (_the_context)->c0_sr = ((_the_context)->c0_sr & 0x0fff0000) | \ |
---|
| 709 | ((_isr)?0xff00:0xff01) | \ |
---|
| 710 | ((_is_fp)?0x20000000:0x10000000); \ |
---|
[7908ba5b] | 711 | } |
---|
| 712 | |
---|
| 713 | /* |
---|
| 714 | * This routine is responsible for somehow restarting the currently |
---|
| 715 | * executing task. If you are lucky, then all that is necessary |
---|
| 716 | * is restoring the context. Otherwise, there will need to be |
---|
| 717 | * a special assembly routine which does something special in this |
---|
| 718 | * case. Context_Restore should work most of the time. It will |
---|
| 719 | * not work if restarting self conflicts with the stack frame |
---|
| 720 | * assumptions of restoring a context. |
---|
| 721 | */ |
---|
| 722 | |
---|
| 723 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 724 | _CPU_Context_restore( (_the_context) ); |
---|
| 725 | |
---|
| 726 | /* |
---|
| 727 | * The purpose of this macro is to allow the initial pointer into |
---|
| 728 | * A floating point context area (used to save the floating point |
---|
| 729 | * context) to be at an arbitrary place in the floating point |
---|
| 730 | * context area. |
---|
| 731 | * |
---|
| 732 | * This is necessary because some FP units are designed to have |
---|
| 733 | * their context saved as a stack which grows into lower addresses. |
---|
| 734 | * Other FP units can be saved by simply moving registers into offsets |
---|
| 735 | * from the base of the context area. Finally some FP units provide |
---|
| 736 | * a "dump context" instruction which could fill in from high to low |
---|
| 737 | * or low to high based on the whim of the CPU designers. |
---|
| 738 | */ |
---|
| 739 | |
---|
| 740 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 741 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
| 742 | |
---|
| 743 | /* |
---|
| 744 | * This routine initializes the FP context area passed to it to. |
---|
| 745 | * There are a few standard ways in which to initialize the |
---|
| 746 | * floating point context. The code included for this macro assumes |
---|
| 747 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 748 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 749 | * context passed to it. |
---|
| 750 | * |
---|
| 751 | * Other models include (1) not doing anything, and (2) putting |
---|
| 752 | * a "null FP status word" in the correct place in the FP context. |
---|
| 753 | */ |
---|
| 754 | |
---|
[2e549dad] | 755 | #if ( CPU_HARDWARE_FP == TRUE ) |
---|
[7908ba5b] | 756 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 757 | { \ |
---|
| 758 | *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ |
---|
| 759 | } |
---|
[2e549dad] | 760 | #endif |
---|
[7908ba5b] | 761 | |
---|
| 762 | /* end of Context handler macros */ |
---|
| 763 | |
---|
| 764 | /* Fatal Error manager macros */ |
---|
| 765 | |
---|
| 766 | /* |
---|
| 767 | * This routine copies _error into a known place -- typically a stack |
---|
| 768 | * location or a register, optionally disables interrupts, and |
---|
| 769 | * halts/stops the CPU. |
---|
| 770 | */ |
---|
| 771 | |
---|
| 772 | #define _CPU_Fatal_halt( _error ) \ |
---|
[32f415d] | 773 | do { \ |
---|
| 774 | unsigned int _level; \ |
---|
| 775 | _CPU_ISR_Disable(_level); \ |
---|
[aa7f8a1f] | 776 | loop: goto loop; \ |
---|
[32f415d] | 777 | } while (0) |
---|
[7908ba5b] | 778 | |
---|
[aa7f8a1f] | 779 | |
---|
| 780 | extern void mips_break( int error ); |
---|
[7908ba5b] | 781 | |
---|
| 782 | /* Bitfield handler macros */ |
---|
| 783 | |
---|
| 784 | /* |
---|
| 785 | * This routine sets _output to the bit number of the first bit |
---|
| 786 | * set in _value. _value is of CPU dependent type Priority_Bit_map_control. |
---|
| 787 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
| 788 | * least significant bits will be used. |
---|
| 789 | * |
---|
| 790 | * There are a number of variables in using a "find first bit" type |
---|
| 791 | * instruction. |
---|
| 792 | * |
---|
| 793 | * (1) What happens when run on a value of zero? |
---|
| 794 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 795 | * (3) The numbering may be zero or one based. |
---|
| 796 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
| 797 | * |
---|
| 798 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
| 799 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
| 800 | * _CPU_Priority_bits_index(). These three form a set of routines |
---|
| 801 | * which must logically operate together. Bits in the _value are |
---|
| 802 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
| 803 | * The basic major and minor values calculated by _Priority_Major() |
---|
| 804 | * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() |
---|
| 805 | * to properly range between the values returned by the "find first bit" |
---|
| 806 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
| 807 | * calculate the major and directly index into the minor table. |
---|
| 808 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 809 | * is the first bit found. |
---|
| 810 | * |
---|
| 811 | * This entire "find first bit" and mapping process depends heavily |
---|
| 812 | * on the manner in which a priority is broken into a major and minor |
---|
| 813 | * components with the major being the 4 MSB of a priority and minor |
---|
| 814 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 815 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 816 | * to the lowest priority. |
---|
| 817 | * |
---|
| 818 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 819 | * there are ways to make do without it. Here are a handful of ways |
---|
| 820 | * to implement this in software: |
---|
| 821 | * |
---|
| 822 | * - a series of 16 bit test instructions |
---|
| 823 | * - a "binary search using if's" |
---|
| 824 | * - _number = 0 |
---|
| 825 | * if _value > 0x00ff |
---|
| 826 | * _value >>=8 |
---|
| 827 | * _number = 8; |
---|
| 828 | * |
---|
| 829 | * if _value > 0x0000f |
---|
| 830 | * _value >=8 |
---|
| 831 | * _number += 4 |
---|
| 832 | * |
---|
| 833 | * _number += bit_set_table[ _value ] |
---|
| 834 | * |
---|
| 835 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 836 | * bit set |
---|
| 837 | */ |
---|
| 838 | |
---|
| 839 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 840 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
| 841 | |
---|
| 842 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 843 | |
---|
| 844 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 845 | { \ |
---|
| 846 | (_output) = 0; /* do something to prevent warnings */ \ |
---|
| 847 | } |
---|
| 848 | |
---|
| 849 | #endif |
---|
| 850 | |
---|
| 851 | /* end of Bitfield handler macros */ |
---|
| 852 | |
---|
| 853 | /* |
---|
| 854 | * This routine builds the mask which corresponds to the bit fields |
---|
| 855 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
| 856 | * for that routine. |
---|
| 857 | */ |
---|
| 858 | |
---|
| 859 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 860 | |
---|
| 861 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
| 862 | ( 1 << (_bit_number) ) |
---|
| 863 | |
---|
| 864 | #endif |
---|
| 865 | |
---|
| 866 | /* |
---|
| 867 | * This routine translates the bit numbers returned by |
---|
| 868 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
| 869 | * a major or minor component of a priority. See the discussion |
---|
| 870 | * for that routine. |
---|
| 871 | */ |
---|
| 872 | |
---|
| 873 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 874 | |
---|
| 875 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 876 | (_priority) |
---|
| 877 | |
---|
| 878 | #endif |
---|
| 879 | |
---|
| 880 | /* end of Priority handler macros */ |
---|
| 881 | |
---|
| 882 | /* functions */ |
---|
| 883 | |
---|
| 884 | /* |
---|
| 885 | * _CPU_Initialize |
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| 886 | * |
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| 887 | * This routine performs CPU dependent initialization. |
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| 888 | */ |
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| 889 | |
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| 890 | void _CPU_Initialize( |
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| 891 | rtems_cpu_table *cpu_table, |
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| 892 | void (*thread_dispatch) |
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| 893 | ); |
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| 894 | |
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| 895 | /* |
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| 896 | * _CPU_ISR_install_raw_handler |
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| 897 | * |
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[e2040ba] | 898 | * This routine installs a "raw" interrupt handler directly into the |
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[7908ba5b] | 899 | * processor's vector table. |
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| 900 | */ |
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[e2040ba] | 901 | |
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[7908ba5b] | 902 | void _CPU_ISR_install_raw_handler( |
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| 903 | unsigned32 vector, |
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| 904 | proc_ptr new_handler, |
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| 905 | proc_ptr *old_handler |
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| 906 | ); |
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| 907 | |
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| 908 | /* |
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| 909 | * _CPU_ISR_install_vector |
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| 910 | * |
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| 911 | * This routine installs an interrupt vector. |
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| 912 | */ |
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| 913 | |
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| 914 | void _CPU_ISR_install_vector( |
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| 915 | unsigned32 vector, |
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| 916 | proc_ptr new_handler, |
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| 917 | proc_ptr *old_handler |
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| 918 | ); |
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| 919 | |
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| 920 | /* |
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| 921 | * _CPU_Install_interrupt_stack |
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| 922 | * |
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| 923 | * This routine installs the hardware interrupt stack pointer. |
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| 924 | * |
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| 925 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
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| 926 | * is TRUE. |
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| 927 | */ |
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| 928 | |
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| 929 | void _CPU_Install_interrupt_stack( void ); |
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| 930 | |
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| 931 | /* |
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| 932 | * _CPU_Internal_threads_Idle_thread_body |
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| 933 | * |
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| 934 | * This routine is the CPU dependent IDLE thread body. |
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| 935 | * |
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| 936 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
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| 937 | * is TRUE. |
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| 938 | */ |
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| 939 | |
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| 940 | void _CPU_Thread_Idle_body( void ); |
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| 941 | |
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| 942 | /* |
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| 943 | * _CPU_Context_switch |
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| 944 | * |
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| 945 | * This routine switches from the run context to the heir context. |
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| 946 | */ |
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| 947 | |
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| 948 | void _CPU_Context_switch( |
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| 949 | Context_Control *run, |
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| 950 | Context_Control *heir |
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| 951 | ); |
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| 952 | |
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| 953 | /* |
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| 954 | * _CPU_Context_restore |
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| 955 | * |
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| 956 | * This routine is generally used only to restart self in an |
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| 957 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 958 | * |
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| 959 | * NOTE: May be unnecessary to reload some registers. |
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| 960 | */ |
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| 961 | |
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| 962 | void _CPU_Context_restore( |
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| 963 | Context_Control *new_context |
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| 964 | ); |
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| 965 | |
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| 966 | /* |
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| 967 | * _CPU_Context_save_fp |
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| 968 | * |
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| 969 | * This routine saves the floating point context passed to it. |
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| 970 | */ |
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| 971 | |
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| 972 | void _CPU_Context_save_fp( |
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| 973 | void **fp_context_ptr |
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| 974 | ); |
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| 975 | |
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| 976 | /* |
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| 977 | * _CPU_Context_restore_fp |
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| 978 | * |
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| 979 | * This routine restores the floating point context passed to it. |
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| 980 | */ |
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| 981 | |
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| 982 | void _CPU_Context_restore_fp( |
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| 983 | void **fp_context_ptr |
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| 984 | ); |
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| 985 | |
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| 986 | /* The following routine swaps the endian format of an unsigned int. |
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| 987 | * It must be static because it is referenced indirectly. |
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| 988 | * |
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| 989 | * This version will work on any processor, but if there is a better |
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| 990 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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| 991 | * |
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| 992 | * swap least significant two bytes with 16-bit rotate |
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| 993 | * swap upper and lower 16-bits |
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| 994 | * swap most significant two bytes with 16-bit rotate |
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| 995 | * |
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| 996 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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| 997 | * a single instruction (e.g. i486). It is probably best to avoid |
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| 998 | * an "endian swapping control bit" in the CPU. One good reason is |
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| 999 | * that interrupts would probably have to be disabled to insure that |
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| 1000 | * an interrupt does not try to access the same "chunk" with the wrong |
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| 1001 | * endian. Another good reason is that on some CPUs, the endian bit |
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| 1002 | * endianness for ALL fetches -- both code and data -- so the code |
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| 1003 | * will be fetched incorrectly. |
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| 1004 | */ |
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[e2040ba] | 1005 | |
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[7908ba5b] | 1006 | static inline unsigned int CPU_swap_u32( |
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| 1007 | unsigned int value |
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| 1008 | ) |
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| 1009 | { |
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| 1010 | unsigned32 byte1, byte2, byte3, byte4, swapped; |
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[e2040ba] | 1011 | |
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[7908ba5b] | 1012 | byte4 = (value >> 24) & 0xff; |
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| 1013 | byte3 = (value >> 16) & 0xff; |
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| 1014 | byte2 = (value >> 8) & 0xff; |
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| 1015 | byte1 = value & 0xff; |
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[e2040ba] | 1016 | |
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[7908ba5b] | 1017 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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| 1018 | return( swapped ); |
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| 1019 | } |
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| 1020 | |
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| 1021 | #define CPU_swap_u16( value ) \ |
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| 1022 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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| 1023 | |
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| 1024 | #ifdef __cplusplus |
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| 1025 | } |
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| 1026 | #endif |
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| 1027 | |
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| 1028 | #endif |
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