source: rtems/c/src/exec/score/cpu/mips/cpu.c @ 797d88ba

4.104.114.84.95
Last change on this file since 797d88ba was 797d88ba, checked in by Joel Sherrill <joel.sherrill@…>, on 12/13/00 at 22:12:06

2000-12-13 Joel Sherrill <joel@…>

  • cpu.c: Removed duplicate declaration for _ISR_Vector_table.
  • cpu_asm.S: Removed assembly language to vector ISR handler on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP.
  • rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No longer a constant -- get the real value from libcpu.
  • Property mode set to 100644
File size: 5.6 KB
Line 
1/*
2 *  Mips CPU Dependent Source
3 *
4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
5 *           Joel Sherrill <joel@OARcorp.com>.
6 *
7 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
8 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
9 *
10 *         To anyone who acknowledges that this file is provided "AS IS"
11 *         without any express or implied warranty:
12 *             permission to use, copy, modify, and distribute this file
13 *             for any purpose is hereby granted without fee, provided that
14 *             the above copyright notice and this notice appears in all
15 *             copies, and that the name of Transition Networks not be used in
16 *             advertising or publicity pertaining to distribution of the
17 *             software without specific, written prior permission.
18 *             Transition Networks makes no representations about the
19 *             suitability of this software for any purpose.
20 *
21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
22 *
23 *  COPYRIGHT (c) 1989-1999.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.OARcorp.com/rtems/license.html.
29 *
30 *  $Id$
31 */
32
33/*
34 *  Rather than deleting this, it is commented out to (hopefully) help
35 *  the submitter send updates.
36 *
37 * static char _sccsid[] = "@(#)cpu.c 08/20/96     1.5\n";
38 */
39
40#include <rtems/system.h>
41#include <rtems/score/isr.h>
42#include <rtems/score/wkspace.h>
43
44
45/*  _CPU_Initialize
46 *
47 *  This routine performs processor dependent initialization.
48 *
49 *  INPUT PARAMETERS:
50 *    cpu_table       - CPU table to initialize
51 *    thread_dispatch - address of disptaching routine
52 */
53
54
55void null_handler( void )
56{
57}
58
59
60void _CPU_Initialize(
61  rtems_cpu_table  *cpu_table,
62  void      (*thread_dispatch)      /* ignored on this CPU */
63)
64{
65   unsigned int i = ISR_NUMBER_OF_VECTORS;
66
67   while ( i-- ) {
68      _ISR_Vector_table[i] = (ISR_Handler_entry)null_handler;
69   }
70
71  /*
72   *  The thread_dispatch argument is the address of the entry point
73   *  for the routine called at the end of an ISR once it has been
74   *  decided a context switch is necessary.  On some compilation
75   *  systems it is difficult to call a high-level language routine
76   *  from assembly.  This allows us to trick these systems.
77   *
78   *  If you encounter this problem save the entry point in a CPU
79   *  dependent variable.
80   */
81
82  _CPU_Thread_dispatch_pointer = thread_dispatch;
83
84  /*
85   *  If there is not an easy way to initialize the FP context
86   *  during Context_Initialize, then it is usually easier to
87   *  save an "uninitialized" FP context here and copy it to
88   *  the task's during Context_Initialize.
89   */
90
91  /* FP context initialization support goes here */
92
93  _CPU_Table = *cpu_table;
94
95}
96
97/*PAGE
98 *
99 *  _CPU_ISR_Get_level
100 *
101 *  This routine returns the current interrupt level.
102 */
103   
104#if __mips == 3
105
106/* in cpu_asm.S for now */
107
108#elif __mips == 1
109unsigned32 _CPU_ISR_Get_level( void )
110{
111  unsigned int sr;
112
113  mips_get_sr(sr);
114
115  return ((sr & SR_IEC) ? 0 : 1);
116}
117#else
118#error "CPU ISR level: unknown MIPS level for SR handling"
119#endif
120
121/*PAGE
122 *
123 *  _CPU_ISR_install_raw_handler
124 */
125 
126void _CPU_ISR_install_raw_handler(
127  unsigned32  vector,
128  proc_ptr    new_handler,
129  proc_ptr   *old_handler
130)
131{
132  /*
133   *  This is where we install the interrupt handler into the "raw" interrupt
134   *  table used by the CPU to dispatch interrupt handlers.
135   */
136/* Q: This will become necessary for Non IDT/Sim use...*/
137#if 0 /* not necessary */
138/* use IDT/Sim to set interrupt vector.  Needed to co-exist with debugger. */
139   add_ext_int_func( vector, new_handler );
140#endif
141}
142
143/*PAGE
144 *
145 *  _CPU_ISR_install_vector
146 *
147 *  This kernel routine installs the RTEMS handler for the
148 *  specified vector.
149 *
150 *  Input parameters:
151 *    vector      - interrupt vector number
152 *    old_handler - former ISR for this vector number
153 *    new_handler - replacement ISR for this vector number
154 *
155 *  Output parameters:  NONE
156 *
157 */
158
159void _CPU_ISR_install_vector(
160  unsigned32  vector,
161  proc_ptr    new_handler,
162  proc_ptr   *old_handler
163)
164{
165   *old_handler = _ISR_Vector_table[ vector ];
166
167   /*
168    *  If the interrupt vector table is a table of pointer to isr entry
169    *  points, then we need to install the appropriate RTEMS interrupt
170    *  handler for this vector number.
171    */
172
173   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
174
175   /*
176    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
177    *  be used by the _ISR_Handler so the user gets control.
178    */
179
180    _ISR_Vector_table[ vector ] = new_handler;
181}
182
183/*PAGE
184 *
185 *  _CPU_Install_interrupt_stack
186 */
187
188void _CPU_Install_interrupt_stack( void )
189{
190/* we don't support this yet */
191}
192
193/*PAGE
194 *
195 *  _CPU_Internal_threads_Idle_thread_body
196 *
197 *  NOTES:
198 *
199 *  1. This is the same as the regular CPU independent algorithm.
200 *
201 *  2. If you implement this using a "halt", "idle", or "shutdown"
202 *     instruction, then don't forget to put it in an infinite loop.
203 *
204 *  3. Be warned. Some processors with onboard DMA have been known
205 *     to stop the DMA if the CPU were put in IDLE mode.  This might
206 *     also be a problem with other on-chip peripherals.  So use this
207 *     hook with caution.
208 */
209
210void _CPU_Thread_Idle_body( void )
211{
212#if __mips == 3
213   for( ; ; )
214     asm volatile("wait"); /* use wait to enter low power mode */
215#elif __mips == 1
216   for( ; ; )
217     ;
218#else
219#error "IDLE: __mips not set to 1 or 3"
220#endif
221}
222
223extern void mips_break( int error );
224
225#include <stdio.h>
226
227void mips_fatal_error( int error )
228{
229   printf("fatal error 0x%x %d\n",error,error);
230   mips_break( error );
231}
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