source: rtems/c/src/exec/score/cpu/mips/cpu.c @ 3ad7c5d2

4.104.114.84.95
Last change on this file since 3ad7c5d2 was 3ad7c5d2, checked in by Joel Sherrill <joel.sherrill@…>, on 12/19/00 at 16:44:59

2000-12-19 Joel Sherrill <joel@…>

  • cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here because it has not been allocated yet.
  • Property mode set to 100644
File size: 5.5 KB
Line 
1/*
2 *  Mips CPU Dependent Source
3 *
4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
5 *           Joel Sherrill <joel@OARcorp.com>.
6 *
7 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
8 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
9 *
10 *         To anyone who acknowledges that this file is provided "AS IS"
11 *         without any express or implied warranty:
12 *             permission to use, copy, modify, and distribute this file
13 *             for any purpose is hereby granted without fee, provided that
14 *             the above copyright notice and this notice appears in all
15 *             copies, and that the name of Transition Networks not be used in
16 *             advertising or publicity pertaining to distribution of the
17 *             software without specific, written prior permission.
18 *             Transition Networks makes no representations about the
19 *             suitability of this software for any purpose.
20 *
21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
22 *
23 *  COPYRIGHT (c) 1989-1999.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.OARcorp.com/rtems/license.html.
29 *
30 *  $Id$
31 */
32
33/*
34 *  Rather than deleting this, it is commented out to (hopefully) help
35 *  the submitter send updates.
36 *
37 * static char _sccsid[] = "@(#)cpu.c 08/20/96     1.5\n";
38 */
39
40#include <rtems/system.h>
41#include <rtems/score/isr.h>
42#include <rtems/score/wkspace.h>
43
44
45/*  _CPU_Initialize
46 *
47 *  This routine performs processor dependent initialization.
48 *
49 *  INPUT PARAMETERS:
50 *    cpu_table       - CPU table to initialize
51 *    thread_dispatch - address of disptaching routine
52 */
53
54
55void _CPU_Initialize(
56  rtems_cpu_table  *cpu_table,
57  void      (*thread_dispatch)      /* ignored on this CPU */
58)
59{
60  /*
61   *  The thread_dispatch argument is the address of the entry point
62   *  for the routine called at the end of an ISR once it has been
63   *  decided a context switch is necessary.  On some compilation
64   *  systems it is difficult to call a high-level language routine
65   *  from assembly.  This allows us to trick these systems.
66   *
67   *  If you encounter this problem save the entry point in a CPU
68   *  dependent variable.
69   */
70
71  _CPU_Thread_dispatch_pointer = thread_dispatch;
72
73  /*
74   *  If there is not an easy way to initialize the FP context
75   *  during Context_Initialize, then it is usually easier to
76   *  save an "uninitialized" FP context here and copy it to
77   *  the task's during Context_Initialize.
78   */
79
80  /* FP context initialization support goes here */
81
82  _CPU_Table = *cpu_table;
83
84}
85
86/*PAGE
87 *
88 *  _CPU_ISR_Get_level
89 *
90 *  This routine returns the current interrupt level.
91 */
92   
93#if __mips == 3
94
95/* in cpu_asm.S for now */
96
97#elif __mips == 1
98unsigned32 _CPU_ISR_Get_level( void )
99{
100  unsigned int sr;
101
102  mips_get_sr(sr);
103
104  return ((sr & SR_IEC) ? 0 : 1);
105}
106#else
107#error "CPU ISR level: unknown MIPS level for SR handling"
108#endif
109
110/*PAGE
111 *
112 *  _CPU_ISR_install_raw_handler
113 */
114 
115void _CPU_ISR_install_raw_handler(
116  unsigned32  vector,
117  proc_ptr    new_handler,
118  proc_ptr   *old_handler
119)
120{
121  /*
122   *  This is where we install the interrupt handler into the "raw" interrupt
123   *  table used by the CPU to dispatch interrupt handlers.
124   */
125/* Q: This will become necessary for Non IDT/Sim use...*/
126#if 0 /* not necessary */
127/* use IDT/Sim to set interrupt vector.  Needed to co-exist with debugger. */
128   add_ext_int_func( vector, new_handler );
129#endif
130}
131
132/*PAGE
133 *
134 *  _CPU_ISR_install_vector
135 *
136 *  This kernel routine installs the RTEMS handler for the
137 *  specified vector.
138 *
139 *  Input parameters:
140 *    vector      - interrupt vector number
141 *    old_handler - former ISR for this vector number
142 *    new_handler - replacement ISR for this vector number
143 *
144 *  Output parameters:  NONE
145 *
146 */
147
148void _CPU_ISR_install_vector(
149  unsigned32  vector,
150  proc_ptr    new_handler,
151  proc_ptr   *old_handler
152)
153{
154   *old_handler = _ISR_Vector_table[ vector ];
155
156   /*
157    *  If the interrupt vector table is a table of pointer to isr entry
158    *  points, then we need to install the appropriate RTEMS interrupt
159    *  handler for this vector number.
160    */
161
162   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
163
164   /*
165    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
166    *  be used by the _ISR_Handler so the user gets control.
167    */
168
169    _ISR_Vector_table[ vector ] = new_handler;
170}
171
172/*PAGE
173 *
174 *  _CPU_Install_interrupt_stack
175 */
176
177void _CPU_Install_interrupt_stack( void )
178{
179/* we don't support this yet */
180}
181
182/*PAGE
183 *
184 *  _CPU_Internal_threads_Idle_thread_body
185 *
186 *  NOTES:
187 *
188 *  1. This is the same as the regular CPU independent algorithm.
189 *
190 *  2. If you implement this using a "halt", "idle", or "shutdown"
191 *     instruction, then don't forget to put it in an infinite loop.
192 *
193 *  3. Be warned. Some processors with onboard DMA have been known
194 *     to stop the DMA if the CPU were put in IDLE mode.  This might
195 *     also be a problem with other on-chip peripherals.  So use this
196 *     hook with caution.
197 */
198
199void _CPU_Thread_Idle_body( void )
200{
201#if __mips == 3
202   for( ; ; )
203     asm volatile("wait"); /* use wait to enter low power mode */
204#elif __mips == 1
205   for( ; ; )
206     ;
207#else
208#error "IDLE: __mips not set to 1 or 3"
209#endif
210}
211
212extern void mips_break( int error );
213
214#include <stdio.h>
215
216void mips_fatal_error( int error )
217{
218   printf("fatal error 0x%x %d\n",error,error);
219   mips_break( error );
220}
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