[f198c63] | 1 | /* |
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| 2 | * Mips CPU Dependent Source |
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| 3 | * |
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[fda47cd] | 4 | * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and |
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| 5 | * Joel Sherrill <joel@OARcorp.com>. |
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[f198c63] | 6 | * |
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[fda47cd] | 7 | * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> |
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| 8 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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[f198c63] | 9 | * |
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[fda47cd] | 10 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 11 | * without any express or implied warranty: |
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| 12 | * permission to use, copy, modify, and distribute this file |
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| 13 | * for any purpose is hereby granted without fee, provided that |
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| 14 | * the above copyright notice and this notice appears in all |
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| 15 | * copies, and that the name of Transition Networks not be used in |
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| 16 | * advertising or publicity pertaining to distribution of the |
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| 17 | * software without specific, written prior permission. |
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| 18 | * Transition Networks makes no representations about the |
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| 19 | * suitability of this software for any purpose. |
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[f198c63] | 20 | * |
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[fda47cd] | 21 | * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: |
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[f198c63] | 22 | * |
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[08311cc3] | 23 | * COPYRIGHT (c) 1989-1999. |
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[f198c63] | 24 | * On-Line Applications Research Corporation (OAR). |
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| 25 | * |
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[98e4ebf5] | 26 | * The license and distribution terms for this file may be |
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| 27 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 28 | * http://www.OARcorp.com/rtems/license.html. |
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[f198c63] | 29 | * |
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[cda277f] | 30 | * $Id$ |
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[f198c63] | 31 | */ |
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| 32 | |
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[32ef3dc] | 33 | /* |
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| 34 | * Rather than deleting this, it is commented out to (hopefully) help |
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| 35 | * the submitter send updates. |
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| 36 | * |
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| 37 | * static char _sccsid[] = "@(#)cpu.c 08/20/96 1.5\n"; |
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| 38 | */ |
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[f198c63] | 39 | |
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| 40 | #include <rtems/system.h> |
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| 41 | #include <rtems/score/isr.h> |
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| 42 | #include <rtems/score/wkspace.h> |
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| 43 | |
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| 44 | |
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| 45 | /* _CPU_Initialize |
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| 46 | * |
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| 47 | * This routine performs processor dependent initialization. |
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| 48 | * |
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| 49 | * INPUT PARAMETERS: |
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| 50 | * cpu_table - CPU table to initialize |
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| 51 | * thread_dispatch - address of disptaching routine |
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| 52 | */ |
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| 53 | |
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| 54 | |
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| 55 | void null_handler( void ) |
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| 56 | { |
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| 57 | } |
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| 58 | |
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| 59 | |
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| 60 | void _CPU_Initialize( |
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| 61 | rtems_cpu_table *cpu_table, |
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| 62 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 63 | ) |
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| 64 | { |
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| 65 | unsigned int i = ISR_NUMBER_OF_VECTORS; |
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| 66 | |
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[32f415d] | 67 | while ( i-- ) { |
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[f198c63] | 68 | _ISR_Vector_table[i] = (ISR_Handler_entry)null_handler; |
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| 69 | } |
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| 70 | |
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| 71 | /* |
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| 72 | * The thread_dispatch argument is the address of the entry point |
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| 73 | * for the routine called at the end of an ISR once it has been |
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| 74 | * decided a context switch is necessary. On some compilation |
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| 75 | * systems it is difficult to call a high-level language routine |
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| 76 | * from assembly. This allows us to trick these systems. |
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| 77 | * |
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| 78 | * If you encounter this problem save the entry point in a CPU |
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| 79 | * dependent variable. |
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| 80 | */ |
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| 81 | |
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| 82 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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| 83 | |
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| 84 | /* |
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| 85 | * If there is not an easy way to initialize the FP context |
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| 86 | * during Context_Initialize, then it is usually easier to |
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| 87 | * save an "uninitialized" FP context here and copy it to |
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| 88 | * the task's during Context_Initialize. |
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| 89 | */ |
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| 90 | |
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| 91 | /* FP context initialization support goes here */ |
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| 92 | |
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| 93 | _CPU_Table = *cpu_table; |
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| 94 | |
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| 95 | } |
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| 96 | |
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| 97 | /*PAGE |
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| 98 | * |
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| 99 | * _CPU_ISR_Get_level |
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[32f415d] | 100 | * |
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| 101 | * This routine returns the current interrupt level. |
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[f198c63] | 102 | */ |
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[32f415d] | 103 | |
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| 104 | #if __mips == 3 |
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| 105 | |
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| 106 | /* in cpu_asm.S for now */ |
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| 107 | |
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| 108 | #elif __mips == 1 |
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[f198c63] | 109 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 110 | { |
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[32f415d] | 111 | unsigned int sr; |
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| 112 | |
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| 113 | mips_get_sr(sr); |
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| 114 | |
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| 115 | return ((sr & SR_IEC) ? 0 : 1); |
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[f198c63] | 116 | } |
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[32f415d] | 117 | #else |
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| 118 | #error "CPU ISR level: unknown MIPS level for SR handling" |
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[f198c63] | 119 | #endif |
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| 120 | |
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| 121 | /*PAGE |
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| 122 | * |
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| 123 | * _CPU_ISR_install_raw_handler |
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| 124 | */ |
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| 125 | |
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| 126 | void _CPU_ISR_install_raw_handler( |
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| 127 | unsigned32 vector, |
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| 128 | proc_ptr new_handler, |
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| 129 | proc_ptr *old_handler |
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| 130 | ) |
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| 131 | { |
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| 132 | /* |
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| 133 | * This is where we install the interrupt handler into the "raw" interrupt |
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| 134 | * table used by the CPU to dispatch interrupt handlers. |
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| 135 | */ |
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[fda47cd] | 136 | /* Q: This will become necessary for Non IDT/Sim use...*/ |
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[f198c63] | 137 | #if 0 /* not necessary */ |
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| 138 | /* use IDT/Sim to set interrupt vector. Needed to co-exist with debugger. */ |
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| 139 | add_ext_int_func( vector, new_handler ); |
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| 140 | #endif |
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| 141 | } |
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| 142 | |
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| 143 | /*PAGE |
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| 144 | * |
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| 145 | * _CPU_ISR_install_vector |
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| 146 | * |
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| 147 | * This kernel routine installs the RTEMS handler for the |
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| 148 | * specified vector. |
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| 149 | * |
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| 150 | * Input parameters: |
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| 151 | * vector - interrupt vector number |
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| 152 | * old_handler - former ISR for this vector number |
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| 153 | * new_handler - replacement ISR for this vector number |
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| 154 | * |
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| 155 | * Output parameters: NONE |
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| 156 | * |
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| 157 | */ |
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| 158 | |
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| 159 | void _CPU_ISR_install_vector( |
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| 160 | unsigned32 vector, |
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| 161 | proc_ptr new_handler, |
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| 162 | proc_ptr *old_handler |
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| 163 | ) |
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| 164 | { |
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| 165 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 166 | |
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| 167 | /* |
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| 168 | * If the interrupt vector table is a table of pointer to isr entry |
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| 169 | * points, then we need to install the appropriate RTEMS interrupt |
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| 170 | * handler for this vector number. |
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| 171 | */ |
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| 172 | |
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| 173 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler ); |
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| 174 | |
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| 175 | /* |
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| 176 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 177 | * be used by the _ISR_Handler so the user gets control. |
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| 178 | */ |
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| 179 | |
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| 180 | _ISR_Vector_table[ vector ] = new_handler; |
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| 181 | } |
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| 182 | |
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| 183 | /*PAGE |
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| 184 | * |
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| 185 | * _CPU_Install_interrupt_stack |
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| 186 | */ |
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| 187 | |
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| 188 | void _CPU_Install_interrupt_stack( void ) |
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| 189 | { |
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| 190 | /* we don't support this yet */ |
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| 191 | } |
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| 192 | |
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| 193 | /*PAGE |
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| 194 | * |
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| 195 | * _CPU_Internal_threads_Idle_thread_body |
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| 196 | * |
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| 197 | * NOTES: |
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| 198 | * |
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| 199 | * 1. This is the same as the regular CPU independent algorithm. |
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| 200 | * |
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| 201 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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| 202 | * instruction, then don't forget to put it in an infinite loop. |
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| 203 | * |
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| 204 | * 3. Be warned. Some processors with onboard DMA have been known |
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| 205 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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| 206 | * also be a problem with other on-chip peripherals. So use this |
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| 207 | * hook with caution. |
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| 208 | */ |
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| 209 | |
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| 210 | void _CPU_Thread_Idle_body( void ) |
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| 211 | { |
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[32f415d] | 212 | #if __mips == 3 |
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| 213 | for( ; ; ) |
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| 214 | asm volatile("wait"); /* use wait to enter low power mode */ |
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| 215 | #elif __mips == 1 |
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| 216 | for( ; ; ) |
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| 217 | ; |
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| 218 | #else |
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| 219 | #error "IDLE: __mips not set to 1 or 3" |
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[f198c63] | 220 | #endif |
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[32f415d] | 221 | } |
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[f198c63] | 222 | |
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| 223 | extern void mips_break( int error ); |
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| 224 | |
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| 225 | #include <stdio.h> |
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| 226 | |
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| 227 | void mips_fatal_error( int error ) |
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| 228 | { |
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| 229 | printf("fatal error 0x%x %d\n",error,error); |
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| 230 | mips_break( error ); |
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| 231 | } |
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