source: rtems/c/src/exec/score/cpu/mips/ChangeLog @ e2040ba

4.104.114.84.95
Last change on this file since e2040ba was e2040ba, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2001 at 10:59:42 PM

2001-05-22 Greg Menke <gregory.menke@…>

  • rtems/score/cpu.h: Add the interrupt stack structure and enhance the context initialization to account for floating point tasks.
  • rtems/score/mips.h: Added the routines mips_set_cause(), mips_get_fcr31(), and mips_set_fcr31().
  • Assisted in design and debug by Joel Sherrill <joel@…>.
  • Property mode set to 100644
File size: 6.9 KB
Line 
12001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
2
3        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
4        the context initialization to account for floating point tasks. 
5        * rtems/score/mips.h: Added the routines mips_set_cause(),
6        mips_get_fcr31(), and mips_set_fcr31().
7        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
8
92001-05-07      Joel Sherrill <joel@OARcorp.com>
10
11        * cpu_asm.S: Merged patches from Gregory Menke
12        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
13        stack usage and include nops in the delay slots.
14
152001-04-20      Joel Sherrill <joel@OARcorp.com>
16
17        * cpu_asm.S: Added code to save and restore SR and EPC to
18        properly support nested interrupts.  Note that the ISR
19        (not RTEMS) enables interrupts allowing the nesting to occur.
20
212001-03-14      Joel Sherrill <joel@OARcorp.com>
22
23        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
24        Removed unused variable _CPU_Thread_dispatch_pointer
25        and cleaned numerous comments.
26       
272001-03-13      Joel Sherrill <joel@OARcorp.com>
28
29        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
30        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
31        Also reimplemented some assembly routines in C further reducing
32        the amount of assembly and increasing maintainability.
33
342001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
35
36        * Makefile.am, rtems/score/Makefile.am:
37        Apply include_*HEADERS instead of H_FILES.
38
392001-01-12      Joel Sherrill <joel@OARcorp.com>
40
41        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
42        register constraints from "general" to "register".
43
442001-01-09      Joel Sherrill <joel@OARcorp.com>
45
46        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
47        to make it easier to conditionalize the code for various ISA levels.
48
492001-01-08      Joel Sherrill <joel@OARcorp.com>
50
51        * idtcpu.h: Commented out definition of "wait".  It was stupid to
52        use such a common word as a macro.
53        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
54        * rtems/score/mips.h: Added include of <idtcpu.h>.
55        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
56
572001-01-03      Joel Sherrill <joel@OARcorp.com>
58
59        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
60        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
61
622000-12-19      Joel Sherrill <joel@OARcorp.com>
63
64        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
65        Previous code resulting in the interrupted immediately returning
66        to the caller of the routine it was inside.
67
682000-12-19      Joel Sherrill <joel@OARcorp.com>
69
70        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
71        because it has not been allocated yet.
72
732000-12-13      Joel Sherrill <joel@OARcorp.com>
74
75        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
76        * cpu_asm.S: Removed assembly language to vector ISR handler
77        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
78        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
79        longer a constant -- get the real value from libcpu.
80
812000-12-13      Joel Sherrill <joel@OARcorp.com>
82
83        * cpu_asm.h: Removed.
84        * Makefile.am: Remove cpu_asm.h.
85        * rtems/score/mips64orion.h: Renamed mips.h.
86        * rtems/score/mips.h: New file, formerly mips64orion.h.
87        Header rewritten.
88        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
89        mips_disable_in_interrupt_mask): New macros.
90        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
91        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
92        few defines that were in <cpu_asm.h>.
93        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
94        MIPS ISA 3 is still in assembly for now.
95        (_CPU_Thread_Idle_body): Rewrote in C.
96        * cpu_asm.S: Rewrote file header.
97        (FRAME,ENDFRAME) now in asm.h.
98        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
99        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
100        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
101        leaves other bits in SR alone on task switch.
102        (mips_enable_interrupts,mips_disable_interrupts,
103        mips_enable_global_interrupts,mips_disable_global_interrupts,
104        disable_int, enable_int): Removed.
105        (mips_get_sr): Rewritten as C macro.
106        (_CPU_Thread_Idle_body): Rewritten in C.
107        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
108        placed in libcpu.
109        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
110        to libcpu/mips/shared/interrupts.
111        (general): Cleaned up comment blocks and #if 0 areas.
112        * idtcpu.h: Made ifdef report an error.
113        * iregdef.h: Removed warning.
114        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
115        number defined by libcpu.
116        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
117        to access SR.
118        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
119        (_CPU_Context_Initialize): Honor ISR level in task initialization.
120        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
121
1222000-12-06      Joel Sherrill <joel@OARcorp.com>
123
124        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
125        context should be 32 not 64 bits.
126
1272000-11-30      Joel Sherrill <joel@OARcorp.com>
128
129        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
130        correct name of _CPU_Context_switch_restore.  Added dummy
131        version of exc_utlb_code() so applications would link.
132
1332000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
134
135        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
136
1372000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
138
139        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
140
1412000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
142
143        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
144        Switch to GNU canonicalization.
145
1462000-10-24      Alan Cudmore <alanc@linuxstart.com> and
147        Joel Sherrill <joel@OARcorp.com>
148
149        * This is a major reworking of the mips64orion port to use
150        gcc predefines as much as possible and a big push to multilib
151        the mips port.  The mips64orion port was copied/renamed to mips
152        to be more like other GNU tools.  Alan did most of the technical
153        work of determining how to map old macro names used by the mips64orion
154        port to standard compiler macro definitions.  Joel did the merge
155        with CVS magic to keep individual file history and did the BSP
156        modifications. Details follow:
157        * Makefile.am: idtmon.h in mips64orion port not present.
158        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
159        * cpu.c: Comments added.
160        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
161        First attempt at exception/interrupt processing for ISA level 1
162        and minus any use of IDT/MON added.
163        * idtcpu.h: Conditionals changed to use gcc predefines.
164        * iregdef.h: Ditto.
165        * cpu_asm.h: No real change.  Merger required commit.
166        * rtems/Makefile.am: Ditto.
167        * rtems/score/Makefile.am: Ditto.
168        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
169        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
170        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
171
1722000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
173
174        * Makefile.am: Include compile.am.
175
1762000-08-10      Joel Sherrill <joel@OARcorp.com>
177
178        * ChangeLog: New file.
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