source: rtems/c/src/exec/score/cpu/mips/ChangeLog @ af81910

4.104.114.84.95
Last change on this file since af81910 was af81910, checked in by Ralf Corsepius <ralf.corsepius@…>, on Jul 5, 2002 at 3:54:50 PM

2002-07-05 Ralf Corsepius <corsepiu@…>

  • configure.ac: RTEMS_TOP(../../../..).
  • Property mode set to 100644
File size: 12.7 KB
Line 
12002-07-05      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
2
3        * configure.ac: RTEMS_TOP(../../../..).
4
52002-07-03      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
6
7        * rtems.c: Remove.
8        * Makefile.am: Reflect changes above.
9
102002-07-01      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
11
12        * configure.ac: Remove RTEMS_PROJECT_ROOT.
13
142002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
15
16        * configure.ac: Add RTEMS_PROG_CCAS
17
182002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
19
20        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
21        Add AC_PROG_RANLIB.
22
232002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
24
25        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
26        Use ../../../aclocal.
27
282001-04-03      Joel Sherrill <joel@OARcorp.com>
29
30        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
31        * rtems/score/mipstypes.h: Removed.
32        * rtems/score/types.h: New file via CVS magic.
33        * Makefile.am, rtems/score/cpu.h: Account for name change.
34
352002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
36
37        * configure.ac:
38        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
39        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
40        * Makefile.am: Remove AUTOMAKE_OPTIONS.
41
422002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
43
44        * cpu_asm.S: Now compiles on 4600 and 4650.
45
462002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
47
48        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
49        * rtems/score/cpu.h: Fixed register numbering in comments and made
50        interrupt enable/disable more robust.
51       
522002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
53        * cpu_asm.S: Added support for the debug exception vector, cleaned
54        up the exception processing & exception return stuff.  Re-added
55        EPC in the task context structure so the gdb stub will know where
56        a thread is executing.  Should've left it there in the first place...
57        * idtcpu.h: Added support for the debug exception vector.
58        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
59        stack frame in an interrupt so context switch code can get the
60        userspace EPC when scheduling.
61        * rtems/score/cpu.h: Re-added EPC to the task context.
62
632002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
64
65        * cpu_asm.S: Fixed exception return address, modified FP context
66        switch so FPU is properly enabled and also doesn't screw up the
67        exception FP handling.
68        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
69        returning from exceptions.
70        * iregdef.h: Added R_TAR to the stack frame so the target address
71        can be saved on a per-exception basis.  The new entry is past the
72        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
73        stuff.
74        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
75        to obtain FPU defines without systax errors generated by the C
76        defintions.
77        * cpu.c: Improved interrupt level saves & restores.
78       
792002-02-08      Joel Sherrill <joel@OARcorp.com>
80
81        * iregdef.h, rtems/score/cpu.h: Reordered register in the
82        exception stack frame to better match gdb's expectations.
83
842001-02-05      Joel Sherrill <joel@OARcorp.com>
85
86        * cpu_asm.S: Enhanced to save/restore more registers on
87        exceptions.
88        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
89        register individually and document when it is saved.
90        * idtcpu.h: Added constants for the coprocessor 1 registers
91        revision and status.
92
932001-02-05      Joel Sherrill <joel@OARcorp.com>
94
95        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
96
972001-02-04      Joel Sherrill <joel@OARcorp.com>
98
99        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
100        in the previous patch that has now been confirmed.
101
1022001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
103
104        * cpu.c: Enhancements and fixes for modifying the SR when changing
105        the interrupt level.
106        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
107        managed on a per-task basis, improved handling of interrupt levels,
108        and made deferred FP contexts work on the MIPS.
109        * rtems/score/cpu.h: Modified to support above changes.
110
1112002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
112
113        * rtems/Makefile.am: Removed.
114        * rtems/score/Makefile.am: Removed.
115        * configure.ac: Reflect changes above.
116        * Makefile.am: Reflect changes above.
117
1182002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
119
120        * asm.h: Remove #include <rtems/score/targopts.h>.
121        Add #include <rtems/score/cpuopts.h>.
122        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
123
124
1252001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
126
127        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
128
1292001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
130
131        * Makefile.am: Add multilib support.
132
1332001-11-28      Joel Sherrill <joel@OARcorp.com>,
134
135        This was tracked as PR91.
136        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
137        is used to specify if the port uses the standard macro for this (FALSE).
138        A TRUE setting indicates the port provides its own implementation.
139
1402001-10-12      Joel Sherrill <joel@OARcorp.com>
141
142        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
143        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
144        Wayne Bullaughey <wayne@wmi.com>.
145
1462001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
147
148        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
149        * configure.in: Remove.
150        * configure.ac: New file, generated from configure.in by autoupdate.
151
1522001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
153
154        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
155        * Makefile.am: Use 'PREINSTALL_FILES ='.
156
1572001-07-03      Joel Sherrill <joel@OARcorp.com>
158
159        * cpu.c: Fixed typo.
160
1612000-05-24      Joel Sherrill <joel@OARcorp.com>
162
163        * rtems/score/mips.h: Added constants for MIPS exception numbers.
164        All exceptions should be given low numbers and thus can be installed
165        and processed in a uniform manner.  Variances between various MIPS
166        ISA levels were not accounted for.
167
1682001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
169
170        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
171        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
172
1732001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
174
175        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
176        the context initialization to account for floating point tasks. 
177        * rtems/score/mips.h: Added the routines mips_set_cause(),
178        mips_get_fcr31(), and mips_set_fcr31().
179        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
180
1812001-05-07      Joel Sherrill <joel@OARcorp.com>
182
183        * cpu_asm.S: Merged patches from Gregory Menke
184        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
185        stack usage and include nops in the delay slots.
186
1872001-04-20      Joel Sherrill <joel@OARcorp.com>
188
189        * cpu_asm.S: Added code to save and restore SR and EPC to
190        properly support nested interrupts.  Note that the ISR
191        (not RTEMS) enables interrupts allowing the nesting to occur.
192
1932001-03-14      Joel Sherrill <joel@OARcorp.com>
194
195        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
196        Removed unused variable _CPU_Thread_dispatch_pointer
197        and cleaned numerous comments.
198       
1992001-03-13      Joel Sherrill <joel@OARcorp.com>
200
201        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
202        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
203        Also reimplemented some assembly routines in C further reducing
204        the amount of assembly and increasing maintainability.
205
2062001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
207
208        * Makefile.am, rtems/score/Makefile.am:
209        Apply include_*HEADERS instead of H_FILES.
210
2112001-01-12      Joel Sherrill <joel@OARcorp.com>
212
213        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
214        register constraints from "general" to "register".
215
2162001-01-09      Joel Sherrill <joel@OARcorp.com>
217
218        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
219        to make it easier to conditionalize the code for various ISA levels.
220
2212001-01-08      Joel Sherrill <joel@OARcorp.com>
222
223        * idtcpu.h: Commented out definition of "wait".  It was stupid to
224        use such a common word as a macro.
225        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
226        * rtems/score/mips.h: Added include of <idtcpu.h>.
227        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
228
2292001-01-03      Joel Sherrill <joel@OARcorp.com>
230
231        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
232        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
233
2342000-12-19      Joel Sherrill <joel@OARcorp.com>
235
236        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
237        Previous code resulting in the interrupted immediately returning
238        to the caller of the routine it was inside.
239
2402000-12-19      Joel Sherrill <joel@OARcorp.com>
241
242        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
243        because it has not been allocated yet.
244
2452000-12-13      Joel Sherrill <joel@OARcorp.com>
246
247        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
248        * cpu_asm.S: Removed assembly language to vector ISR handler
249        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
250        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
251        longer a constant -- get the real value from libcpu.
252
2532000-12-13      Joel Sherrill <joel@OARcorp.com>
254
255        * cpu_asm.h: Removed.
256        * Makefile.am: Remove cpu_asm.h.
257        * rtems/score/mips64orion.h: Renamed mips.h.
258        * rtems/score/mips.h: New file, formerly mips64orion.h.
259        Header rewritten.
260        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
261        mips_disable_in_interrupt_mask): New macros.
262        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
263        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
264        few defines that were in <cpu_asm.h>.
265        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
266        MIPS ISA 3 is still in assembly for now.
267        (_CPU_Thread_Idle_body): Rewrote in C.
268        * cpu_asm.S: Rewrote file header.
269        (FRAME,ENDFRAME) now in asm.h.
270        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
271        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
272        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
273        leaves other bits in SR alone on task switch.
274        (mips_enable_interrupts,mips_disable_interrupts,
275        mips_enable_global_interrupts,mips_disable_global_interrupts,
276        disable_int, enable_int): Removed.
277        (mips_get_sr): Rewritten as C macro.
278        (_CPU_Thread_Idle_body): Rewritten in C.
279        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
280        placed in libcpu.
281        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
282        to libcpu/mips/shared/interrupts.
283        (general): Cleaned up comment blocks and #if 0 areas.
284        * idtcpu.h: Made ifdef report an error.
285        * iregdef.h: Removed warning.
286        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
287        number defined by libcpu.
288        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
289        to access SR.
290        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
291        (_CPU_Context_Initialize): Honor ISR level in task initialization.
292        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
293
2942000-12-06      Joel Sherrill <joel@OARcorp.com>
295
296        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
297        context should be 32 not 64 bits.
298
2992000-11-30      Joel Sherrill <joel@OARcorp.com>
300
301        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
302        correct name of _CPU_Context_switch_restore.  Added dummy
303        version of exc_utlb_code() so applications would link.
304
3052000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
306
307        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
308
3092000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
310
311        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
312
3132000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
314
315        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
316        Switch to GNU canonicalization.
317
3182000-10-24      Alan Cudmore <alanc@linuxstart.com> and
319        Joel Sherrill <joel@OARcorp.com>
320
321        * This is a major reworking of the mips64orion port to use
322        gcc predefines as much as possible and a big push to multilib
323        the mips port.  The mips64orion port was copied/renamed to mips
324        to be more like other GNU tools.  Alan did most of the technical
325        work of determining how to map old macro names used by the mips64orion
326        port to standard compiler macro definitions.  Joel did the merge
327        with CVS magic to keep individual file history and did the BSP
328        modifications. Details follow:
329        * Makefile.am: idtmon.h in mips64orion port not present.
330        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
331        * cpu.c: Comments added.
332        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
333        First attempt at exception/interrupt processing for ISA level 1
334        and minus any use of IDT/MON added.
335        * idtcpu.h: Conditionals changed to use gcc predefines.
336        * iregdef.h: Ditto.
337        * cpu_asm.h: No real change.  Merger required commit.
338        * rtems/Makefile.am: Ditto.
339        * rtems/score/Makefile.am: Ditto.
340        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
341        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
342        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
343
3442000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
345
346        * Makefile.am: Include compile.am.
347
3482000-08-10      Joel Sherrill <joel@OARcorp.com>
349
350        * ChangeLog: New file.
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