| 1 | 2001-01-12 Joel Sherrill <joel@OARcorp.com> |
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| 2 | |
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| 3 | * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected |
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| 4 | register constraints from "general" to "register". |
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| 5 | |
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| 6 | 2001-01-09 Joel Sherrill <joel@OARcorp.com> |
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| 7 | |
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| 8 | * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants |
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| 9 | to make it easier to conditionalize the code for various ISA levels. |
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| 10 | |
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| 11 | 2001-01-08 Joel Sherrill <joel@OARcorp.com> |
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| 12 | |
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| 13 | * idtcpu.h: Commented out definition of "wait". It was stupid to |
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| 14 | use such a common word as a macro. |
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| 15 | * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3. |
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| 16 | * rtems/score/mips.h: Added include of <idtcpu.h>. |
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| 17 | * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected. |
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| 18 | |
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| 19 | 2001-01-03 Joel Sherrill <joel@OARcorp.com> |
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| 20 | |
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| 21 | * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). |
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| 22 | * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN. |
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| 23 | |
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| 24 | 2000-12-19 Joel Sherrill <joel@OARcorp.com> |
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| 25 | |
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| 26 | * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register. |
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| 27 | Previous code resulting in the interrupted immediately returning |
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| 28 | to the caller of the routine it was inside. |
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| 29 | |
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| 30 | 2000-12-19 Joel Sherrill <joel@OARcorp.com> |
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| 31 | |
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| 32 | * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here |
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| 33 | because it has not been allocated yet. |
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| 34 | |
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| 35 | 2000-12-13 Joel Sherrill <joel@OARcorp.com> |
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| 36 | |
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| 37 | * cpu.c: Removed duplicate declaration for _ISR_Vector_table. |
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| 38 | * cpu_asm.S: Removed assembly language to vector ISR handler |
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| 39 | on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP. |
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| 40 | * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No |
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| 41 | longer a constant -- get the real value from libcpu. |
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| 42 | |
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| 43 | 2000-12-13 Joel Sherrill <joel@OARcorp.com> |
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| 44 | |
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| 45 | * cpu_asm.h: Removed. |
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| 46 | * Makefile.am: Remove cpu_asm.h. |
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| 47 | * rtems/score/mips64orion.h: Renamed mips.h. |
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| 48 | * rtems/score/mips.h: New file, formerly mips64orion.h. |
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| 49 | Header rewritten. |
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| 50 | (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, |
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| 51 | mips_disable_in_interrupt_mask): New macros. |
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| 52 | * rtems/score/Makefile.am: Reflect renaming mips64orion.h. |
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| 53 | * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the |
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| 54 | few defines that were in <cpu_asm.h>. |
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| 55 | * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. |
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| 56 | MIPS ISA 3 is still in assembly for now. |
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| 57 | (_CPU_Thread_Idle_body): Rewrote in C. |
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| 58 | * cpu_asm.S: Rewrote file header. |
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| 59 | (FRAME,ENDFRAME) now in asm.h. |
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| 60 | (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. |
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| 61 | (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. |
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| 62 | (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and |
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| 63 | leaves other bits in SR alone on task switch. |
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| 64 | (mips_enable_interrupts,mips_disable_interrupts, |
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| 65 | mips_enable_global_interrupts,mips_disable_global_interrupts, |
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| 66 | disable_int, enable_int): Removed. |
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| 67 | (mips_get_sr): Rewritten as C macro. |
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| 68 | (_CPU_Thread_Idle_body): Rewritten in C. |
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| 69 | (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and |
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| 70 | placed in libcpu. |
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| 71 | (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved |
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| 72 | to libcpu/mips/shared/interrupts. |
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| 73 | (general): Cleaned up comment blocks and #if 0 areas. |
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| 74 | * idtcpu.h: Made ifdef report an error. |
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| 75 | * iregdef.h: Removed warning. |
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| 76 | * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable |
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| 77 | number defined by libcpu. |
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| 78 | (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines |
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| 79 | to access SR. |
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| 80 | (_CPU_ISR_Set_level): Rewritten as macro for ISA I. |
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| 81 | (_CPU_Context_Initialize): Honor ISR level in task initialization. |
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| 82 | (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro. |
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| 83 | |
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| 84 | 2000-12-06 Joel Sherrill <joel@OARcorp.com> |
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| 85 | |
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| 86 | * rtems/score/cpu.h: When mips ISA level is 1, registers in the |
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| 87 | context should be 32 not 64 bits. |
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| 88 | |
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| 89 | 2000-11-30 Joel Sherrill <joel@OARcorp.com> |
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| 90 | |
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| 91 | * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to |
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| 92 | correct name of _CPU_Context_switch_restore. Added dummy |
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| 93 | version of exc_utlb_code() so applications would link. |
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| 94 | |
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| 95 | 2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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| 96 | |
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| 97 | * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. |
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| 98 | |
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| 99 | 2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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| 100 | |
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| 101 | * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. |
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| 102 | |
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| 103 | 2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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| 104 | |
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| 105 | * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. |
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| 106 | Switch to GNU canonicalization. |
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| 107 | |
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| 108 | 2000-10-24 Alan Cudmore <alanc@linuxstart.com> and |
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| 109 | Joel Sherrill <joel@OARcorp.com> |
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| 110 | |
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| 111 | * This is a major reworking of the mips64orion port to use |
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| 112 | gcc predefines as much as possible and a big push to multilib |
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| 113 | the mips port. The mips64orion port was copied/renamed to mips |
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| 114 | to be more like other GNU tools. Alan did most of the technical |
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| 115 | work of determining how to map old macro names used by the mips64orion |
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| 116 | port to standard compiler macro definitions. Joel did the merge |
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| 117 | with CVS magic to keep individual file history and did the BSP |
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| 118 | modifications. Details follow: |
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| 119 | * Makefile.am: idtmon.h in mips64orion port not present. |
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| 120 | * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added. |
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| 121 | * cpu.c: Comments added. |
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| 122 | * cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added. |
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| 123 | First attempt at exception/interrupt processing for ISA level 1 |
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| 124 | and minus any use of IDT/MON added. |
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| 125 | * idtcpu.h: Conditionals changed to use gcc predefines. |
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| 126 | * iregdef.h: Ditto. |
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| 127 | * cpu_asm.h: No real change. Merger required commit. |
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| 128 | * rtems/Makefile.am: Ditto. |
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| 129 | * rtems/score/Makefile.am: Ditto. |
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| 130 | * rtems/score/cpu.h: Change MIPS64ORION to MIPS. |
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| 131 | * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert |
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| 132 | from using RTEMS_CPU_MODEL to gcc predefines to figre things out. |
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| 133 | |
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| 134 | 2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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| 135 | |
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| 136 | * Makefile.am: Include compile.am. |
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| 137 | |
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| 138 | 2000-08-10 Joel Sherrill <joel@OARcorp.com> |
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| 139 | |
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| 140 | * ChangeLog: New file. |
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