source: rtems/c/src/exec/score/cpu/mips/ChangeLog @ 9099a85

4.104.114.84.95
Last change on this file since 9099a85 was 9099a85, checked in by Joel Sherrill <joel.sherrill@…>, on 02/08/02 at 23:04:03

2002-02-08 Joel Sherrill <joel@…>

  • iregdef.h, rtems/score/cpu.h: Reordered register in the exception stack frame to better match gdb's expectations.
  • Property mode set to 100644
File size: 10.0 KB
Line 
12002-02-08      Joel Sherrill <joel@OARcorp.com>
2
3        * iregdef.h, rtems/score/cpu.h: Reordered register in the
4        exception stack frame to better match gdb's expectations.
5
62001-02-05      Joel Sherrill <joel@OARcorp.com>
7
8        * cpu_asm.S: Enhanced to save/restore more registers on
9        exceptions.
10        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
11        register individually and document when it is saved.
12        * idtcpu.h: Added constants for the coprocessor 1 registers
13        revision and status.
14
152001-02-05      Joel Sherrill <joel@OARcorp.com>
16
17        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
18
192001-02-04      Joel Sherrill <joel@OARcorp.com>
20
21        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
22        in the previous patch that has now been confirmed.
23
242001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
25
26        * cpu.c: Enhancements and fixes for modifying the SR when changing
27        the interrupt level.
28        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
29        managed on a per-task basis, improved handling of interrupt levels,
30        and made deferred FP contexts work on the MIPS.
31        * rtems/score/cpu.h: Modified to support above changes.
32
332002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
34
35        * rtems/Makefile.am: Removed.
36        * rtems/score/Makefile.am: Removed.
37        * configure.ac: Reflect changes above.
38        * Makefile.am: Reflect changes above.
39
402002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
41
42        * asm.h: Remove #include <rtems/score/targopts.h>.
43        Add #include <rtems/score/cpuopts.h>.
44        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
45
46
472001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
48
49        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
50
512001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
52
53        * Makefile.am: Add multilib support.
54
552001-11-28      Joel Sherrill <joel@OARcorp.com>,
56
57        This was tracked as PR91.
58        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
59        is used to specify if the port uses the standard macro for this (FALSE).
60        A TRUE setting indicates the port provides its own implementation.
61
622001-10-12      Joel Sherrill <joel@OARcorp.com>
63
64        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
65        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
66        Wayne Bullaughey <wayne@wmi.com>.
67
682001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
69
70        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
71        * configure.in: Remove.
72        * configure.ac: New file, generated from configure.in by autoupdate.
73
742001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
75
76        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
77        * Makefile.am: Use 'PREINSTALL_FILES ='.
78
792001-07-03      Joel Sherrill <joel@OARcorp.com>
80
81        * cpu.c: Fixed typo.
82
832000-05-24      Joel Sherrill <joel@OARcorp.com>
84
85        * rtems/score/mips.h: Added constants for MIPS exception numbers.
86        All exceptions should be given low numbers and thus can be installed
87        and processed in a uniform manner.  Variances between various MIPS
88        ISA levels were not accounted for.
89
902001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
91
92        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
93        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
94
952001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
96
97        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
98        the context initialization to account for floating point tasks. 
99        * rtems/score/mips.h: Added the routines mips_set_cause(),
100        mips_get_fcr31(), and mips_set_fcr31().
101        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
102
1032001-05-07      Joel Sherrill <joel@OARcorp.com>
104
105        * cpu_asm.S: Merged patches from Gregory Menke
106        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
107        stack usage and include nops in the delay slots.
108
1092001-04-20      Joel Sherrill <joel@OARcorp.com>
110
111        * cpu_asm.S: Added code to save and restore SR and EPC to
112        properly support nested interrupts.  Note that the ISR
113        (not RTEMS) enables interrupts allowing the nesting to occur.
114
1152001-03-14      Joel Sherrill <joel@OARcorp.com>
116
117        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
118        Removed unused variable _CPU_Thread_dispatch_pointer
119        and cleaned numerous comments.
120       
1212001-03-13      Joel Sherrill <joel@OARcorp.com>
122
123        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
124        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
125        Also reimplemented some assembly routines in C further reducing
126        the amount of assembly and increasing maintainability.
127
1282001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
129
130        * Makefile.am, rtems/score/Makefile.am:
131        Apply include_*HEADERS instead of H_FILES.
132
1332001-01-12      Joel Sherrill <joel@OARcorp.com>
134
135        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
136        register constraints from "general" to "register".
137
1382001-01-09      Joel Sherrill <joel@OARcorp.com>
139
140        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
141        to make it easier to conditionalize the code for various ISA levels.
142
1432001-01-08      Joel Sherrill <joel@OARcorp.com>
144
145        * idtcpu.h: Commented out definition of "wait".  It was stupid to
146        use such a common word as a macro.
147        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
148        * rtems/score/mips.h: Added include of <idtcpu.h>.
149        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
150
1512001-01-03      Joel Sherrill <joel@OARcorp.com>
152
153        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
154        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
155
1562000-12-19      Joel Sherrill <joel@OARcorp.com>
157
158        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
159        Previous code resulting in the interrupted immediately returning
160        to the caller of the routine it was inside.
161
1622000-12-19      Joel Sherrill <joel@OARcorp.com>
163
164        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
165        because it has not been allocated yet.
166
1672000-12-13      Joel Sherrill <joel@OARcorp.com>
168
169        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
170        * cpu_asm.S: Removed assembly language to vector ISR handler
171        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
172        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
173        longer a constant -- get the real value from libcpu.
174
1752000-12-13      Joel Sherrill <joel@OARcorp.com>
176
177        * cpu_asm.h: Removed.
178        * Makefile.am: Remove cpu_asm.h.
179        * rtems/score/mips64orion.h: Renamed mips.h.
180        * rtems/score/mips.h: New file, formerly mips64orion.h.
181        Header rewritten.
182        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
183        mips_disable_in_interrupt_mask): New macros.
184        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
185        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
186        few defines that were in <cpu_asm.h>.
187        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
188        MIPS ISA 3 is still in assembly for now.
189        (_CPU_Thread_Idle_body): Rewrote in C.
190        * cpu_asm.S: Rewrote file header.
191        (FRAME,ENDFRAME) now in asm.h.
192        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
193        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
194        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
195        leaves other bits in SR alone on task switch.
196        (mips_enable_interrupts,mips_disable_interrupts,
197        mips_enable_global_interrupts,mips_disable_global_interrupts,
198        disable_int, enable_int): Removed.
199        (mips_get_sr): Rewritten as C macro.
200        (_CPU_Thread_Idle_body): Rewritten in C.
201        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
202        placed in libcpu.
203        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
204        to libcpu/mips/shared/interrupts.
205        (general): Cleaned up comment blocks and #if 0 areas.
206        * idtcpu.h: Made ifdef report an error.
207        * iregdef.h: Removed warning.
208        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
209        number defined by libcpu.
210        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
211        to access SR.
212        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
213        (_CPU_Context_Initialize): Honor ISR level in task initialization.
214        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
215
2162000-12-06      Joel Sherrill <joel@OARcorp.com>
217
218        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
219        context should be 32 not 64 bits.
220
2212000-11-30      Joel Sherrill <joel@OARcorp.com>
222
223        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
224        correct name of _CPU_Context_switch_restore.  Added dummy
225        version of exc_utlb_code() so applications would link.
226
2272000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
228
229        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
230
2312000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
232
233        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
234
2352000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
236
237        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
238        Switch to GNU canonicalization.
239
2402000-10-24      Alan Cudmore <alanc@linuxstart.com> and
241        Joel Sherrill <joel@OARcorp.com>
242
243        * This is a major reworking of the mips64orion port to use
244        gcc predefines as much as possible and a big push to multilib
245        the mips port.  The mips64orion port was copied/renamed to mips
246        to be more like other GNU tools.  Alan did most of the technical
247        work of determining how to map old macro names used by the mips64orion
248        port to standard compiler macro definitions.  Joel did the merge
249        with CVS magic to keep individual file history and did the BSP
250        modifications. Details follow:
251        * Makefile.am: idtmon.h in mips64orion port not present.
252        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
253        * cpu.c: Comments added.
254        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
255        First attempt at exception/interrupt processing for ISA level 1
256        and minus any use of IDT/MON added.
257        * idtcpu.h: Conditionals changed to use gcc predefines.
258        * iregdef.h: Ditto.
259        * cpu_asm.h: No real change.  Merger required commit.
260        * rtems/Makefile.am: Ditto.
261        * rtems/score/Makefile.am: Ditto.
262        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
263        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
264        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
265
2662000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
267
268        * Makefile.am: Include compile.am.
269
2702000-08-10      Joel Sherrill <joel@OARcorp.com>
271
272        * ChangeLog: New file.
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