source: rtems/c/src/exec/score/cpu/mips/ChangeLog @ 77b8106

4.104.114.84.95
Last change on this file since 77b8106 was 77b8106, checked in by Joel Sherrill <joel.sherrill@…>, on 07/03/01 at 16:58:56

2001-07-03 Joel Sherrill <joel@…>

  • cpu.c: Fixed typo.
  • Property mode set to 100644
File size: 7.4 KB
Line 
12001-07-03      Joel Sherrill <joel@OARcorp.com>
2
3        * cpu.c: Fixed typo.
4
52000-05-24      Joel Sherrill <joel@OARcorp.com>
6
7        * rtems/score/mips.h: Added constants for MIPS exception numbers.
8        All exceptions should be given low numbers and thus can be installed
9        and processed in a uniform manner.  Variances between various MIPS
10        ISA levels were not accounted for.
11
122001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
13
14        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
15        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
16
172001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
18
19        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
20        the context initialization to account for floating point tasks. 
21        * rtems/score/mips.h: Added the routines mips_set_cause(),
22        mips_get_fcr31(), and mips_set_fcr31().
23        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
24
252001-05-07      Joel Sherrill <joel@OARcorp.com>
26
27        * cpu_asm.S: Merged patches from Gregory Menke
28        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
29        stack usage and include nops in the delay slots.
30
312001-04-20      Joel Sherrill <joel@OARcorp.com>
32
33        * cpu_asm.S: Added code to save and restore SR and EPC to
34        properly support nested interrupts.  Note that the ISR
35        (not RTEMS) enables interrupts allowing the nesting to occur.
36
372001-03-14      Joel Sherrill <joel@OARcorp.com>
38
39        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
40        Removed unused variable _CPU_Thread_dispatch_pointer
41        and cleaned numerous comments.
42       
432001-03-13      Joel Sherrill <joel@OARcorp.com>
44
45        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
46        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
47        Also reimplemented some assembly routines in C further reducing
48        the amount of assembly and increasing maintainability.
49
502001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
51
52        * Makefile.am, rtems/score/Makefile.am:
53        Apply include_*HEADERS instead of H_FILES.
54
552001-01-12      Joel Sherrill <joel@OARcorp.com>
56
57        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
58        register constraints from "general" to "register".
59
602001-01-09      Joel Sherrill <joel@OARcorp.com>
61
62        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
63        to make it easier to conditionalize the code for various ISA levels.
64
652001-01-08      Joel Sherrill <joel@OARcorp.com>
66
67        * idtcpu.h: Commented out definition of "wait".  It was stupid to
68        use such a common word as a macro.
69        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
70        * rtems/score/mips.h: Added include of <idtcpu.h>.
71        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
72
732001-01-03      Joel Sherrill <joel@OARcorp.com>
74
75        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
76        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
77
782000-12-19      Joel Sherrill <joel@OARcorp.com>
79
80        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
81        Previous code resulting in the interrupted immediately returning
82        to the caller of the routine it was inside.
83
842000-12-19      Joel Sherrill <joel@OARcorp.com>
85
86        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
87        because it has not been allocated yet.
88
892000-12-13      Joel Sherrill <joel@OARcorp.com>
90
91        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
92        * cpu_asm.S: Removed assembly language to vector ISR handler
93        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
94        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
95        longer a constant -- get the real value from libcpu.
96
972000-12-13      Joel Sherrill <joel@OARcorp.com>
98
99        * cpu_asm.h: Removed.
100        * Makefile.am: Remove cpu_asm.h.
101        * rtems/score/mips64orion.h: Renamed mips.h.
102        * rtems/score/mips.h: New file, formerly mips64orion.h.
103        Header rewritten.
104        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
105        mips_disable_in_interrupt_mask): New macros.
106        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
107        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
108        few defines that were in <cpu_asm.h>.
109        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
110        MIPS ISA 3 is still in assembly for now.
111        (_CPU_Thread_Idle_body): Rewrote in C.
112        * cpu_asm.S: Rewrote file header.
113        (FRAME,ENDFRAME) now in asm.h.
114        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
115        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
116        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
117        leaves other bits in SR alone on task switch.
118        (mips_enable_interrupts,mips_disable_interrupts,
119        mips_enable_global_interrupts,mips_disable_global_interrupts,
120        disable_int, enable_int): Removed.
121        (mips_get_sr): Rewritten as C macro.
122        (_CPU_Thread_Idle_body): Rewritten in C.
123        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
124        placed in libcpu.
125        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
126        to libcpu/mips/shared/interrupts.
127        (general): Cleaned up comment blocks and #if 0 areas.
128        * idtcpu.h: Made ifdef report an error.
129        * iregdef.h: Removed warning.
130        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
131        number defined by libcpu.
132        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
133        to access SR.
134        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
135        (_CPU_Context_Initialize): Honor ISR level in task initialization.
136        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
137
1382000-12-06      Joel Sherrill <joel@OARcorp.com>
139
140        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
141        context should be 32 not 64 bits.
142
1432000-11-30      Joel Sherrill <joel@OARcorp.com>
144
145        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
146        correct name of _CPU_Context_switch_restore.  Added dummy
147        version of exc_utlb_code() so applications would link.
148
1492000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
150
151        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
152
1532000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
154
155        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
156
1572000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
158
159        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
160        Switch to GNU canonicalization.
161
1622000-10-24      Alan Cudmore <alanc@linuxstart.com> and
163        Joel Sherrill <joel@OARcorp.com>
164
165        * This is a major reworking of the mips64orion port to use
166        gcc predefines as much as possible and a big push to multilib
167        the mips port.  The mips64orion port was copied/renamed to mips
168        to be more like other GNU tools.  Alan did most of the technical
169        work of determining how to map old macro names used by the mips64orion
170        port to standard compiler macro definitions.  Joel did the merge
171        with CVS magic to keep individual file history and did the BSP
172        modifications. Details follow:
173        * Makefile.am: idtmon.h in mips64orion port not present.
174        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
175        * cpu.c: Comments added.
176        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
177        First attempt at exception/interrupt processing for ISA level 1
178        and minus any use of IDT/MON added.
179        * idtcpu.h: Conditionals changed to use gcc predefines.
180        * iregdef.h: Ditto.
181        * cpu_asm.h: No real change.  Merger required commit.
182        * rtems/Makefile.am: Ditto.
183        * rtems/score/Makefile.am: Ditto.
184        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
185        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
186        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
187
1882000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
189
190        * Makefile.am: Include compile.am.
191
1922000-08-10      Joel Sherrill <joel@OARcorp.com>
193
194        * ChangeLog: New file.
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