source: rtems/c/src/exec/score/cpu/mips/ChangeLog @ 7273b6e

4.104.114.84.95
Last change on this file since 7273b6e was 7273b6e, checked in by Joel Sherrill <joel.sherrill@…>, on 03/28/02 at 00:54:58

2002-03-27 Ralf Corsepius <corsepiu@…>

  • configure.ac: AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). AM_INIT_AUTOMAKE([no-define foreign 1.6]).
  • Makefile.am: Remove AUTOMAKE_OPTIONS.
  • Property mode set to 100644
File size: 11.8 KB
Line 
12002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
2
3        * configure.ac:
4        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
5        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
6        * Makefile.am: Remove AUTOMAKE_OPTIONS.
7
82002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
9
10        * cpu_asm.S: Now compiles on 4600 and 4650.
11
122002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
13
14        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
15        * rtems/score/cpu.h: Fixed register numbering in comments and made
16        interrupt enable/disable more robust.
17       
182002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
19        * cpu_asm.S: Added support for the debug exception vector, cleaned
20        up the exception processing & exception return stuff.  Re-added
21        EPC in the task context structure so the gdb stub will know where
22        a thread is executing.  Should've left it there in the first place...
23        * idtcpu.h: Added support for the debug exception vector.
24        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
25        stack frame in an interrupt so context switch code can get the
26        userspace EPC when scheduling.
27        * rtems/score/cpu.h: Re-added EPC to the task context.
28
292002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
30
31        * cpu_asm.S: Fixed exception return address, modified FP context
32        switch so FPU is properly enabled and also doesn't screw up the
33        exception FP handling.
34        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
35        returning from exceptions.
36        * iregdef.h: Added R_TAR to the stack frame so the target address
37        can be saved on a per-exception basis.  The new entry is past the
38        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
39        stuff.
40        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
41        to obtain FPU defines without systax errors generated by the C
42        defintions.
43        * cpu.c: Improved interrupt level saves & restores.
44       
452002-02-08      Joel Sherrill <joel@OARcorp.com>
46
47        * iregdef.h, rtems/score/cpu.h: Reordered register in the
48        exception stack frame to better match gdb's expectations.
49
502001-02-05      Joel Sherrill <joel@OARcorp.com>
51
52        * cpu_asm.S: Enhanced to save/restore more registers on
53        exceptions.
54        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
55        register individually and document when it is saved.
56        * idtcpu.h: Added constants for the coprocessor 1 registers
57        revision and status.
58
592001-02-05      Joel Sherrill <joel@OARcorp.com>
60
61        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
62
632001-02-04      Joel Sherrill <joel@OARcorp.com>
64
65        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
66        in the previous patch that has now been confirmed.
67
682001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
69
70        * cpu.c: Enhancements and fixes for modifying the SR when changing
71        the interrupt level.
72        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
73        managed on a per-task basis, improved handling of interrupt levels,
74        and made deferred FP contexts work on the MIPS.
75        * rtems/score/cpu.h: Modified to support above changes.
76
772002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
78
79        * rtems/Makefile.am: Removed.
80        * rtems/score/Makefile.am: Removed.
81        * configure.ac: Reflect changes above.
82        * Makefile.am: Reflect changes above.
83
842002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
85
86        * asm.h: Remove #include <rtems/score/targopts.h>.
87        Add #include <rtems/score/cpuopts.h>.
88        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
89
90
912001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
92
93        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
94
952001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
96
97        * Makefile.am: Add multilib support.
98
992001-11-28      Joel Sherrill <joel@OARcorp.com>,
100
101        This was tracked as PR91.
102        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
103        is used to specify if the port uses the standard macro for this (FALSE).
104        A TRUE setting indicates the port provides its own implementation.
105
1062001-10-12      Joel Sherrill <joel@OARcorp.com>
107
108        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
109        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
110        Wayne Bullaughey <wayne@wmi.com>.
111
1122001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
113
114        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
115        * configure.in: Remove.
116        * configure.ac: New file, generated from configure.in by autoupdate.
117
1182001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
119
120        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
121        * Makefile.am: Use 'PREINSTALL_FILES ='.
122
1232001-07-03      Joel Sherrill <joel@OARcorp.com>
124
125        * cpu.c: Fixed typo.
126
1272000-05-24      Joel Sherrill <joel@OARcorp.com>
128
129        * rtems/score/mips.h: Added constants for MIPS exception numbers.
130        All exceptions should be given low numbers and thus can be installed
131        and processed in a uniform manner.  Variances between various MIPS
132        ISA levels were not accounted for.
133
1342001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
135
136        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
137        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
138
1392001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
140
141        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
142        the context initialization to account for floating point tasks. 
143        * rtems/score/mips.h: Added the routines mips_set_cause(),
144        mips_get_fcr31(), and mips_set_fcr31().
145        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
146
1472001-05-07      Joel Sherrill <joel@OARcorp.com>
148
149        * cpu_asm.S: Merged patches from Gregory Menke
150        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
151        stack usage and include nops in the delay slots.
152
1532001-04-20      Joel Sherrill <joel@OARcorp.com>
154
155        * cpu_asm.S: Added code to save and restore SR and EPC to
156        properly support nested interrupts.  Note that the ISR
157        (not RTEMS) enables interrupts allowing the nesting to occur.
158
1592001-03-14      Joel Sherrill <joel@OARcorp.com>
160
161        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
162        Removed unused variable _CPU_Thread_dispatch_pointer
163        and cleaned numerous comments.
164       
1652001-03-13      Joel Sherrill <joel@OARcorp.com>
166
167        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
168        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
169        Also reimplemented some assembly routines in C further reducing
170        the amount of assembly and increasing maintainability.
171
1722001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
173
174        * Makefile.am, rtems/score/Makefile.am:
175        Apply include_*HEADERS instead of H_FILES.
176
1772001-01-12      Joel Sherrill <joel@OARcorp.com>
178
179        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
180        register constraints from "general" to "register".
181
1822001-01-09      Joel Sherrill <joel@OARcorp.com>
183
184        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
185        to make it easier to conditionalize the code for various ISA levels.
186
1872001-01-08      Joel Sherrill <joel@OARcorp.com>
188
189        * idtcpu.h: Commented out definition of "wait".  It was stupid to
190        use such a common word as a macro.
191        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
192        * rtems/score/mips.h: Added include of <idtcpu.h>.
193        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
194
1952001-01-03      Joel Sherrill <joel@OARcorp.com>
196
197        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
198        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
199
2002000-12-19      Joel Sherrill <joel@OARcorp.com>
201
202        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
203        Previous code resulting in the interrupted immediately returning
204        to the caller of the routine it was inside.
205
2062000-12-19      Joel Sherrill <joel@OARcorp.com>
207
208        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
209        because it has not been allocated yet.
210
2112000-12-13      Joel Sherrill <joel@OARcorp.com>
212
213        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
214        * cpu_asm.S: Removed assembly language to vector ISR handler
215        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
216        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
217        longer a constant -- get the real value from libcpu.
218
2192000-12-13      Joel Sherrill <joel@OARcorp.com>
220
221        * cpu_asm.h: Removed.
222        * Makefile.am: Remove cpu_asm.h.
223        * rtems/score/mips64orion.h: Renamed mips.h.
224        * rtems/score/mips.h: New file, formerly mips64orion.h.
225        Header rewritten.
226        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
227        mips_disable_in_interrupt_mask): New macros.
228        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
229        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
230        few defines that were in <cpu_asm.h>.
231        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
232        MIPS ISA 3 is still in assembly for now.
233        (_CPU_Thread_Idle_body): Rewrote in C.
234        * cpu_asm.S: Rewrote file header.
235        (FRAME,ENDFRAME) now in asm.h.
236        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
237        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
238        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
239        leaves other bits in SR alone on task switch.
240        (mips_enable_interrupts,mips_disable_interrupts,
241        mips_enable_global_interrupts,mips_disable_global_interrupts,
242        disable_int, enable_int): Removed.
243        (mips_get_sr): Rewritten as C macro.
244        (_CPU_Thread_Idle_body): Rewritten in C.
245        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
246        placed in libcpu.
247        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
248        to libcpu/mips/shared/interrupts.
249        (general): Cleaned up comment blocks and #if 0 areas.
250        * idtcpu.h: Made ifdef report an error.
251        * iregdef.h: Removed warning.
252        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
253        number defined by libcpu.
254        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
255        to access SR.
256        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
257        (_CPU_Context_Initialize): Honor ISR level in task initialization.
258        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
259
2602000-12-06      Joel Sherrill <joel@OARcorp.com>
261
262        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
263        context should be 32 not 64 bits.
264
2652000-11-30      Joel Sherrill <joel@OARcorp.com>
266
267        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
268        correct name of _CPU_Context_switch_restore.  Added dummy
269        version of exc_utlb_code() so applications would link.
270
2712000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
272
273        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
274
2752000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
276
277        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
278
2792000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
280
281        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
282        Switch to GNU canonicalization.
283
2842000-10-24      Alan Cudmore <alanc@linuxstart.com> and
285        Joel Sherrill <joel@OARcorp.com>
286
287        * This is a major reworking of the mips64orion port to use
288        gcc predefines as much as possible and a big push to multilib
289        the mips port.  The mips64orion port was copied/renamed to mips
290        to be more like other GNU tools.  Alan did most of the technical
291        work of determining how to map old macro names used by the mips64orion
292        port to standard compiler macro definitions.  Joel did the merge
293        with CVS magic to keep individual file history and did the BSP
294        modifications. Details follow:
295        * Makefile.am: idtmon.h in mips64orion port not present.
296        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
297        * cpu.c: Comments added.
298        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
299        First attempt at exception/interrupt processing for ISA level 1
300        and minus any use of IDT/MON added.
301        * idtcpu.h: Conditionals changed to use gcc predefines.
302        * iregdef.h: Ditto.
303        * cpu_asm.h: No real change.  Merger required commit.
304        * rtems/Makefile.am: Ditto.
305        * rtems/score/Makefile.am: Ditto.
306        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
307        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
308        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
309
3102000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
311
312        * Makefile.am: Include compile.am.
313
3142000-08-10      Joel Sherrill <joel@OARcorp.com>
315
316        * ChangeLog: New file.
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