source: rtems/c/src/exec/score/cpu/mips/ChangeLog @ 684eebc8

4.104.114.84.95
Last change on this file since 684eebc8 was 684eebc8, checked in by Joel Sherrill <joel.sherrill@…>, on 09/27/01 at 13:24:14

2001-09-23 Ralf Corsepius <corsepiu@…>

  • rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
  • Makefile.am: Use 'PREINSTALL_FILES ='.
  • Property mode set to 100644
File size: 7.6 KB
Line 
12001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
2
3        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
4        * Makefile.am: Use 'PREINSTALL_FILES ='.
5
62001-07-03      Joel Sherrill <joel@OARcorp.com>
7
8        * cpu.c: Fixed typo.
9
102000-05-24      Joel Sherrill <joel@OARcorp.com>
11
12        * rtems/score/mips.h: Added constants for MIPS exception numbers.
13        All exceptions should be given low numbers and thus can be installed
14        and processed in a uniform manner.  Variances between various MIPS
15        ISA levels were not accounted for.
16
172001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
18
19        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
20        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
21
222001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
23
24        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
25        the context initialization to account for floating point tasks. 
26        * rtems/score/mips.h: Added the routines mips_set_cause(),
27        mips_get_fcr31(), and mips_set_fcr31().
28        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
29
302001-05-07      Joel Sherrill <joel@OARcorp.com>
31
32        * cpu_asm.S: Merged patches from Gregory Menke
33        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
34        stack usage and include nops in the delay slots.
35
362001-04-20      Joel Sherrill <joel@OARcorp.com>
37
38        * cpu_asm.S: Added code to save and restore SR and EPC to
39        properly support nested interrupts.  Note that the ISR
40        (not RTEMS) enables interrupts allowing the nesting to occur.
41
422001-03-14      Joel Sherrill <joel@OARcorp.com>
43
44        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
45        Removed unused variable _CPU_Thread_dispatch_pointer
46        and cleaned numerous comments.
47       
482001-03-13      Joel Sherrill <joel@OARcorp.com>
49
50        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
51        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
52        Also reimplemented some assembly routines in C further reducing
53        the amount of assembly and increasing maintainability.
54
552001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
56
57        * Makefile.am, rtems/score/Makefile.am:
58        Apply include_*HEADERS instead of H_FILES.
59
602001-01-12      Joel Sherrill <joel@OARcorp.com>
61
62        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
63        register constraints from "general" to "register".
64
652001-01-09      Joel Sherrill <joel@OARcorp.com>
66
67        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
68        to make it easier to conditionalize the code for various ISA levels.
69
702001-01-08      Joel Sherrill <joel@OARcorp.com>
71
72        * idtcpu.h: Commented out definition of "wait".  It was stupid to
73        use such a common word as a macro.
74        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
75        * rtems/score/mips.h: Added include of <idtcpu.h>.
76        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
77
782001-01-03      Joel Sherrill <joel@OARcorp.com>
79
80        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
81        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
82
832000-12-19      Joel Sherrill <joel@OARcorp.com>
84
85        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
86        Previous code resulting in the interrupted immediately returning
87        to the caller of the routine it was inside.
88
892000-12-19      Joel Sherrill <joel@OARcorp.com>
90
91        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
92        because it has not been allocated yet.
93
942000-12-13      Joel Sherrill <joel@OARcorp.com>
95
96        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
97        * cpu_asm.S: Removed assembly language to vector ISR handler
98        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
99        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
100        longer a constant -- get the real value from libcpu.
101
1022000-12-13      Joel Sherrill <joel@OARcorp.com>
103
104        * cpu_asm.h: Removed.
105        * Makefile.am: Remove cpu_asm.h.
106        * rtems/score/mips64orion.h: Renamed mips.h.
107        * rtems/score/mips.h: New file, formerly mips64orion.h.
108        Header rewritten.
109        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
110        mips_disable_in_interrupt_mask): New macros.
111        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
112        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
113        few defines that were in <cpu_asm.h>.
114        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
115        MIPS ISA 3 is still in assembly for now.
116        (_CPU_Thread_Idle_body): Rewrote in C.
117        * cpu_asm.S: Rewrote file header.
118        (FRAME,ENDFRAME) now in asm.h.
119        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
120        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
121        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
122        leaves other bits in SR alone on task switch.
123        (mips_enable_interrupts,mips_disable_interrupts,
124        mips_enable_global_interrupts,mips_disable_global_interrupts,
125        disable_int, enable_int): Removed.
126        (mips_get_sr): Rewritten as C macro.
127        (_CPU_Thread_Idle_body): Rewritten in C.
128        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
129        placed in libcpu.
130        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
131        to libcpu/mips/shared/interrupts.
132        (general): Cleaned up comment blocks and #if 0 areas.
133        * idtcpu.h: Made ifdef report an error.
134        * iregdef.h: Removed warning.
135        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
136        number defined by libcpu.
137        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
138        to access SR.
139        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
140        (_CPU_Context_Initialize): Honor ISR level in task initialization.
141        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
142
1432000-12-06      Joel Sherrill <joel@OARcorp.com>
144
145        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
146        context should be 32 not 64 bits.
147
1482000-11-30      Joel Sherrill <joel@OARcorp.com>
149
150        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
151        correct name of _CPU_Context_switch_restore.  Added dummy
152        version of exc_utlb_code() so applications would link.
153
1542000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
155
156        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
157
1582000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
159
160        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
161
1622000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
163
164        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
165        Switch to GNU canonicalization.
166
1672000-10-24      Alan Cudmore <alanc@linuxstart.com> and
168        Joel Sherrill <joel@OARcorp.com>
169
170        * This is a major reworking of the mips64orion port to use
171        gcc predefines as much as possible and a big push to multilib
172        the mips port.  The mips64orion port was copied/renamed to mips
173        to be more like other GNU tools.  Alan did most of the technical
174        work of determining how to map old macro names used by the mips64orion
175        port to standard compiler macro definitions.  Joel did the merge
176        with CVS magic to keep individual file history and did the BSP
177        modifications. Details follow:
178        * Makefile.am: idtmon.h in mips64orion port not present.
179        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
180        * cpu.c: Comments added.
181        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
182        First attempt at exception/interrupt processing for ISA level 1
183        and minus any use of IDT/MON added.
184        * idtcpu.h: Conditionals changed to use gcc predefines.
185        * iregdef.h: Ditto.
186        * cpu_asm.h: No real change.  Merger required commit.
187        * rtems/Makefile.am: Ditto.
188        * rtems/score/Makefile.am: Ditto.
189        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
190        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
191        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
192
1932000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
194
195        * Makefile.am: Include compile.am.
196
1972000-08-10      Joel Sherrill <joel@OARcorp.com>
198
199        * ChangeLog: New file.
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