1 | 2002-03-20 Greg Menke <gregory.menke@gsfc.nasa.gov> |
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2 | |
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3 | * cpu_asm.S: Now compiles on 4600 and 4650. |
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4 | |
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5 | 2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov> |
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6 | |
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7 | * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug. |
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8 | * rtems/score/cpu.h: Fixed register numbering in comments and made |
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9 | interrupt enable/disable more robust. |
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10 | |
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11 | 2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov> |
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12 | * cpu_asm.S: Added support for the debug exception vector, cleaned |
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13 | up the exception processing & exception return stuff. Re-added |
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14 | EPC in the task context structure so the gdb stub will know where |
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15 | a thread is executing. Should've left it there in the first place... |
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16 | * idtcpu.h: Added support for the debug exception vector. |
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17 | * cpu.c: Added ___exceptionTaskStack to hold a pointer to the |
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18 | stack frame in an interrupt so context switch code can get the |
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19 | userspace EPC when scheduling. |
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20 | * rtems/score/cpu.h: Re-added EPC to the task context. |
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21 | |
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22 | 2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov> |
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23 | |
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24 | * cpu_asm.S: Fixed exception return address, modified FP context |
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25 | switch so FPU is properly enabled and also doesn't screw up the |
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26 | exception FP handling. |
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27 | * idtcpu.h: Added C0_TAR, the MIPS target address register used for |
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28 | returning from exceptions. |
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29 | * iregdef.h: Added R_TAR to the stack frame so the target address |
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30 | can be saved on a per-exception basis. The new entry is past the |
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31 | end of the frame gdb cares about, so doesn't affect gdb or cpu.h |
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32 | stuff. |
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33 | * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it |
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34 | to obtain FPU defines without systax errors generated by the C |
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35 | defintions. |
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36 | * cpu.c: Improved interrupt level saves & restores. |
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37 | |
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38 | 2002-02-08 Joel Sherrill <joel@OARcorp.com> |
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39 | |
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40 | * iregdef.h, rtems/score/cpu.h: Reordered register in the |
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41 | exception stack frame to better match gdb's expectations. |
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42 | |
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43 | 2001-02-05 Joel Sherrill <joel@OARcorp.com> |
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44 | |
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45 | * cpu_asm.S: Enhanced to save/restore more registers on |
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46 | exceptions. |
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47 | * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every |
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48 | register individually and document when it is saved. |
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49 | * idtcpu.h: Added constants for the coprocessor 1 registers |
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50 | revision and status. |
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51 | |
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52 | 2001-02-05 Joel Sherrill <joel@OARcorp.com> |
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53 | |
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54 | * rtems/Makefile.am, rtems/score/Makefile.am: Removed again. |
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55 | |
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56 | 2001-02-04 Joel Sherrill <joel@OARcorp.com> |
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57 | |
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58 | * rtems/score/cpu.h: IDLE task should not be FP. This was a mistake |
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59 | in the previous patch that has now been confirmed. |
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60 | |
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61 | 2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov> |
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62 | |
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63 | * cpu.c: Enhancements and fixes for modifying the SR when changing |
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64 | the interrupt level. |
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65 | * cpu_asm.S: Fixed handling of FP enable bit so it is properly |
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66 | managed on a per-task basis, improved handling of interrupt levels, |
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67 | and made deferred FP contexts work on the MIPS. |
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68 | * rtems/score/cpu.h: Modified to support above changes. |
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69 | |
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70 | 2002-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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71 | |
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72 | * rtems/Makefile.am: Removed. |
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73 | * rtems/score/Makefile.am: Removed. |
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74 | * configure.ac: Reflect changes above. |
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75 | * Makefile.am: Reflect changes above. |
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76 | |
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77 | 2002-02-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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78 | |
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79 | * asm.h: Remove #include <rtems/score/targopts.h>. |
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80 | Add #include <rtems/score/cpuopts.h>. |
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81 | * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP). |
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82 | |
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83 | |
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84 | 2001-12-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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85 | |
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86 | * configure.ac: Use RTEMS_ENV_RTEMSCPU. |
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87 | |
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88 | 2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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89 | |
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90 | * Makefile.am: Add multilib support. |
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91 | |
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92 | 2001-11-28 Joel Sherrill <joel@OARcorp.com>, |
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93 | |
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94 | This was tracked as PR91. |
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95 | * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which |
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96 | is used to specify if the port uses the standard macro for this (FALSE). |
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97 | A TRUE setting indicates the port provides its own implementation. |
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98 | |
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99 | 2001-10-12 Joel Sherrill <joel@OARcorp.com> |
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100 | |
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101 | * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional |
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102 | compilation block with (CPU_HARDWARE_FP == FALSE). Reported by |
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103 | Wayne Bullaughey <wayne@wmi.com>. |
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104 | |
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105 | 2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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106 | |
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107 | * .cvsignore: Add autom4te.cache for autoconf > 2.52. |
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108 | * configure.in: Remove. |
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109 | * configure.ac: New file, generated from configure.in by autoupdate. |
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110 | |
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111 | 2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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112 | |
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113 | * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. |
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114 | * Makefile.am: Use 'PREINSTALL_FILES ='. |
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115 | |
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116 | 2001-07-03 Joel Sherrill <joel@OARcorp.com> |
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117 | |
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118 | * cpu.c: Fixed typo. |
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119 | |
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120 | 2000-05-24 Joel Sherrill <joel@OARcorp.com> |
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121 | |
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122 | * rtems/score/mips.h: Added constants for MIPS exception numbers. |
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123 | All exceptions should be given low numbers and thus can be installed |
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124 | and processed in a uniform manner. Variances between various MIPS |
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125 | ISA levels were not accounted for. |
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126 | |
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127 | 2001-05-24 Greg Menke <gregory.menke@gsfc.nasa.gov> |
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128 | |
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129 | * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>. |
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130 | * cpu_asm.S: Now works on Mongoose-V. Missed in previous patch. |
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131 | |
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132 | 2001-05-22 Greg Menke <gregory.menke@gsfc.nasa.gov> |
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133 | |
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134 | * rtems/score/cpu.h: Add the interrupt stack structure and enhance |
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135 | the context initialization to account for floating point tasks. |
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136 | * rtems/score/mips.h: Added the routines mips_set_cause(), |
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137 | mips_get_fcr31(), and mips_set_fcr31(). |
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138 | * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>. |
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139 | |
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140 | 2001-05-07 Joel Sherrill <joel@OARcorp.com> |
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141 | |
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142 | * cpu_asm.S: Merged patches from Gregory Menke |
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143 | <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up |
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144 | stack usage and include nops in the delay slots. |
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145 | |
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146 | 2001-04-20 Joel Sherrill <joel@OARcorp.com> |
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147 | |
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148 | * cpu_asm.S: Added code to save and restore SR and EPC to |
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149 | properly support nested interrupts. Note that the ISR |
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150 | (not RTEMS) enables interrupts allowing the nesting to occur. |
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151 | |
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152 | 2001-03-14 Joel Sherrill <joel@OARcorp.com> |
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153 | |
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154 | * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: |
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155 | Removed unused variable _CPU_Thread_dispatch_pointer |
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156 | and cleaned numerous comments. |
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157 | |
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158 | 2001-03-13 Joel Sherrill <joel@OARcorp.com> |
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159 | |
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160 | * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h: |
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161 | Merged MIPS1 and MIPS3 code reducing the number of lines of assembly. |
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162 | Also reimplemented some assembly routines in C further reducing |
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163 | the amount of assembly and increasing maintainability. |
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164 | |
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165 | 2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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166 | |
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167 | * Makefile.am, rtems/score/Makefile.am: |
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168 | Apply include_*HEADERS instead of H_FILES. |
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169 | |
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170 | 2001-01-12 Joel Sherrill <joel@OARcorp.com> |
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171 | |
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172 | * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected |
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173 | register constraints from "general" to "register". |
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174 | |
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175 | 2001-01-09 Joel Sherrill <joel@OARcorp.com> |
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176 | |
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177 | * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants |
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178 | to make it easier to conditionalize the code for various ISA levels. |
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179 | |
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180 | 2001-01-08 Joel Sherrill <joel@OARcorp.com> |
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181 | |
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182 | * idtcpu.h: Commented out definition of "wait". It was stupid to |
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183 | use such a common word as a macro. |
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184 | * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3. |
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185 | * rtems/score/mips.h: Added include of <idtcpu.h>. |
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186 | * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected. |
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187 | |
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188 | 2001-01-03 Joel Sherrill <joel@OARcorp.com> |
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189 | |
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190 | * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). |
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191 | * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN. |
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192 | |
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193 | 2000-12-19 Joel Sherrill <joel@OARcorp.com> |
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194 | |
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195 | * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register. |
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196 | Previous code resulting in the interrupted immediately returning |
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197 | to the caller of the routine it was inside. |
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198 | |
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199 | 2000-12-19 Joel Sherrill <joel@OARcorp.com> |
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200 | |
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201 | * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here |
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202 | because it has not been allocated yet. |
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203 | |
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204 | 2000-12-13 Joel Sherrill <joel@OARcorp.com> |
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205 | |
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206 | * cpu.c: Removed duplicate declaration for _ISR_Vector_table. |
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207 | * cpu_asm.S: Removed assembly language to vector ISR handler |
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208 | on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP. |
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209 | * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No |
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210 | longer a constant -- get the real value from libcpu. |
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211 | |
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212 | 2000-12-13 Joel Sherrill <joel@OARcorp.com> |
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213 | |
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214 | * cpu_asm.h: Removed. |
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215 | * Makefile.am: Remove cpu_asm.h. |
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216 | * rtems/score/mips64orion.h: Renamed mips.h. |
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217 | * rtems/score/mips.h: New file, formerly mips64orion.h. |
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218 | Header rewritten. |
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219 | (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, |
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220 | mips_disable_in_interrupt_mask): New macros. |
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221 | * rtems/score/Makefile.am: Reflect renaming mips64orion.h. |
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222 | * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the |
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223 | few defines that were in <cpu_asm.h>. |
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224 | * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. |
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225 | MIPS ISA 3 is still in assembly for now. |
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226 | (_CPU_Thread_Idle_body): Rewrote in C. |
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227 | * cpu_asm.S: Rewrote file header. |
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228 | (FRAME,ENDFRAME) now in asm.h. |
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229 | (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. |
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230 | (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. |
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231 | (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and |
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232 | leaves other bits in SR alone on task switch. |
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233 | (mips_enable_interrupts,mips_disable_interrupts, |
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234 | mips_enable_global_interrupts,mips_disable_global_interrupts, |
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235 | disable_int, enable_int): Removed. |
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236 | (mips_get_sr): Rewritten as C macro. |
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237 | (_CPU_Thread_Idle_body): Rewritten in C. |
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238 | (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and |
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239 | placed in libcpu. |
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240 | (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved |
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241 | to libcpu/mips/shared/interrupts. |
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242 | (general): Cleaned up comment blocks and #if 0 areas. |
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243 | * idtcpu.h: Made ifdef report an error. |
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244 | * iregdef.h: Removed warning. |
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245 | * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable |
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246 | number defined by libcpu. |
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247 | (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines |
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248 | to access SR. |
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249 | (_CPU_ISR_Set_level): Rewritten as macro for ISA I. |
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250 | (_CPU_Context_Initialize): Honor ISR level in task initialization. |
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251 | (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro. |
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252 | |
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253 | 2000-12-06 Joel Sherrill <joel@OARcorp.com> |
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254 | |
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255 | * rtems/score/cpu.h: When mips ISA level is 1, registers in the |
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256 | context should be 32 not 64 bits. |
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257 | |
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258 | 2000-11-30 Joel Sherrill <joel@OARcorp.com> |
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259 | |
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260 | * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to |
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261 | correct name of _CPU_Context_switch_restore. Added dummy |
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262 | version of exc_utlb_code() so applications would link. |
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263 | |
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264 | 2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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265 | |
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266 | * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. |
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267 | |
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268 | 2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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269 | |
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270 | * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. |
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271 | |
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272 | 2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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273 | |
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274 | * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. |
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275 | Switch to GNU canonicalization. |
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276 | |
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277 | 2000-10-24 Alan Cudmore <alanc@linuxstart.com> and |
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278 | Joel Sherrill <joel@OARcorp.com> |
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279 | |
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280 | * This is a major reworking of the mips64orion port to use |
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281 | gcc predefines as much as possible and a big push to multilib |
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282 | the mips port. The mips64orion port was copied/renamed to mips |
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283 | to be more like other GNU tools. Alan did most of the technical |
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284 | work of determining how to map old macro names used by the mips64orion |
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285 | port to standard compiler macro definitions. Joel did the merge |
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286 | with CVS magic to keep individual file history and did the BSP |
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287 | modifications. Details follow: |
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288 | * Makefile.am: idtmon.h in mips64orion port not present. |
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289 | * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added. |
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290 | * cpu.c: Comments added. |
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291 | * cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added. |
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292 | First attempt at exception/interrupt processing for ISA level 1 |
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293 | and minus any use of IDT/MON added. |
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294 | * idtcpu.h: Conditionals changed to use gcc predefines. |
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295 | * iregdef.h: Ditto. |
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296 | * cpu_asm.h: No real change. Merger required commit. |
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297 | * rtems/Makefile.am: Ditto. |
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298 | * rtems/score/Makefile.am: Ditto. |
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299 | * rtems/score/cpu.h: Change MIPS64ORION to MIPS. |
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300 | * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert |
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301 | from using RTEMS_CPU_MODEL to gcc predefines to figre things out. |
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302 | |
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303 | 2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> |
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304 | |
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305 | * Makefile.am: Include compile.am. |
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306 | |
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307 | 2000-08-10 Joel Sherrill <joel@OARcorp.com> |
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308 | |
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309 | * ChangeLog: New file. |
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