source: rtems/c/src/exec/score/cpu/mips/ChangeLog @ 25d3d4d

4.104.114.84.95
Last change on this file since 25d3d4d was 25d3d4d, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 20, 2002 at 6:16:07 PM

2002-03-20 Greg Menke <gregory.menke@…>

  • cpu_asm.S: Now compiles on 4600 and 4650.
  • Property mode set to 100644
File size: 11.6 KB
Line 
12002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
2
3        * cpu_asm.S: Now compiles on 4600 and 4650.
4
52002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
6
7        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
8        * rtems/score/cpu.h: Fixed register numbering in comments and made
9        interrupt enable/disable more robust.
10       
112002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
12        * cpu_asm.S: Added support for the debug exception vector, cleaned
13        up the exception processing & exception return stuff.  Re-added
14        EPC in the task context structure so the gdb stub will know where
15        a thread is executing.  Should've left it there in the first place...
16        * idtcpu.h: Added support for the debug exception vector.
17        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
18        stack frame in an interrupt so context switch code can get the
19        userspace EPC when scheduling.
20        * rtems/score/cpu.h: Re-added EPC to the task context.
21
222002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
23
24        * cpu_asm.S: Fixed exception return address, modified FP context
25        switch so FPU is properly enabled and also doesn't screw up the
26        exception FP handling.
27        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
28        returning from exceptions.
29        * iregdef.h: Added R_TAR to the stack frame so the target address
30        can be saved on a per-exception basis.  The new entry is past the
31        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
32        stuff.
33        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
34        to obtain FPU defines without systax errors generated by the C
35        defintions.
36        * cpu.c: Improved interrupt level saves & restores.
37       
382002-02-08      Joel Sherrill <joel@OARcorp.com>
39
40        * iregdef.h, rtems/score/cpu.h: Reordered register in the
41        exception stack frame to better match gdb's expectations.
42
432001-02-05      Joel Sherrill <joel@OARcorp.com>
44
45        * cpu_asm.S: Enhanced to save/restore more registers on
46        exceptions.
47        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
48        register individually and document when it is saved.
49        * idtcpu.h: Added constants for the coprocessor 1 registers
50        revision and status.
51
522001-02-05      Joel Sherrill <joel@OARcorp.com>
53
54        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
55
562001-02-04      Joel Sherrill <joel@OARcorp.com>
57
58        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
59        in the previous patch that has now been confirmed.
60
612001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
62
63        * cpu.c: Enhancements and fixes for modifying the SR when changing
64        the interrupt level.
65        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
66        managed on a per-task basis, improved handling of interrupt levels,
67        and made deferred FP contexts work on the MIPS.
68        * rtems/score/cpu.h: Modified to support above changes.
69
702002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
71
72        * rtems/Makefile.am: Removed.
73        * rtems/score/Makefile.am: Removed.
74        * configure.ac: Reflect changes above.
75        * Makefile.am: Reflect changes above.
76
772002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
78
79        * asm.h: Remove #include <rtems/score/targopts.h>.
80        Add #include <rtems/score/cpuopts.h>.
81        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
82
83
842001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
85
86        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
87
882001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
89
90        * Makefile.am: Add multilib support.
91
922001-11-28      Joel Sherrill <joel@OARcorp.com>,
93
94        This was tracked as PR91.
95        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
96        is used to specify if the port uses the standard macro for this (FALSE).
97        A TRUE setting indicates the port provides its own implementation.
98
992001-10-12      Joel Sherrill <joel@OARcorp.com>
100
101        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
102        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
103        Wayne Bullaughey <wayne@wmi.com>.
104
1052001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
106
107        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
108        * configure.in: Remove.
109        * configure.ac: New file, generated from configure.in by autoupdate.
110
1112001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
112
113        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
114        * Makefile.am: Use 'PREINSTALL_FILES ='.
115
1162001-07-03      Joel Sherrill <joel@OARcorp.com>
117
118        * cpu.c: Fixed typo.
119
1202000-05-24      Joel Sherrill <joel@OARcorp.com>
121
122        * rtems/score/mips.h: Added constants for MIPS exception numbers.
123        All exceptions should be given low numbers and thus can be installed
124        and processed in a uniform manner.  Variances between various MIPS
125        ISA levels were not accounted for.
126
1272001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
128
129        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
130        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
131
1322001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
133
134        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
135        the context initialization to account for floating point tasks. 
136        * rtems/score/mips.h: Added the routines mips_set_cause(),
137        mips_get_fcr31(), and mips_set_fcr31().
138        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
139
1402001-05-07      Joel Sherrill <joel@OARcorp.com>
141
142        * cpu_asm.S: Merged patches from Gregory Menke
143        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
144        stack usage and include nops in the delay slots.
145
1462001-04-20      Joel Sherrill <joel@OARcorp.com>
147
148        * cpu_asm.S: Added code to save and restore SR and EPC to
149        properly support nested interrupts.  Note that the ISR
150        (not RTEMS) enables interrupts allowing the nesting to occur.
151
1522001-03-14      Joel Sherrill <joel@OARcorp.com>
153
154        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
155        Removed unused variable _CPU_Thread_dispatch_pointer
156        and cleaned numerous comments.
157       
1582001-03-13      Joel Sherrill <joel@OARcorp.com>
159
160        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
161        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
162        Also reimplemented some assembly routines in C further reducing
163        the amount of assembly and increasing maintainability.
164
1652001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
166
167        * Makefile.am, rtems/score/Makefile.am:
168        Apply include_*HEADERS instead of H_FILES.
169
1702001-01-12      Joel Sherrill <joel@OARcorp.com>
171
172        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
173        register constraints from "general" to "register".
174
1752001-01-09      Joel Sherrill <joel@OARcorp.com>
176
177        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
178        to make it easier to conditionalize the code for various ISA levels.
179
1802001-01-08      Joel Sherrill <joel@OARcorp.com>
181
182        * idtcpu.h: Commented out definition of "wait".  It was stupid to
183        use such a common word as a macro.
184        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
185        * rtems/score/mips.h: Added include of <idtcpu.h>.
186        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
187
1882001-01-03      Joel Sherrill <joel@OARcorp.com>
189
190        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
191        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
192
1932000-12-19      Joel Sherrill <joel@OARcorp.com>
194
195        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
196        Previous code resulting in the interrupted immediately returning
197        to the caller of the routine it was inside.
198
1992000-12-19      Joel Sherrill <joel@OARcorp.com>
200
201        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
202        because it has not been allocated yet.
203
2042000-12-13      Joel Sherrill <joel@OARcorp.com>
205
206        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
207        * cpu_asm.S: Removed assembly language to vector ISR handler
208        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
209        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
210        longer a constant -- get the real value from libcpu.
211
2122000-12-13      Joel Sherrill <joel@OARcorp.com>
213
214        * cpu_asm.h: Removed.
215        * Makefile.am: Remove cpu_asm.h.
216        * rtems/score/mips64orion.h: Renamed mips.h.
217        * rtems/score/mips.h: New file, formerly mips64orion.h.
218        Header rewritten.
219        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
220        mips_disable_in_interrupt_mask): New macros.
221        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
222        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
223        few defines that were in <cpu_asm.h>.
224        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
225        MIPS ISA 3 is still in assembly for now.
226        (_CPU_Thread_Idle_body): Rewrote in C.
227        * cpu_asm.S: Rewrote file header.
228        (FRAME,ENDFRAME) now in asm.h.
229        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
230        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
231        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
232        leaves other bits in SR alone on task switch.
233        (mips_enable_interrupts,mips_disable_interrupts,
234        mips_enable_global_interrupts,mips_disable_global_interrupts,
235        disable_int, enable_int): Removed.
236        (mips_get_sr): Rewritten as C macro.
237        (_CPU_Thread_Idle_body): Rewritten in C.
238        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
239        placed in libcpu.
240        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
241        to libcpu/mips/shared/interrupts.
242        (general): Cleaned up comment blocks and #if 0 areas.
243        * idtcpu.h: Made ifdef report an error.
244        * iregdef.h: Removed warning.
245        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
246        number defined by libcpu.
247        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
248        to access SR.
249        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
250        (_CPU_Context_Initialize): Honor ISR level in task initialization.
251        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
252
2532000-12-06      Joel Sherrill <joel@OARcorp.com>
254
255        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
256        context should be 32 not 64 bits.
257
2582000-11-30      Joel Sherrill <joel@OARcorp.com>
259
260        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
261        correct name of _CPU_Context_switch_restore.  Added dummy
262        version of exc_utlb_code() so applications would link.
263
2642000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
265
266        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
267
2682000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
269
270        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
271
2722000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
273
274        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
275        Switch to GNU canonicalization.
276
2772000-10-24      Alan Cudmore <alanc@linuxstart.com> and
278        Joel Sherrill <joel@OARcorp.com>
279
280        * This is a major reworking of the mips64orion port to use
281        gcc predefines as much as possible and a big push to multilib
282        the mips port.  The mips64orion port was copied/renamed to mips
283        to be more like other GNU tools.  Alan did most of the technical
284        work of determining how to map old macro names used by the mips64orion
285        port to standard compiler macro definitions.  Joel did the merge
286        with CVS magic to keep individual file history and did the BSP
287        modifications. Details follow:
288        * Makefile.am: idtmon.h in mips64orion port not present.
289        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
290        * cpu.c: Comments added.
291        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
292        First attempt at exception/interrupt processing for ISA level 1
293        and minus any use of IDT/MON added.
294        * idtcpu.h: Conditionals changed to use gcc predefines.
295        * iregdef.h: Ditto.
296        * cpu_asm.h: No real change.  Merger required commit.
297        * rtems/Makefile.am: Ditto.
298        * rtems/score/Makefile.am: Ditto.
299        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
300        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
301        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
302
3032000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
304
305        * Makefile.am: Include compile.am.
306
3072000-08-10      Joel Sherrill <joel@OARcorp.com>
308
309        * ChangeLog: New file.
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