source: rtems/c/src/exec/score/cpu/m68k/rtems/score/m68k.h @ 08311cc3

4.104.114.84.95
Last change on this file since 08311cc3 was 08311cc3, checked in by Joel Sherrill <joel.sherrill@…>, on 11/17/99 at 17:51:34

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1/*  m68k.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __M68k_h
17#define __M68k_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/*
24 *  This section contains the information required to build
25 *  RTEMS for a particular member of the Motorola MC68xxx
26 *  family.  It does this by setting variables to indicate
27 *  which implementation dependent features are present in
28 *  a particular member of the family.
29 *
30 *  Currently recognized:
31 *     -m68000
32 *     -m68000 -msoft-float
33 *     -m68020
34 *     -m68020 -msoft-float
35 *     -m68030
36 *     -m68040 -msoft-float
37 *     -m68040
38 *     -m68040 -msoft-float
39 *     -m68060
40 *     -m68060 -msoft-float
41 *     -m68302        (no FP) (deprecated, use -m68000)
42 *     -m68332        (no FP) (deprecated, use -mcpu32)
43 *     -mcpu32        (no FP)
44 *     -m5200         (no FP)
45 *
46 *  As of gcc 2.8.1 and egcs 1.1, there is no distinction made between
47 *  the CPU32 and CPU32+.  The option -mcpu32 generates code which can
48 *  be run on either core.  RTEMS distinguishes between these two cores
49 *  because they have different alignment rules which impact performance.
50 *  If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should
51 *  be defined in your custom file (see make/custom/gen68360.cfg for an
52 *  example of how to do this.  If gcc ever distinguishes between these
53 *  two cores, then RTEMS__mcpu32p__ usage will be replaced with the
54 *  appropriate compiler defined predefine.
55 *
56 *  Here is some information on the 040 variants (courtesy of Doug McBride,
57 *  mcbride@rodin.colorado.edu):
58 *
59 *    "The 68040 is a superset of the 68EC040 and the 68LC040.  The
60 *    68EC040 and 68LC040 do not have FPU's.  The 68LC040 and the
61 *    68EC040 have renamed the DLE pin as JS0 which must be tied to
62 *    Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1.  The
63 *    68EC040 has access control units instead of memory management units.
64 *    The 68EC040 should not have the PFLUSH or PTEST instructions executed
65 *    (cause an indeterminate result).  The 68EC040 and 68LC040 do not
66 *    implement the DLE or multiplexed bus modes.  The 68EC040 does not
67 *    implement the output buffer impedance selection mode of operation."
68 *
69 *  M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
70 *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
71 *  68010, 68302, 68306, 68307).  This instruction is available on the 68020
72 *  up and the cpu32 based models. 
73 *
74 *  M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
75 *  data access (68020, 68030, 68040, 68060, CPU32+).
76 *
77 *  NOTE:
78 *    Eventually it would be nice to evaluate doing a lot of this section
79 *    by having each model specify which core it uses and then go from there.
80 */
81
82#if defined(__mc68020__)
83 
84#define CPU_MODEL_NAME          "m68020"
85#define M68K_HAS_VBR             1
86#define M68K_HAS_SEPARATE_STACKS 1
87#define M68K_HAS_BFFFO           1
88#define M68K_HAS_PREINDEXING     1
89#define M68K_HAS_EXTB_L          1
90#define M68K_HAS_MISALIGNED      1
91# if defined (__HAVE_68881__)
92# define M68K_HAS_FPU            1
93# define M68K_HAS_FPSP_PACKAGE   0
94# else
95# define M68K_HAS_FPU            0
96# define M68K_HAS_FPSP_PACKAGE   0
97# endif
98 
99#elif defined(__mc68030__)
100 
101#define CPU_MODEL_NAME          "m68030"
102#define M68K_HAS_VBR             1
103#define M68K_HAS_SEPARATE_STACKS 1
104#define M68K_HAS_BFFFO           1
105#define M68K_HAS_PREINDEXING     1
106#define M68K_HAS_EXTB_L          1
107#define M68K_HAS_MISALIGNED      1
108# if defined (__HAVE_68881__)
109# define M68K_HAS_FPU            1
110# define M68K_HAS_FPSP_PACKAGE   0
111# else
112# define M68K_HAS_FPU            0
113# define M68K_HAS_FPSP_PACKAGE   0
114# endif
115 
116#elif defined(__mc68040__)
117
118#define CPU_MODEL_NAME          "m68040"
119#define M68K_HAS_VBR             1
120#define M68K_HAS_SEPARATE_STACKS 1
121#define M68K_HAS_BFFFO           1
122#define M68K_HAS_PREINDEXING     1
123#define M68K_HAS_EXTB_L          1
124#define M68K_HAS_MISALIGNED      1
125# if defined (__HAVE_68881__)
126# define M68K_HAS_FPU            1
127# define M68K_HAS_FPSP_PACKAGE   1
128# else
129# define M68K_HAS_FPU            0
130# define M68K_HAS_FPSP_PACKAGE   0
131# endif
132 
133#elif defined(__mc68060__)
134
135#define CPU_MODEL_NAME          "m68060"
136#define M68K_HAS_VBR             1
137#define M68K_HAS_SEPARATE_STACKS 0
138#define M68K_HAS_BFFFO           1
139#define M68K_HAS_PREINDEXING     1
140#define M68K_HAS_EXTB_L          1
141#define M68K_HAS_MISALIGNED      1
142# if defined (__HAVE_68881__)
143# define M68K_HAS_FPU            1
144# define M68K_HAS_FPSP_PACKAGE   1
145# else
146# define M68K_HAS_FPU            0
147# define M68K_HAS_FPSP_PACKAGE   0
148# endif
149 
150#elif defined(__mc68302__)
151#define CPU_MODEL_NAME          "m68302"
152#define M68K_HAS_VBR             0
153#define M68K_HAS_SEPARATE_STACKS 0
154#define M68K_HAS_BFFFO           0
155#define M68K_HAS_PREINDEXING     0
156#define M68K_HAS_EXTB_L          0
157#define M68K_HAS_MISALIGNED      0
158#define M68K_HAS_FPU             0
159#define M68K_HAS_FPSP_PACKAGE    0
160
161  /* gcc and egcs do not distinguish between CPU32 and CPU32+ */
162#elif defined(RTEMS__mcpu32p__)
163 
164#define CPU_MODEL_NAME          "mcpu32+"
165#define M68K_HAS_VBR             1
166#define M68K_HAS_SEPARATE_STACKS 0
167#define M68K_HAS_BFFFO           0
168#define M68K_HAS_PREINDEXING     1
169#define M68K_HAS_EXTB_L          1
170#define M68K_HAS_MISALIGNED      1
171#define M68K_HAS_FPU             0
172#define M68K_HAS_FPSP_PACKAGE    0
173
174#elif defined(__mcpu32__)
175 
176#define CPU_MODEL_NAME          "mcpu32"
177#define M68K_HAS_VBR             1
178#define M68K_HAS_SEPARATE_STACKS 0
179#define M68K_HAS_BFFFO           0
180#define M68K_HAS_PREINDEXING     1
181#define M68K_HAS_EXTB_L          1
182#define M68K_HAS_MISALIGNED      0
183#define M68K_HAS_FPU             0
184#define M68K_HAS_FPSP_PACKAGE    0
185
186#elif defined(__mcf5200__)
187/* Motorola ColdFire V2 core - RISC/68020 hybrid */
188#define CPU_MODEL_NAME         "m5200"
189#define M68K_HAS_VBR             1
190#define M68K_HAS_BFFFO           0
191#define M68K_HAS_SEPARATE_STACKS 0
192#define M68K_HAS_PREINDEXING     0
193#define M68K_HAS_EXTB_L          1
194#define M68K_HAS_MISALIGNED      1
195#define M68K_HAS_FPU             0
196#define M68K_HAS_FPSP_PACKAGE    0
197#define M68K_COLDFIRE_ARCH       1
198
199#elif defined(__mc68000__)
200 
201#define CPU_MODEL_NAME          "m68000"
202#define M68K_HAS_VBR             0
203#define M68K_HAS_SEPARATE_STACKS 0
204#define M68K_HAS_BFFFO           0
205#define M68K_HAS_PREINDEXING     0
206#define M68K_HAS_EXTB_L          0
207#define M68K_HAS_MISALIGNED      0
208# if defined (__HAVE_68881__)
209# define M68K_HAS_FPU            1
210# define M68K_HAS_FPSP_PACKAGE   0
211# else
212# define M68K_HAS_FPU            0
213# define M68K_HAS_FPSP_PACKAGE   0
214# endif
215
216#else
217
218#error "Unsupported CPU model -- are you sure you're running a 68k compiler?"
219
220#endif
221
222/*
223 *  If the above did not specify a ColdFire architecture, then set
224 *  this flag to indicate that it is not a ColdFire CPU.
225 */
226
227#if !defined(M68K_COLDFIRE_ARCH)
228#define M68K_COLDFIRE_ARCH       0
229#endif
230
231/*
232 *  Define the name of the CPU family.
233 */
234
235#if ( M68K_COLDFIRE_ARCH == 1 )
236  #define CPU_NAME "Motorola ColdFire"
237#else
238  #define CPU_NAME "Motorola MC68xxx"
239#endif
240
241#ifndef ASM
242
243#if ( M68K_COLDFIRE_ARCH == 1 )
244#define m68k_disable_interrupts( _level ) \
245   do { register unsigned32 _tmpsr = 0x0700; \
246        asm volatile ( "move.w %%sr,%0\n\t" \
247                       "or.l   %0,%1\n\t" \
248                       "move.w %1,%%sr" \
249                       : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) ); \
250   } while( 0 )
251#else
252#define m68k_disable_interrupts( _level ) \
253  asm volatile ( "move.w  %%sr,%0\n\t" \
254                 "or.w    #0x0700,%%sr" \
255                    : "=d" (_level))
256#endif
257
258#define m68k_enable_interrupts( _level ) \
259  asm volatile ( "move.w  %0,%%sr " : : "d" (_level));
260
261#if ( M68K_COLDFIRE_ARCH == 1 )
262#define m68k_flash_interrupts( _level ) \
263   do { register unsigned32 _tmpsr = 0x0700; \
264        asm volatile ( "move.w %2,%%sr\n\t" \
265                       "or.l   %2,%1\n\t" \
266                       "move.w %1,%%sr" \
267                       : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) ); \
268   } while( 0 )
269#else
270#define m68k_flash_interrupts( _level ) \
271  asm volatile ( "move.w  %0,%%sr\n\t" \
272                 "or.w    #0x0700,%%sr" \
273                    : : "d" (_level))
274#endif
275
276#define m68k_get_interrupt_level( _level ) \
277  do { \
278    register unsigned32 _tmpsr; \
279    \
280    asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
281    _level = (_tmpsr & 0x0700) >> 8; \
282  } while (0)
283   
284#define m68k_set_interrupt_level( _newlevel ) \
285  do { \
286    register unsigned32 _tmpsr; \
287    \
288    asm volatile( "move.w  %%sr,%0" : "=d" (_tmpsr)); \
289    _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
290    asm volatile( "move.w  %0,%%sr" : : "d" (_tmpsr)); \
291  } while (0)
292
293#if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 )
294#define m68k_get_vbr( vbr ) \
295  asm volatile ( "movec   %%vbr,%0 " : "=r" (vbr))
296
297#define m68k_set_vbr( vbr ) \
298  asm volatile ( "movec   %0,%%vbr " : : "r" (vbr))
299
300#elif ( M68K_COLDFIRE_ARCH == 1 )
301#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
302
303#define m68k_set_vbr( _vbr ) \
304    asm volatile ("move.l  %%a7,%%d1 \n\t" \
305                  "move.l  %0,%%a7\n\t"    \
306                  "movec   %%a7,%%vbr\n\t" \
307                  "move.l  %%d1,%%a7\n\t"  \
308                  : : "d" (_vbr) : "d1" );
309 
310#else
311#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
312#define m68k_set_vbr( _vbr )
313#endif
314
315/*
316 *  The following routine swaps the endian format of an unsigned int.
317 *  It must be static because it is referenced indirectly.
318 */
319
320static inline unsigned int m68k_swap_u32(
321  unsigned int value
322)
323{
324  unsigned int swapped = value;
325
326  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
327  asm volatile( "swap  %0"    : "=d" (swapped) : "0" (swapped) );
328  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
329
330  return( swapped );
331}
332
333static inline unsigned int m68k_swap_u16(
334  unsigned int value
335)
336{
337  unsigned short swapped = value;
338
339  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
340
341  return( swapped );
342}
343
344/* XXX this is only valid for some m68k family members and should be fixed */
345
346#define m68k_enable_caching() \
347  { register unsigned32 _ctl=0x01; \
348    asm volatile ( "movec   %0,%%cacr" \
349                       : "=d" (_ctl) : "0" (_ctl) ); \
350  }
351
352#define CPU_swap_u32( value )  m68k_swap_u32( value )
353#define CPU_swap_u16( value )  m68k_swap_u16( value )
354
355#endif  /* !ASM */
356
357#ifdef __cplusplus
358}
359#endif
360
361#endif
362/* end of include file */
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