source: rtems/c/src/exec/score/cpu/m68k/rtems/score/cpu.h @ e090b7e

4.104.114.84.95
Last change on this file since e090b7e was e090b7e, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 19, 2000 at 3:32:20 PM

2000-10-19 Antti P Miettinen <anmietti@…>

  • rtems/score/cpu.h: define CPU_Exception_frame for rdbg.
  • m68302.h: Make buffer pointer in m302_SCC_bd volatile.
  • Property mode set to 100644
File size: 17.4 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __CPU_h
17#define __CPU_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include <rtems/score/m68k.h>              /* pick up machine definitions */
24#ifndef ASM
25#include <rtems/score/m68ktypes.h>
26#endif
27
28/* conditional compilation parameters */
29
30#define CPU_INLINE_ENABLE_DISPATCH       TRUE
31#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
32
33/*
34 *  Use the m68k's hardware interrupt stack support and have the
35 *  interrupt manager allocate the memory for it.
36 */
37
38#if ( M68K_HAS_SEPARATE_STACKS == 1)
39#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
40#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
41#else
42#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
43#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
44#endif
45#define CPU_ALLOCATE_INTERRUPT_STACK     1
46
47/*
48 *  Does the RTEMS invoke the user's ISR with the vector number and
49 *  a pointer to the saved interrupt frame (1) or just the vector
50 *  number (0)?
51 */
52
53#define CPU_ISR_PASSES_FRAME_POINTER 0
54
55/*
56 *  Some family members have no FP, some have an FPU such as the
57 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
58 *
59 *  NOTE:  If on a CPU without hardware FP, then one can use software
60 *         emulation.  The gcc software FP emulation code has data which
61 *         must be contexted switched on a per task basis.
62 */
63
64#if ( M68K_HAS_FPU == 1 )
65#define CPU_HARDWARE_FP     TRUE
66#define CPU_SOFTWARE_FP     FALSE
67#else
68#define CPU_HARDWARE_FP     FALSE
69#if defined(__GNUC__)
70#define CPU_SOFTWARE_FP     TRUE
71#else
72#define CPU_SOFTWARE_FP     FALSE
73#endif
74#endif
75
76/*
77 *  All tasks are not by default floating point tasks on this CPU.
78 *  The IDLE task does not have a floating point context on this CPU.
79 *  It is safe to use the deferred floating point context switch
80 *  algorithm on this CPU.
81 */
82
83#define CPU_ALL_TASKS_ARE_FP             FALSE
84#define CPU_IDLE_TASK_IS_FP              FALSE
85#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
86
87#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
88#define CPU_STACK_GROWS_UP               FALSE
89#define CPU_STRUCTURE_ALIGNMENT
90
91/*
92 *  Define what is required to specify how the network to host conversion
93 *  routines are handled.
94 */
95
96#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
97#define CPU_BIG_ENDIAN                           TRUE
98#define CPU_LITTLE_ENDIAN                        FALSE
99
100#ifndef ASM
101/* structures */
102
103/*
104 *  Basic integer context for the m68k family.
105 */
106
107typedef struct {
108  unsigned32  sr;                /* (sr) status register */
109  unsigned32  d2;                /* (d2) data register 2 */
110  unsigned32  d3;                /* (d3) data register 3 */
111  unsigned32  d4;                /* (d4) data register 4 */
112  unsigned32  d5;                /* (d5) data register 5 */
113  unsigned32  d6;                /* (d6) data register 6 */
114  unsigned32  d7;                /* (d7) data register 7 */
115  void       *a2;                /* (a2) address register 2 */
116  void       *a3;                /* (a3) address register 3 */
117  void       *a4;                /* (a4) address register 4 */
118  void       *a5;                /* (a5) address register 5 */
119  void       *a6;                /* (a6) address register 6 */
120  void       *a7_msp;            /* (a7) master stack pointer */
121}   Context_Control;
122
123/*
124 *  Floating point context ares
125 */
126
127#if (CPU_SOFTWARE_FP == TRUE)
128
129/*
130 *  This is the same as gcc's view of the software FP condition code
131 *  register _fpCCR.  The implementation of the emulation code is
132 *  in the gcc-VERSION/config/m68k directory.  This structure is
133 *  correct as of gcc 2.7.2.2.
134 */
135
136typedef struct {
137  unsigned16   _exception_bits;
138  unsigned16   _trap_enable_bits;
139  unsigned16   _sticky_bits;
140  unsigned16   _rounding_mode;
141  unsigned16   _format;
142  unsigned16   _last_operation;
143  union {
144    float sf;
145    double df;
146  } _operand1;
147  union {
148    float sf;
149    double df;
150  } _operand2;
151} Context_Control_fp;
152
153#else
154
155/*
156 *  FP context save area for the M68881/M68882 numeric coprocessors.
157 */
158
159typedef struct {
160  unsigned8   fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
161                                    /*    96 bytes for FMOVEM FP0-7      */
162                                    /*    12 bytes for FMOVEM CREGS      */
163                                    /*     4 bytes for non-null flag     */
164} Context_Control_fp;
165#endif
166
167/*
168 *  The following structures define the set of information saved
169 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
170 *  These are not used by m68k handlers.
171 *  The exception frame is for rdbg.
172 */
173
174typedef struct {
175  unsigned32 vecnum; /* vector number */
176} CPU_Interrupt_frame;
177
178typedef struct {
179  unsigned32 vecnum; /* vector number */
180  unsigned32 sr; /* status register */
181  unsigned32 pc; /* program counter */
182  unsigned32 d0, d1, d2, d3, d4, d5, d6, d7;
183  unsigned32 a0, a1, a2, a3, a4, a5, a6, a7;
184} CPU_Exception_frame;
185
186/*
187 *  The following table contains the information required to configure
188 *  the m68k specific parameters.
189 */
190
191typedef struct {
192  void       (*pretasking_hook)( void );
193  void       (*predriver_hook)( void );
194  void       (*postdriver_hook)( void );
195  void       (*idle_task)( void );
196  boolean      do_zero_of_workspace;
197  unsigned32   idle_task_stack_size;
198  unsigned32   interrupt_stack_size;
199  unsigned32   extra_mpci_receive_server_stack;
200  void *     (*stack_allocate_hook)( unsigned32 );
201  void       (*stack_free_hook)( void* );
202  /* end of fields required on all CPUs */
203
204  m68k_isr    *interrupt_vector_table;
205}   rtems_cpu_table;
206
207/*
208 *  Macros to access required entires in the CPU Table are in
209 *  the file rtems/system.h.
210 */
211
212/*
213 *  Macros to access M68K specific additions to the CPU Table
214 */
215
216#define rtems_cpu_configuration_get_interrupt_vector_table() \
217   (_CPU_Table.interrupt_vector_table)
218
219/* variables */
220
221SCORE_EXTERN void                   *_CPU_Interrupt_stack_low;
222SCORE_EXTERN void                   *_CPU_Interrupt_stack_high;
223
224extern char                         _VBR[]; 
225
226#if ( M68K_HAS_VBR == 0 )
227
228/*
229 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
230 * pushed onto the stack. This is not is the same order as VBR processors.
231 * The ISR handler takes the format and uses it for dispatching the user
232 * handler.
233 *
234 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
235 *
236 */
237
238typedef struct {
239  unsigned16 move_a7;            /* move #FORMAT_ID,%a7@- */
240  unsigned16 format_id;
241  unsigned16 jmp;                /* jmp  _ISR_Handlers */
242  unsigned32 isr_handler;
243} _CPU_ISR_handler_entry;
244
245#define M68K_MOVE_A7 0x3F3C
246#define M68K_JMP     0x4EF9
247
248      /* points to jsr-exception-table in targets wo/ VBR register */
249SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; 
250
251#endif /* M68K_HAS_VBR */
252#endif /* ASM */
253
254/* constants */
255
256/*
257 *  This defines the number of levels and the mask used to pick those
258 *  bits out of a thread mode.
259 */
260
261#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
262#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
263
264/*
265 *  context size area for floating point
266 */
267
268#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
269
270/*
271 *  extra stack required by the MPCI receive server thread
272 */
273
274#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
275
276/*
277 *  m68k family supports 256 distinct vectors.
278 */
279
280#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
281#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
282
283/*
284 *  Minimum size of a thread's stack.
285 */
286
287#define CPU_STACK_MINIMUM_SIZE           4096
288
289/*
290 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
291 */
292
293#define CPU_ALIGNMENT                    4
294#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
295#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
296
297/*
298 *  On m68k thread stacks require no further alignment after allocation
299 *  from the Workspace.
300 */
301
302#define CPU_STACK_ALIGNMENT        0
303
304#ifndef ASM
305
306/* macros */
307
308/*
309 *  ISR handler macros
310 *
311 *  These macros perform the following functions:
312 *     + disable all maskable CPU interrupts
313 *     + restore previous interrupt level (enable)
314 *     + temporarily restore interrupts (flash)
315 *     + set a particular level
316 */
317
318#define _CPU_ISR_Disable( _level ) \
319  m68k_disable_interrupts( _level )
320
321#define _CPU_ISR_Enable( _level ) \
322  m68k_enable_interrupts( _level )
323
324#define _CPU_ISR_Flash( _level ) \
325  m68k_flash_interrupts( _level )
326
327#define _CPU_ISR_Set_level( _newlevel ) \
328   m68k_set_interrupt_level( _newlevel )
329
330unsigned32 _CPU_ISR_Get_level( void );
331
332/* end of ISR handler macros */
333
334/*
335 *  Context handler macros
336 *
337 *  These macros perform the following functions:
338 *     + initialize a context area
339 *     + restart the current thread
340 *     + calculate the initial pointer into a FP context area
341 *     + initialize an FP context area
342 */
343
344#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
345                                 _isr, _entry_point, _is_fp ) \
346   do { \
347     unsigned32 _stack; \
348     \
349     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
350     _stack                  = (unsigned32)(_stack_base) + (_size) - 4; \
351     (_the_context)->a7_msp  = (void *)_stack; \
352     *(void **)_stack        = (void *)(_entry_point); \
353   } while ( 0 )
354
355#define _CPU_Context_Restart_self( _the_context ) \
356  { asm volatile( "movew %0,%%sr ; " \
357                  "moval %1,%%a7 ; " \
358                  "rts"  \
359        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
360        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
361  }
362
363/*
364 *  Floating Point Context Area Support routines
365 */
366
367#if (CPU_SOFTWARE_FP == TRUE)
368
369/*
370 *  This software FP implementation is only for GCC.
371 */
372
373#define _CPU_Context_Fp_start( _base, _offset ) \
374   ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
375
376
377#define _CPU_Context_Initialize_fp( _fp_area ) \
378   { \
379   Context_Control_fp *_fp; \
380   _fp = *(Context_Control_fp **)_fp_area; \
381   _fp->_exception_bits = 0; \
382   _fp->_trap_enable_bits = 0; \
383   _fp->_sticky_bits = 0; \
384   _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
385   _fp->_format = 0;         /* NIL */ \
386   _fp->_last_operation = 0;  /* NOOP */ \
387   _fp->_operand1.df = 0; \
388   _fp->_operand2.df = 0; \
389   }
390#else
391#define _CPU_Context_Fp_start( _base, _offset ) \
392   ((void *) \
393     _Addresses_Add_offset( \
394        (_base), \
395        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
396     ) \
397   )
398
399#define _CPU_Context_Initialize_fp( _fp_area ) \
400   { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
401     \
402     *(--(_fp_context)) = 0; \
403     *(_fp_area) = (unsigned8 *)(_fp_context); \
404   }
405#endif
406
407/* end of Context handler macros */
408
409/*
410 *  Fatal Error manager macros
411 *
412 *  These macros perform the following functions:
413 *    + disable interrupts and halt the CPU
414 */
415
416#if ( M68K_COLDFIRE_ARCH == 1 )
417#define _CPU_Fatal_halt( _error ) \
418  { asm volatile( "move.w %%sr,%%d0\n\t" \
419                  "or.l %2,%%d0\n\t" \
420                  "move.w %%d0,%%sr\n\t" \
421                  "move.l %1,%%d0\n\t" \
422                  "move.l #0xDEADBEEF,%%d1\n\t" \
423                  "halt" \
424                  : "=g" (_error) \
425                  : "0" (_error), "d"(0x0700) \
426                  : "d0", "d1" ); \
427  }
428#else
429#define _CPU_Fatal_halt( _error ) \
430  { asm volatile( "movl  %0,%%d0; " \
431                  "orw   #0x0700,%%sr; " \
432                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
433  }
434#endif
435
436/* end of Fatal Error manager macros */
437
438/*
439 *  Bitfield handler macros
440 *
441 *  These macros perform the following functions:
442 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
443 *
444 *  NOTE:
445 *
446 *    It appears that on the M68020 bitfield are always 32 bits wide
447 *    when in a register.  This code forces the bitfield to be in
448 *    memory (it really always is anyway). This allows us to
449 *    have a real 16 bit wide bitfield which operates "correctly."
450 */
451
452#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
453#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
454
455#if ( M68K_HAS_BFFFO == 1 )
456
457#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
458  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
459#else
460
461/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
462   _CPU_Priority_bits_index is not needed), handles the 0 case, and
463   does not molest _value -- jsg */
464#if ( M68K_COLDFIRE_ARCH == 1 )
465#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
466  { \
467    extern const unsigned char __BFFFOtable[256]; \
468    register int dumby; \
469    \
470    asm volatile ( \
471       "   clr.l   %1\n"         \
472       "   move.w  %2,%1\n"      \
473       "   lsr.l   #8,%1\n"      \
474       "   beq.s   1f\n"         \
475       "   move.b  (%3,%1),%0\n" \
476       "   bra.s   0f\n"         \
477       "1: move.w  %2,%1\n"      \
478       "   move.b  (%3,%1),%0\n" \
479       "   addq.l  #8,%0\n"      \
480       "0: and.l   #0xff,%0\n"   \
481       : "=&d" ((_output)), "=&d" ((dumby))    \
482       : "d" ((_value)), "ao" ((__BFFFOtable)) \
483       : "cc" ) ; \
484  }
485#elif ( M68K_HAS_EXTB_L == 1 )
486#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
487  { \
488    extern const unsigned char __BFFFOtable[256]; \
489    register int dumby; \
490    \
491    asm volatile ( "   move.w  %2,%1\n"        \
492       "   lsr.w   #8,%1\n"        \
493       "   beq.s   1f\n"           \
494       "   move.b  (%3,%1.w),%0\n" \
495       "   extb.l  %0\n"           \
496       "   bra.s   0f\n"           \
497       "1: moveq.l #8,%0\n"        \
498       "   add.b   (%3,%2.w),%0\n" \
499       "0:\n"                      \
500       : "=&d" ((_output)), "=&d" ((dumby)) \
501       : "d" ((_value)), "ao" ((__BFFFOtable)) \
502       : "cc" ) ; \
503  }
504#else
505#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
506  { \
507    extern const unsigned char __BFFFOtable[256]; \
508    register int dumby; \
509    \
510    asm volatile ( "   move.w  %2,%1\n"        \
511       "   lsr.w   #8,%1\n"        \
512       "   beq.s   1f\n"           \
513       "   move.b  (%3,%1.w),%0\n" \
514       "   and.l   #0x000000ff,%0\n"\
515       "   bra.s   0f\n"           \
516       "1: moveq.l #8,%0\n"        \
517       "   add.b   (%3,%2.w),%0\n" \
518       "0:\n"                      \
519       : "=&d" ((_output)), "=&d" ((dumby)) \
520       : "d" ((_value)), "ao" ((__BFFFOtable)) \
521       : "cc" ) ; \
522  }
523#endif
524
525#endif
526
527/* end of Bitfield handler macros */
528
529/*
530 *  Priority handler macros
531 *
532 *  These macros perform the following functions:
533 *    + return a mask with the bit for this major/minor portion of
534 *      of thread priority set.
535 *    + translate the bit number returned by "Bitfield_find_first_bit"
536 *      into an index into the thread ready chain bit maps
537 */
538
539#define _CPU_Priority_Mask( _bit_number ) \
540  ( 0x8000 >> (_bit_number) )
541
542#define _CPU_Priority_bits_index( _priority ) \
543  (_priority)
544
545/* end of Priority handler macros */
546
547/* functions */
548
549/*
550 *  _CPU_Initialize
551 *
552 *  This routine performs CPU dependent initialization.
553 */
554
555void _CPU_Initialize(
556  rtems_cpu_table  *cpu_table,
557  void      (*thread_dispatch)
558);
559
560/*
561 *  _CPU_ISR_install_raw_handler
562 *
563 *  This routine installs a "raw" interrupt handler directly into the
564 *  processor's vector table.
565 */
566 
567void _CPU_ISR_install_raw_handler(
568  unsigned32  vector,
569  proc_ptr    new_handler,
570  proc_ptr   *old_handler
571);
572
573/*
574 *  _CPU_ISR_install_vector
575 *
576 *  This routine installs an interrupt vector.
577 */
578
579void _CPU_ISR_install_vector(
580  unsigned32       vector,
581  proc_ptr         new_handler,
582  proc_ptr        *old_handler
583);
584
585/*
586 *  _CPU_Install_interrupt_stack
587 *
588 *  This routine installs the hardware interrupt stack pointer.
589 */
590
591void _CPU_Install_interrupt_stack( void );
592
593/*
594 *  _CPU_Context_switch
595 *
596 *  This routine switches from the run context to the heir context.
597 */
598
599void _CPU_Context_switch(
600  Context_Control  *run,
601  Context_Control  *heir
602);
603
604/*
605 *  _CPU_Context_save_fp
606 *
607 *  This routine saves the floating point context passed to it.
608 */
609
610void _CPU_Context_save_fp(
611  void **fp_context_ptr
612);
613
614/*
615 *  _CPU_Context_restore_fp
616 *
617 *  This routine restores the floating point context passed to it.
618 */
619
620void _CPU_Context_restore_fp(
621  void **fp_context_ptr
622);
623
624#if (M68K_HAS_FPSP_PACKAGE == 1)
625/*
626 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
627 *
628 *  NOTES: 
629 *
630 *  Motorola 68k family CPU's before the 68040 used a coprocessor
631 *  (68881 or 68882) to handle floating point.  The 68040 has internal
632 *  floating point support -- but *not* the complete support provided by
633 *  the 68881 or 68882.  The leftover functions are taken care of by the
634 *  M68040 Floating Point Support Package.  Quoting from the MC68040
635 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
636 *
637 *    "When used with the M68040FPSP, the MC68040 FPU is fully
638 *    compliant with IEEE floating-point standards."
639 *
640 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
641 *  is invoked early in the application code to insure that proper FP
642 *  behavior is installed.  This is not left to the BSP to call, since
643 *  this would force all applications using that BSP to use FPSP which
644 *  is not necessarily desirable.
645 *
646 *  There is a similar package for the 68060 but RTEMS does not yet
647 *  support the 68060.
648 */
649
650void M68KFPSPInstallExceptionHandlers (void);
651
652SCORE_EXTERN int (*_FPSP_install_raw_handler)(
653  unsigned32 vector,
654  proc_ptr new_handler,
655  proc_ptr *old_handler
656);
657
658#endif
659
660
661#endif
662
663#ifdef __cplusplus
664}
665#endif
666
667#endif
668/* end of include file */
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