source: rtems/c/src/exec/score/cpu/m68k/qsm.h @ 38ffa0c

4.104.114.84.95
Last change on this file since 38ffa0c was 38ffa0c, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 19, 1995 at 6:32:18 PM

Incorporated the submission from John S. Gwynne
<jsg@…> of the rest of the 68000-ish support
for interrupt handling and bfffo support, the two BSPs he submitted
(efi68k and efi332), and SGI Irix 5.3 host support.

  • Property mode set to 100644
File size: 7.7 KB
Line 
1/*
2 *-------------------------------------------------------------------
3 *
4 *   QSM -- Queued Serial Module
5 *
6 * The QSM contains two serial interfaces: (a) the queued serial
7 * peripheral interface (QSPI) and the serial communication interface
8 * (SCI). The QSPI provides peripheral expansion and/or interprocessor
9 * communication through a full-duplex, synchronous, three-wire bus. A
10 * self contained RAM queue permits serial data transfers without CPU
11 * intervention and automatic continuous sampling. The SCI provides a
12 * standard non-return to zero mark/space format with wakeup functions
13 * to allow the CPU to run uninterrupted until woken
14 *
15 * For more information, refer to Motorola's "Modular Microcontroller
16 * Family Queued Serial Module Reference Manual" (Motorola document
17 * QSMRM/AD).
18 *
19 * This file has been created by John S. Gwynne for support of
20 * Motorola's 68332 MCU in the efi332 project.
21 *
22 * Redistribution and use in source and binary forms are permitted
23 * provided that the following conditions are met:
24 * 1. Redistribution of source code and documentation must retain
25 *    the above authorship, this list of conditions and the
26 *    following disclaimer.
27 * 2. The name of the author may not be used to endorse or promote
28 *    products derived from this software without specific prior
29 *    written permission.
30 *
31 * This software is provided "AS IS" without warranty of any kind,
32 * either expressed or implied, including, but not limited to, the
33 * implied warranties of merchantability, title and fitness for a
34 * particular purpose.
35 *
36 *------------------------------------------------------------------
37 */
38#ifndef _QSM_H_
39#define _QSM_H_
40
41
42#include <efi332.h>
43
44
45/* SAM-- shift and mask */
46#undef  SAM
47#define SAM(a,b,c) ((a << b) & c)
48
49
50/* QSM_CRB (QSM Control Register Block) base address of the QSM
51   control registers */
52#if SIM_MM == 0
53#define QSM_CRB 0x7ffc00
54#else
55#undef SIM_MM
56#define SIM_MM 1
57#define QSM_CRB 0xfffc00
58#endif
59
60
61#define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB)
62                                /* QSM Configuration Register */
63#define    STOP 0x8000          /*    Stop Enable */
64#define    FRZ  0x6000          /*    Freeze Control */
65#define    SUPV 0x0080          /*    Supervisor/Unrestricted */
66#define    IARB 0x000f          /*    Inerrupt Arbitration */
67
68
69#define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB)
70                                /* QSM Test Register */
71/* Used only for factor testing */
72
73
74#define QILR (volatile unsigned char * const)(0x04 + QSM_CRB)
75                                /* QSM Interrupt Level Register */
76#define    ILQSPI 0x38          /*    Interrupt Level for QSPI */
77#define    ILSCI  0x07          /*    Interrupt Level for SCI */
78
79
80#define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB)
81                                /* QSM Interrupt Vector Register */
82#define    INTV   0xff          /*    Interrupt Vector Number */
83
84
85#define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB)
86                                /* SCI Control Register 0 */
87#define    SCBR   0x1fff        /*    SCI Baud Rate */
88
89
90#define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB)
91                                /* SCI Control Register 1 */
92#define    LOOPS  0x4000        /*    Loop Mode */
93#define    WOMS   0x2000        /*    Wired-OR Mode for SCI Pins */
94#define    ILT    0x1000        /*    Idle-Line Detect Type */
95#define    PT     0x0800        /*    Parity Type */
96#define    PE     0x0400        /*    Parity Enable */
97#define    M      0x0200        /*    Mode Select */
98#define    WAKE   0x0100        /*    Wakeup by Address Mark */
99#define    TIE    0x0080        /*    Transmit Complete Interrupt Enable */
100#define    TCIE   0x0040        /*    Transmit Complete Interrupt Enable */
101#define    RIE    0x0020        /*    Receiver Interrupt Enable */
102#define    ILIE   0x0010        /*    Idle-Line Interrupt Enable */
103#define    TE     0x0008        /*    Transmitter Enable */
104#define    RE     0x0004        /*    Receiver Enable */
105#define    RWU    0x0002        /*    Receiver Wakeup */
106#define    SBK    0x0001        /*    Send Break */
107
108
109#define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB)
110                                /* SCI Status Register */
111#define    TDRE   0x0100        /*    Transmit Data Register Empty */
112#define    TC     0x0080        /*    Transmit Complete */
113#define    RDRF   0x0040        /*    Receive Data Register Full */
114#define    RAF    0x0020        /*    Receiver Active */
115#define    IDLE   0x0010        /*    Idle-Line Detected */
116#define    OR     0x0008        /*    Overrun Error */
117#define    NF     0x0004        /*    Noise Error Flag */
118#define    FE     0x0002        /*    Framing Error */
119#define    PF     0x0001        /*    Parity Error */
120
121
122#define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB)
123                                /* SCI Data Register */
124
125
126#define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB)
127                                /* Port QS Data Register */
128
129#define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB)
130                                /* PORT QS Pin Assignment Rgister */
131/* Any bit cleared (zero) defines the corresponding pin to be an I/O
132   pin. Any bit set defines the corresponding pin to be a QSPI
133   signal. */
134/* note: PQS2 is a digital I/O pin unless the SPI is enabled in which
135   case it becomes the SPI serial clock SCK. */
136/* note: PQS7 is a digital I/O pin unless the SCI transmitter is
137   enabled in which case it becomes the SCI serial output TxD. */
138#define QSMFun 0x0
139#define QSMDis 0x1
140/*
141 * PQSPAR Field     | QSM Function | Discrete I/O pin
142 *------------------+--------------+------------------   */
143#define PQSPA0   0  /*   MISO      |      PQS0           */
144#define PQSPA1   1  /*   MOSI      |      PQS1           */
145#define PQSPA2   2  /*   SCK       |      PQS2 (see note)*/
146#define PQSPA3   3  /*   PCSO/!SS  |      PQS3           */
147#define PQSPA4   4  /*   PCS1      |      PQS4           */
148#define PQSPA5   5  /*   PCS2      |      PQS5           */
149#define PQSPA6   6  /*   PCS3      |      PQS6           */
150#define PQSPA7   7  /*   TxD       |      PQS7 (see note)*/
151
152
153#define DDRQS  (volatile unsigned char * const)(0x17 + QSM_CRB)
154                                /* PORT QS Data Direction Register */
155/* Clearing a bit makes the corresponding pin an input; setting a bit
156   makes the pin an output. */
157
158
159#define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB)
160                                /* QSPI Control Register 0 */
161#define    MSTR   0x8000        /*    Master/Slave Mode Select */
162#define    WOMQ   0x4000        /*    Wired-OR Mode for QSPI Pins */
163#define    BITS   0x3c00        /*    Bits Per Transfer */
164#define    CPOL   0x0200        /*    Clock Polarity */
165#define    CPHA   0x0100        /*    Clock Phase */
166#define    SPBR   0x00ff        /*    Serial Clock Baud Rate */
167
168
169#define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB)
170                                /* QSPI Control Register 1 */
171#define    SPE    0x8000        /*    QSPI Enable */
172#define    DSCKL  0x7f00        /*    Delay before SCK */
173#define    DTL    0x00ff        /*    Length of Delay after Transfer */
174
175
176#define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB)
177                                /* QSPI Control Register 2 */
178#define    SPIFIE 0x8000        /*    SPI Finished Interrupt Enable */
179#define    WREN   0x4000        /*    Wrap Enable */
180#define    WRTO   0x2000        /*    Wrap To */
181#define    ENDQP  0x0f00        /*    Ending Queue Pointer */
182#define    NEWQP  0x000f        /*    New Queue Pointer Value */
183
184
185#define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB)
186                                /* QSPI Control Register 3 */
187#define    LOOPQ  0x0400        /*    QSPI Loop Mode */
188#define    HMIE   0x0200        /*    HALTA and MODF Interrupt Enable */
189#define    HALT   0x0100        /*    Halt */
190
191
192#define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB)
193                                /* QSPI Status Register */
194#define    SPIF   0x0080        /*    QSPI Finished Flag */
195#define    MODF   0x0040        /*    Mode Fault Flag */
196#define    HALTA  0x0020        /*    Halt Acknowlwdge Flag */
197#define    CPTQP  x0000f        /*    Completed Queue Pointer */
198
199#define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB)
200                                /* QSPI Receive Data RAM */
201#define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB)
202                                /* QSPI Transmit Data RAM */
203#define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB)
204                                /* QSPI Command RAM */
205
206#endif /* _QSM_H_ */
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