source: rtems/c/src/exec/score/cpu/m68k/m68k.h @ dce1c1a1

4.104.114.84.95
Last change on this file since dce1c1a1 was dce1c1a1, checked in by Joel Sherrill <joel.sherrill@…>, on May 1, 1996 at 3:24:37 PM

Updates from Eric Norum to use the mcpu32 flags and fix comments.

  • Property mode set to 100644
File size: 8.8 KB
Line 
1/*  m68k.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __M68k_h
18#define __M68k_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  The following define the CPU Family and Model within the family
26 *
27 *  NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
28 *        with the name of the appropriate macro for this target CPU.
29 */
30 
31#ifdef m68k
32#undef m68k
33#endif
34#define m68k
35
36#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
37#undef REPLACE_THIS_WITH_THE_CPU_MODEL
38#endif
39#define REPLACE_THIS_WITH_THE_CPU_MODEL
40
41#ifdef REPLACE_THIS_WITH_THE_BSP
42#undef REPLACE_THIS_WITH_THE_BSP
43#endif
44#define REPLACE_THIS_WITH_THE_BSP
45
46/*
47 *  This section contains the information required to build
48 *  RTEMS for a particular member of the Motorola MC68xxx
49 *  family.  It does this by setting variables to indicate
50 *  which implementation dependent features are present in
51 *  a particular member of the family.
52 *
53 *  Currently recognized:
54 *     m68000        (no FP)
55 *     m68020        (implies FP)
56 *     m68020_nofp   (no FP)
57 *     m68030        (implies FP)
58 *     m68040        (implies FP)
59 *     m68lc040      (no FP)
60 *     m68ec040      (no FP)
61 *     m68302        (no FP)
62 *     mcpu32        (no FP)  (includes m68360)
63 *
64 *  Primary difference (for RTEMS) between m68040, m680lc040, and
65 *  m68ec040 is the presence or absence of the FPU.
66 *
67 *  Here is some information on the 040 variants (courtesy of Doug McBride,
68 *  mcbride@rodin.colorado.edu):
69 *
70 *    "The 68040 is a superset of the 68EC040 and the 68LC040.  The
71 *    68EC040 and 68LC040 do not have FPU's.  The 68LC040 and the
72 *    68EC040 have renamed the DLE pin as JS0 which must be tied to
73 *    Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1.  The
74 *    68EC040 has access control units instead of memory management units.
75 *    The 68EC040 should not have the PFLUSH or PTEST instructions executed
76 *    (cause an indeterminate result).  The 68EC040 and 68LC040 do not
77 *    implement the DLE or multiplexed bus modes.  The 68EC040 does not
78 *    implement the output buffer impedance selection mode of operation."
79 *
80 *  M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
81 *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
82 *  68010, 68302, 68306, 68307).  This instruction is available on the 68020
83 *  up and the cpu32 based models. 
84 *
85 *  NOTE:
86 *    Eventually it would be nice to evaluate doing a lot of this section
87 *    by having each model specigy which core it uses and then go from there.
88 */
89
90#if defined(m68000)
91 
92#define CPU_MODEL_NAME         "m68000"
93#define M68K_HAS_VBR             0
94#define M68K_HAS_SEPARATE_STACKS 0
95#define M68K_HAS_FPU             0
96#define M68K_HAS_BFFFO           0
97#define M68K_HAS_PREINDEXING     0
98#define M68K_HAS_EXTB_L          0
99
100#elif defined(m68020)
101 
102#define CPU_MODEL_NAME         "m68020"
103#define M68K_HAS_VBR             1
104#define M68K_HAS_SEPARATE_STACKS 1
105#define M68K_HAS_FPU             1
106#define M68K_HAS_BFFFO           1
107#define M68K_HAS_PREINDEXING     1
108#define M68K_HAS_EXTB_L          1
109 
110#elif defined(m68020_nofp)
111 
112#define CPU_MODEL_NAME         "m68020 w/o fp"
113#define M68K_HAS_VBR             1
114#define M68K_HAS_SEPARATE_STACKS 1
115#define M68K_HAS_FPU             0
116#define M68K_HAS_BFFFO           1
117#define M68K_HAS_PREINDEXING     1
118#define M68K_HAS_EXTB_L          1
119 
120#elif defined(m68030)
121 
122#define CPU_MODEL_NAME         "m68030"
123#define M68K_HAS_VBR             1
124#define M68K_HAS_SEPARATE_STACKS 1
125#define M68K_HAS_FPU             1
126#define M68K_HAS_BFFFO           1
127#define M68K_HAS_PREINDEXING     1
128#define M68K_HAS_EXTB_L          1
129 
130#elif defined(m68040)
131
132#define CPU_MODEL_NAME         "m68040"
133#define M68K_HAS_VBR             1
134#define M68K_HAS_SEPARATE_STACKS 1
135#define M68K_HAS_FPU             1
136#define M68K_HAS_BFFFO           1
137#define M68K_HAS_PREINDEXING     1
138#define M68K_HAS_EXTB_L          1
139 
140#elif defined(m68lc040)
141
142#define CPU_MODEL_NAME         "m68lc040"
143#define M68K_HAS_VBR             1
144#define M68K_HAS_SEPARATE_STACKS 1
145#define M68K_HAS_FPU             0
146#define M68K_HAS_BFFFO           1
147#define M68K_HAS_PREINDEXING     1
148#define M68K_HAS_EXTB_L          1
149 
150#elif defined(m68ec040)
151
152#define CPU_MODEL_NAME         "m68ec040"
153#define M68K_HAS_VBR             1
154#define M68K_HAS_SEPARATE_STACKS 1
155#define M68K_HAS_FPU             0
156#define M68K_HAS_BFFFO           1
157#define M68K_HAS_PREINDEXING     1
158#define M68K_HAS_EXTB_L          1
159
160#elif defined(m68302)
161 /* essentially a m68000 with onboard peripherals */
162#define CPU_MODEL_NAME         "m68302"
163#define M68K_HAS_VBR             0
164#define M68K_HAS_SEPARATE_STACKS 0
165#define M68K_HAS_FPU             0
166#define M68K_HAS_BFFFO           0
167#define M68K_HAS_PREINDEXING     0
168#define M68K_HAS_EXTB_L          0
169
170#elif defined(m68332)
171 
172#define CPU_MODEL_NAME         "m68332"
173#define M68K_HAS_VBR             1
174#define M68K_HAS_SEPARATE_STACKS 0
175#define M68K_HAS_FPU             0
176#define M68K_HAS_BFFFO           0
177#define M68K_HAS_PREINDEXING     0
178#define M68K_HAS_EXTB_L          1
179
180#elif defined(mcpu32)
181 
182#define CPU_MODEL_NAME         "mcpu32"
183#define M68K_HAS_VBR             1
184#define M68K_HAS_SEPARATE_STACKS 0
185#define M68K_HAS_FPU             0
186#define M68K_HAS_BFFFO           0
187#define M68K_HAS_PREINDEXING     1
188#define M68K_HAS_EXTB_L          1
189
190#else
191
192#error "Unsupported CPU Model"
193
194#endif
195
196/*
197 *  If defined, this causes some of the macros to initialize their
198 *  variables to zero before doing inline assembly.  This gets rid
199 *  of compile time warnings at the cost of a little execution time
200 *  in some time critical routines.
201 */
202
203#define NO_UNINITIALIZED_WARNINGS
204
205/*
206 *  Define the name of the CPU family.
207 */
208
209#define CPU_NAME "Motorola MC68xxx"
210
211#ifndef ASM
212
213#ifdef NO_UNINITIALIZED_WARNINGS
214#define m68k_disable_interrupts( _level ) \
215  { \
216    (_level) = 0;  /* avoids warnings */ \
217    asm volatile ( "movew   %%sr,%0 ; \
218                    orw     #0x0700,%%sr" \
219                    : "=d" ((_level)) : "0" ((_level)) \
220    ); \
221  }
222#else
223#define m68k_disable_interrupts( _level ) \
224  { \
225    asm volatile ( "movew   %%sr,%0 ; \
226                    orw     #0x0700,%%sr" \
227                    : "=d" ((_level)) : "0" ((_level)) \
228    ); \
229  }
230#endif
231
232#define m68k_enable_interrupts( _level ) \
233  { \
234    asm volatile ( "movew   %0,%%sr " \
235                   : "=d" ((_level)) : "0" ((_level)) \
236    ); \
237  }
238
239#define m68k_flash_interrupts( _level ) \
240  { \
241    asm volatile ( "movew   %0,%%sr ; \
242                    orw     #0x0700,%%sr" \
243                    : "=d" ((_level)) : "0" ((_level)) \
244    ); \
245  }
246
247#define m68k_get_interrupt_level( _level ) \
248  do { \
249    register unsigned32 _tmpsr = 0; \
250    \
251    asm volatile( "movw  %%sr,%0" \
252                   : "=d" (_tmpsr) : "0" (_tmpsr) \
253    ); \
254    \
255    _level = (_tmpsr & 0x0700) >> 8; \
256  } while (0)
257   
258#define m68k_set_interrupt_level( _newlevel ) \
259  { \
260    register unsigned32 _tmpsr = 0; \
261    \
262    asm volatile( "movw  %%sr,%0" \
263                   : "=d" (_tmpsr) : "0" (_tmpsr) \
264    ); \
265    \
266    _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
267    \
268    asm volatile( "movw  %0,%%sr" \
269                   : "=d" (_tmpsr) : "0" (_tmpsr) \
270    ); \
271  }
272
273#if ( M68K_HAS_VBR == 1 )
274#define m68k_get_vbr( vbr ) \
275  { (vbr) = 0; \
276    asm volatile ( "movec   %%vbr,%0 " \
277                       : "=r" (vbr) : "0" (vbr) ); \
278  }
279
280#define m68k_set_vbr( vbr ) \
281  { register m68k_isr *_vbr= (m68k_isr *)(vbr); \
282    asm volatile ( "movec   %0,%%vbr " \
283                       : "=a" (_vbr) : "0" (_vbr) ); \
284  }
285#else
286#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
287#define m68k_set_vbr( _vbr )
288#endif
289
290/*
291 *  The following routine swaps the endian format of an unsigned int.
292 *  It must be static because it is referenced indirectly.
293 */
294
295static inline unsigned int m68k_swap_u32(
296  unsigned int value
297)
298{
299  unsigned int swapped = value;
300
301  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
302  asm volatile( "swap  %0"    : "=d" (swapped) : "0" (swapped) );
303  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
304
305  return( swapped );
306}
307
308/* XXX this is only valid for some m68k family members and should be fixed */
309
310#define m68k_enable_caching() \
311  { register unsigned32 _ctl=0x01; \
312    asm volatile ( "movec   %0,%%cacr" \
313                       : "=d" (_ctl) : "0" (_ctl) ); \
314  }
315
316#define CPU_swap_u32( value )  m68k_swap_u32( value )
317
318#ifdef __cplusplus
319}
320#endif
321
322#endif  /* !ASM */
323
324#endif
325/* end of include file */
Note: See TracBrowser for help on using the repository browser.