source: rtems/c/src/exec/score/cpu/m68k/m68k.h @ b22b1294

4.104.114.84.95
Last change on this file since b22b1294 was b22b1294, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 25, 1998 at 4:26:43 PM

Coldfire support patch from David Fiddes <D.J.Fiddes@…>.

  • Property mode set to 100644
File size: 10.0 KB
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1/*  m68k.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __M68k_h
18#define __M68k_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  This section contains the information required to build
26 *  RTEMS for a particular member of the Motorola MC68xxx
27 *  family.  It does this by setting variables to indicate
28 *  which implementation dependent features are present in
29 *  a particular member of the family.
30 *
31 *  Currently recognized:
32 *     -m68000
33 *     -m68000 -msoft-float
34 *     -m68020
35 *     -m68020 -msoft-float
36 *     -m68030
37 *     -m68040 -msoft-float
38 *     -m68040
39 *     -m68040 -msoft-float
40 *     -m68302        (no FP) (deprecated, use -m68000)
41 *     -m68332        (no FP) (deprecated, use -mcpu32)
42 *     -mcpu32        (no FP)
43 *     -m5200         (no FP)
44 *
45 *  As of gcc 2.8.1 and egcs 1.1, there is no distinction made between
46 *  the CPU32 and CPU32+.  The option -mcpu32 generates code which can
47 *  be run on either core.  RTEMS distinguishes between these two cores
48 *  because they have different alignment rules which impact performance.
49 *  If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should
50 *  be defined in your custom file (see make/custom/gen68360.cfg for an
51 *  example of how to do this.  If gcc ever distinguishes between these
52 *  two cores, then RTEMS__mcpu32p__ usage will be replaced with the
53 *  appropriate compiler defined predefine.
54 *
55 *  Here is some information on the 040 variants (courtesy of Doug McBride,
56 *  mcbride@rodin.colorado.edu):
57 *
58 *    "The 68040 is a superset of the 68EC040 and the 68LC040.  The
59 *    68EC040 and 68LC040 do not have FPU's.  The 68LC040 and the
60 *    68EC040 have renamed the DLE pin as JS0 which must be tied to
61 *    Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1.  The
62 *    68EC040 has access control units instead of memory management units.
63 *    The 68EC040 should not have the PFLUSH or PTEST instructions executed
64 *    (cause an indeterminate result).  The 68EC040 and 68LC040 do not
65 *    implement the DLE or multiplexed bus modes.  The 68EC040 does not
66 *    implement the output buffer impedance selection mode of operation."
67 *
68 *  M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
69 *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
70 *  68010, 68302, 68306, 68307).  This instruction is available on the 68020
71 *  up and the cpu32 based models. 
72 *
73 *  M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
74 *  data access (68020, 68030, 68040, 68060, CPU32+).
75 *
76 *  NOTE:
77 *    Eventually it would be nice to evaluate doing a lot of this section
78 *    by having each model specify which core it uses and then go from there.
79 */
80
81#if defined(__mc68020__)
82 
83#define CPU_MODEL_NAME          "m68020"
84#define M68K_HAS_VBR             1
85#define M68K_HAS_SEPARATE_STACKS 1
86#define M68K_HAS_BFFFO           1
87#define M68K_HAS_PREINDEXING     1
88#define M68K_HAS_EXTB_L          1
89#define M68K_HAS_MISALIGNED      1
90# if defined (__HAVE_68881__)
91# define M68K_HAS_FPU            1
92# define M68K_HAS_FPSP_PACKAGE   0
93# else
94# define M68K_HAS_FPU            0
95# define M68K_HAS_FPSP_PACKAGE   0
96# endif
97 
98#elif defined(__mc68030__)
99 
100#define CPU_MODEL_NAME          "m68030"
101#define M68K_HAS_VBR             1
102#define M68K_HAS_SEPARATE_STACKS 1
103#define M68K_HAS_BFFFO           1
104#define M68K_HAS_PREINDEXING     1
105#define M68K_HAS_EXTB_L          1
106#define M68K_HAS_MISALIGNED      1
107# if defined (__HAVE_68881__)
108# define M68K_HAS_FPU            1
109# define M68K_HAS_FPSP_PACKAGE   0
110# else
111# define M68K_HAS_FPU            0
112# define M68K_HAS_FPSP_PACKAGE   0
113# endif
114 
115#elif defined(__mc68040__)
116
117#define CPU_MODEL_NAME          "m68040"
118#define M68K_HAS_VBR             1
119#define M68K_HAS_SEPARATE_STACKS 1
120#define M68K_HAS_BFFFO           1
121#define M68K_HAS_PREINDEXING     1
122#define M68K_HAS_EXTB_L          1
123#define M68K_HAS_MISALIGNED      1
124# if defined (__HAVE_68881__)
125# define M68K_HAS_FPU            1
126# define M68K_HAS_FPSP_PACKAGE   1
127# else
128# define M68K_HAS_FPU            0
129# define M68K_HAS_FPSP_PACKAGE   0
130# endif
131 
132#elif defined(__mc68302__)
133#define CPU_MODEL_NAME          "m68302"
134#define M68K_HAS_VBR             0
135#define M68K_HAS_SEPARATE_STACKS 0
136#define M68K_HAS_BFFFO           0
137#define M68K_HAS_PREINDEXING     0
138#define M68K_HAS_EXTB_L          0
139#define M68K_HAS_MISALIGNED      0
140#define M68K_HAS_FPU             0
141#define M68K_HAS_FPSP_PACKAGE    0
142
143  /* gcc and egcs do not distinguish between CPU32 and CPU32+ */
144#elif defined(RTEMS__mcpu32p__)
145 
146#define CPU_MODEL_NAME          "mcpu32+"
147#define M68K_HAS_VBR             1
148#define M68K_HAS_SEPARATE_STACKS 0
149#define M68K_HAS_BFFFO           0
150#define M68K_HAS_PREINDEXING     1
151#define M68K_HAS_EXTB_L          1
152#define M68K_HAS_MISALIGNED      1
153#define M68K_HAS_FPU             0
154#define M68K_HAS_FPSP_PACKAGE    0
155
156#elif defined(__mcpu32__)
157 
158#define CPU_MODEL_NAME          "mcpu32"
159#define M68K_HAS_VBR             1
160#define M68K_HAS_SEPARATE_STACKS 0
161#define M68K_HAS_BFFFO           0
162#define M68K_HAS_PREINDEXING     1
163#define M68K_HAS_EXTB_L          1
164#define M68K_HAS_MISALIGNED      0
165#define M68K_HAS_FPU             0
166#define M68K_HAS_FPSP_PACKAGE    0
167
168#elif defined(__mcf5200__)
169/* Motorola ColdFire V2 core - RISC/68020 hybrid */ 
170#define CPU_MODEL_NAME         "m5200"
171#define M68K_HAS_VBR             1
172#define M68K_HAS_BFFFO           0
173#define M68K_HAS_SEPARATE_STACKS 0
174#define M68K_HAS_PREINDEXING     0
175#define M68K_HAS_EXTB_L          1
176#define M68K_HAS_MISALIGNED      1
177#define M68K_HAS_FPU             0
178#define M68K_HAS_FPSP_PACKAGE    0
179#define M68K_COLDFIRE_ARCH       1
180
181#elif defined(__mc68000__)
182 
183#define CPU_MODEL_NAME          "m68000"
184#define M68K_HAS_VBR             0
185#define M68K_HAS_SEPARATE_STACKS 0
186#define M68K_HAS_BFFFO           0
187#define M68K_HAS_PREINDEXING     0
188#define M68K_HAS_EXTB_L          0
189#define M68K_HAS_MISALIGNED      0
190# if defined (__HAVE_68881__)
191# define M68K_HAS_FPU            1
192# define M68K_HAS_FPSP_PACKAGE   0
193# else
194# define M68K_HAS_FPU            0
195# define M68K_HAS_FPSP_PACKAGE   0
196# endif
197
198#else
199
200#error "Unsupported CPU model -- are you sure you're running a 68k compiler?"
201
202#endif
203
204/*
205 *  If the above did not specify a ColdFire architecture, then set
206 *  this flag to indicate that it is not a ColdFire CPU.
207 */
208
209#if !defined(M68K_COLDFIRE_ARCH)
210#define M68K_COLDFIRE_ARCH       0
211#endif
212
213/*
214 *  Define the name of the CPU family.
215 */
216
217#if ( M68K_COLDFIRE_ARCH == 1 )
218  #define CPU_NAME "Motorola ColdFire"
219#else
220  #define CPU_NAME "Motorola MC68xxx"
221#endif
222
223#ifndef ASM
224
225#if ( M68K_COLDFIRE_ARCH == 1 )
226#define m68k_disable_interrupts( _level ) \
227   do { register unsigned32 _tmpsr = 0x0700; \
228        asm volatile ( "move.w %%sr,%0\n\t" \
229                       "or.l   %0,%1\n\t" \
230                       "move.w %1,%%sr" \
231                       : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) ); \
232   } while( 0 )
233#else
234#define m68k_disable_interrupts( _level ) \
235  asm volatile ( "move.w  %%sr,%0\n\t" \
236                 "or.w    #0x0700,%%sr" \
237                    : "=d" (_level))
238#endif
239
240#define m68k_enable_interrupts( _level ) \
241  asm volatile ( "move.w  %0,%%sr " : : "d" (_level));
242
243#if ( M68K_COLDFIRE_ARCH == 1 )
244#define m68k_flash_interrupts( _level ) \
245   do { register unsigned32 _tmpsr = 0x0700; \
246        asm volatile ( "move.w %2,%%sr\n\t" \
247                       "or.l   %2,%1\n\t" \
248                       "move.w %1,%%sr" \
249                       : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) ); \
250   } while( 0 )
251#else
252#define m68k_flash_interrupts( _level ) \
253  asm volatile ( "move.w  %0,%%sr\n\t" \
254                 "or.w    #0x0700,%%sr" \
255                    : : "d" (_level))
256#endif
257
258#define m68k_get_interrupt_level( _level ) \
259  do { \
260    register unsigned32 _tmpsr; \
261    \
262    asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
263    _level = (_tmpsr & 0x0700) >> 8; \
264  } while (0)
265   
266#define m68k_set_interrupt_level( _newlevel ) \
267  do { \
268    register unsigned32 _tmpsr; \
269    \
270    asm volatile( "move.w  %%sr,%0" : "=d" (_tmpsr)); \
271    _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
272    asm volatile( "move.w  %0,%%sr" : : "d" (_tmpsr)); \
273  } while (0)
274
275#if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 )
276#define m68k_get_vbr( vbr ) \
277  asm volatile ( "movec   %%vbr,%0 " : "=r" (vbr))
278
279#define m68k_set_vbr( vbr ) \
280  asm volatile ( "movec   %0,%%vbr " : : "r" (vbr))
281
282#elif ( M68K_COLDFIRE_ARCH == 1 )
283#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
284
285#define m68k_set_vbr( _vbr ) \
286    asm volatile ("move.l  %%a7,%%d1 \n\t" \
287                  "move.l  %0,%%a7\n\t"    \
288                  "movec   %%a7,%%vbr\n\t" \
289                  "move.l  %%d1,%%a7\n\t"  \
290                  : : "d" (_vbr) : "d1" );
291 
292#else
293#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
294#define m68k_set_vbr( _vbr )
295#endif
296
297/*
298 *  The following routine swaps the endian format of an unsigned int.
299 *  It must be static because it is referenced indirectly.
300 */
301
302static inline unsigned int m68k_swap_u32(
303  unsigned int value
304)
305{
306  unsigned int swapped = value;
307
308  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
309  asm volatile( "swap  %0"    : "=d" (swapped) : "0" (swapped) );
310  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
311
312  return( swapped );
313}
314
315static inline unsigned int m68k_swap_u16(
316  unsigned int value
317)
318{
319  unsigned short swapped = value;
320
321  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
322
323  return( swapped );
324}
325
326/* XXX this is only valid for some m68k family members and should be fixed */
327
328#define m68k_enable_caching() \
329  { register unsigned32 _ctl=0x01; \
330    asm volatile ( "movec   %0,%%cacr" \
331                       : "=d" (_ctl) : "0" (_ctl) ); \
332  }
333
334#define CPU_swap_u32( value )  m68k_swap_u32( value )
335#define CPU_swap_u16( value )  m68k_swap_u16( value )
336
337#endif  /* !ASM */
338
339#ifdef __cplusplus
340}
341#endif
342
343#endif
344/* end of include file */
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