source: rtems/c/src/exec/score/cpu/m68k/m68k.h @ 98e4ebf

4.104.114.84.9
Last change on this file since 98e4ebf was 98e4ebf, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 8, 1997 at 3:45:54 PM

Fixed typo in the pointer to the license terms.

  • Property mode set to 100644
File size: 7.6 KB
Line 
1/*  m68k.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1997.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __M68k_h
18#define __M68k_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  This section contains the information required to build
26 *  RTEMS for a particular member of the Motorola MC68xxx
27 *  family.  It does this by setting variables to indicate
28 *  which implementation dependent features are present in
29 *  a particular member of the family.
30 *
31 *  Currently recognized:
32 *     m68000        (no FP)
33 *     m68020        (implies FP)
34 *     m68020_nofp   (no FP)
35 *     m68030        (implies FP)
36 *     m68040        (implies FP)
37 *     m68lc040      (no FP)
38 *     m68ec040      (no FP)
39 *     m68302        (no FP)
40 *     m68332        (no FP)
41 *     mcpu32        (no FP)  (includes m68360)
42 *
43 *  Primary difference (for RTEMS) between m68040, m680lc040, and
44 *  m68ec040 is the presence or absence of the FPU.
45 *
46 *  Here is some information on the 040 variants (courtesy of Doug McBride,
47 *  mcbride@rodin.colorado.edu):
48 *
49 *    "The 68040 is a superset of the 68EC040 and the 68LC040.  The
50 *    68EC040 and 68LC040 do not have FPU's.  The 68LC040 and the
51 *    68EC040 have renamed the DLE pin as JS0 which must be tied to
52 *    Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1.  The
53 *    68EC040 has access control units instead of memory management units.
54 *    The 68EC040 should not have the PFLUSH or PTEST instructions executed
55 *    (cause an indeterminate result).  The 68EC040 and 68LC040 do not
56 *    implement the DLE or multiplexed bus modes.  The 68EC040 does not
57 *    implement the output buffer impedance selection mode of operation."
58 *
59 *  M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
60 *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
61 *  68010, 68302, 68306, 68307).  This instruction is available on the 68020
62 *  up and the cpu32 based models. 
63 *
64 *  NOTE:
65 *    Eventually it would be nice to evaluate doing a lot of this section
66 *    by having each model specify which core it uses and then go from there.
67 */
68
69#if defined(m68000)
70 
71#define CPU_MODEL_NAME         "m68000"
72#define M68K_HAS_VBR             0
73#define M68K_HAS_SEPARATE_STACKS 0
74#define M68K_HAS_FPU             0
75#define M68K_HAS_BFFFO           0
76#define M68K_HAS_PREINDEXING     0
77#define M68K_HAS_EXTB_L          0
78#define M68K_HAS_FPSP_PACKAGE    0
79
80#elif defined(m68020)
81 
82#define CPU_MODEL_NAME         "m68020"
83#define M68K_HAS_VBR             1
84#define M68K_HAS_SEPARATE_STACKS 1
85#define M68K_HAS_FPU             1
86#define M68K_HAS_BFFFO           1
87#define M68K_HAS_PREINDEXING     1
88#define M68K_HAS_EXTB_L          1
89#define M68K_HAS_FPSP_PACKAGE    0
90 
91#elif defined(m68020_nofp)
92 
93#define CPU_MODEL_NAME         "m68020 w/o fp"
94#define M68K_HAS_VBR             1
95#define M68K_HAS_SEPARATE_STACKS 1
96#define M68K_HAS_FPU             0
97#define M68K_HAS_BFFFO           1
98#define M68K_HAS_PREINDEXING     1
99#define M68K_HAS_EXTB_L          1
100#define M68K_HAS_FPSP_PACKAGE    0
101 
102#elif defined(m68030)
103 
104#define CPU_MODEL_NAME         "m68030"
105#define M68K_HAS_VBR             1
106#define M68K_HAS_SEPARATE_STACKS 1
107#define M68K_HAS_FPU             1
108#define M68K_HAS_BFFFO           1
109#define M68K_HAS_PREINDEXING     1
110#define M68K_HAS_EXTB_L          1
111#define M68K_HAS_FPSP_PACKAGE    0
112 
113#elif defined(m68040)
114
115#define CPU_MODEL_NAME         "m68040"
116#define M68K_HAS_VBR             1
117#define M68K_HAS_SEPARATE_STACKS 1
118#define M68K_HAS_FPU             1
119#define M68K_HAS_BFFFO           1
120#define M68K_HAS_PREINDEXING     1
121#define M68K_HAS_EXTB_L          1
122#define M68K_HAS_FPSP_PACKAGE    1
123 
124#elif defined(m68lc040)
125
126#define CPU_MODEL_NAME         "m68lc040"
127#define M68K_HAS_VBR             1
128#define M68K_HAS_SEPARATE_STACKS 1
129#define M68K_HAS_FPU             0
130#define M68K_HAS_BFFFO           1
131#define M68K_HAS_PREINDEXING     1
132#define M68K_HAS_EXTB_L          1
133#define M68K_HAS_FPSP_PACKAGE    0
134 
135#elif defined(m68ec040)
136
137#define CPU_MODEL_NAME         "m68ec040"
138#define M68K_HAS_VBR             1
139#define M68K_HAS_SEPARATE_STACKS 1
140#define M68K_HAS_FPU             0
141#define M68K_HAS_BFFFO           1
142#define M68K_HAS_PREINDEXING     1
143#define M68K_HAS_EXTB_L          1
144#define M68K_HAS_FPSP_PACKAGE    0
145
146#elif defined(m68302)
147 /* essentially a m68000 with onboard peripherals */
148#define CPU_MODEL_NAME         "m68302"
149#define M68K_HAS_VBR             0
150#define M68K_HAS_SEPARATE_STACKS 0
151#define M68K_HAS_FPU             0
152#define M68K_HAS_BFFFO           0
153#define M68K_HAS_PREINDEXING     0
154#define M68K_HAS_EXTB_L          0
155#define M68K_HAS_FPSP_PACKAGE    0
156
157#elif defined(m68332)
158 
159#define CPU_MODEL_NAME         "m68332"
160#define M68K_HAS_VBR             1
161#define M68K_HAS_SEPARATE_STACKS 0
162#define M68K_HAS_FPU             0
163#define M68K_HAS_BFFFO           0
164#define M68K_HAS_PREINDEXING     0
165#define M68K_HAS_EXTB_L          1
166#define M68K_HAS_FPSP_PACKAGE    0
167
168#elif defined(mcpu32)
169 
170#define CPU_MODEL_NAME         "mcpu32"
171#define M68K_HAS_VBR             1
172#define M68K_HAS_SEPARATE_STACKS 0
173#define M68K_HAS_FPU             0
174#define M68K_HAS_BFFFO           0
175#define M68K_HAS_PREINDEXING     1
176#define M68K_HAS_EXTB_L          1
177#define M68K_HAS_FPSP_PACKAGE    0
178
179#else
180
181#error "Unsupported CPU Model"
182
183#endif
184
185/*
186 *  Define the name of the CPU family.
187 */
188
189#define CPU_NAME "Motorola MC68xxx"
190
191#ifndef ASM
192
193#define m68k_disable_interrupts( _level ) \
194  asm volatile ( "movew   %%sr,%0\n\t" \
195                 "orw     #0x0700,%%sr" \
196                    : "=d" (_level))
197
198#define m68k_enable_interrupts( _level ) \
199  asm volatile ( "movew   %0,%%sr " : : "d" (_level));
200
201#define m68k_flash_interrupts( _level ) \
202  asm volatile ( "movew   %0,%%sr\n\t" \
203                 "orw     #0x0700,%%sr" \
204                    : : "d" (_level))
205
206#define m68k_get_interrupt_level( _level ) \
207  do { \
208    register unsigned32 _tmpsr; \
209    \
210    asm volatile( "movw  %%sr,%0" : "=d" (_tmpsr)); \
211    _level = (_tmpsr & 0x0700) >> 8; \
212  } while (0)
213   
214#define m68k_set_interrupt_level( _newlevel ) \
215  do { \
216    register unsigned32 _tmpsr; \
217    \
218    asm volatile( "movw  %%sr,%0" : "=d" (_tmpsr)); \
219    _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
220    asm volatile( "movw  %0,%%sr" : : "d" (_tmpsr)); \
221  } while (0)
222
223#if ( M68K_HAS_VBR == 1 )
224#define m68k_get_vbr( vbr ) \
225  asm volatile ( "movec   %%vbr,%0 " : "=r" (vbr))
226
227#define m68k_set_vbr( vbr ) \
228  asm volatile ( "movec   %0,%%vbr " : : "r" (vbr))
229#else
230#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
231#define m68k_set_vbr( _vbr )
232#endif
233
234/*
235 *  The following routine swaps the endian format of an unsigned int.
236 *  It must be static because it is referenced indirectly.
237 */
238
239static inline unsigned int m68k_swap_u32(
240  unsigned int value
241)
242{
243  unsigned int swapped = value;
244
245  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
246  asm volatile( "swap  %0"    : "=d" (swapped) : "0" (swapped) );
247  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
248
249  return( swapped );
250}
251
252/* XXX this is only valid for some m68k family members and should be fixed */
253
254#define m68k_enable_caching() \
255  { register unsigned32 _ctl=0x01; \
256    asm volatile ( "movec   %0,%%cacr" \
257                       : "=d" (_ctl) : "0" (_ctl) ); \
258  }
259
260#define CPU_swap_u32( value )  m68k_swap_u32( value )
261
262#ifdef __cplusplus
263}
264#endif
265
266#endif  /* !ASM */
267
268#endif
269/* end of include file */
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