source: rtems/c/src/exec/score/cpu/m68k/m68k.h @ 541dfb2

4.104.114.84.95
Last change on this file since 541dfb2 was 541dfb2, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 29, 1997 at 12:22:24 AM

Removed definitions which are now in targopts.h. This eliminates the
need for the "sed'ing" of this file. This should be a significant win
when addressing non-unix host and non-gnu toolsets.

  • Property mode set to 100644
File size: 7.3 KB
Line 
1/*  m68k.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __M68k_h
18#define __M68k_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  This section contains the information required to build
26 *  RTEMS for a particular member of the Motorola MC68xxx
27 *  family.  It does this by setting variables to indicate
28 *  which implementation dependent features are present in
29 *  a particular member of the family.
30 *
31 *  Currently recognized:
32 *     m68000        (no FP)
33 *     m68020        (implies FP)
34 *     m68020_nofp   (no FP)
35 *     m68030        (implies FP)
36 *     m68040        (implies FP)
37 *     m68lc040      (no FP)
38 *     m68ec040      (no FP)
39 *     m68302        (no FP)
40 *     mcpu32        (no FP)  (includes m68360)
41 *
42 *  Primary difference (for RTEMS) between m68040, m680lc040, and
43 *  m68ec040 is the presence or absence of the FPU.
44 *
45 *  Here is some information on the 040 variants (courtesy of Doug McBride,
46 *  mcbride@rodin.colorado.edu):
47 *
48 *    "The 68040 is a superset of the 68EC040 and the 68LC040.  The
49 *    68EC040 and 68LC040 do not have FPU's.  The 68LC040 and the
50 *    68EC040 have renamed the DLE pin as JS0 which must be tied to
51 *    Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1.  The
52 *    68EC040 has access control units instead of memory management units.
53 *    The 68EC040 should not have the PFLUSH or PTEST instructions executed
54 *    (cause an indeterminate result).  The 68EC040 and 68LC040 do not
55 *    implement the DLE or multiplexed bus modes.  The 68EC040 does not
56 *    implement the output buffer impedance selection mode of operation."
57 *
58 *  M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
59 *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
60 *  68010, 68302, 68306, 68307).  This instruction is available on the 68020
61 *  up and the cpu32 based models. 
62 *
63 *  NOTE:
64 *    Eventually it would be nice to evaluate doing a lot of this section
65 *    by having each model specigy which core it uses and then go from there.
66 */
67
68#if defined(m68000)
69 
70#define CPU_MODEL_NAME         "m68000"
71#define M68K_HAS_VBR             0
72#define M68K_HAS_SEPARATE_STACKS 0
73#define M68K_HAS_FPU             0
74#define M68K_HAS_BFFFO           0
75#define M68K_HAS_PREINDEXING     0
76#define M68K_HAS_EXTB_L          0
77
78#elif defined(m68020)
79 
80#define CPU_MODEL_NAME         "m68020"
81#define M68K_HAS_VBR             1
82#define M68K_HAS_SEPARATE_STACKS 1
83#define M68K_HAS_FPU             1
84#define M68K_HAS_BFFFO           1
85#define M68K_HAS_PREINDEXING     1
86#define M68K_HAS_EXTB_L          1
87 
88#elif defined(m68020_nofp)
89 
90#define CPU_MODEL_NAME         "m68020 w/o fp"
91#define M68K_HAS_VBR             1
92#define M68K_HAS_SEPARATE_STACKS 1
93#define M68K_HAS_FPU             0
94#define M68K_HAS_BFFFO           1
95#define M68K_HAS_PREINDEXING     1
96#define M68K_HAS_EXTB_L          1
97 
98#elif defined(m68030)
99 
100#define CPU_MODEL_NAME         "m68030"
101#define M68K_HAS_VBR             1
102#define M68K_HAS_SEPARATE_STACKS 1
103#define M68K_HAS_FPU             1
104#define M68K_HAS_BFFFO           1
105#define M68K_HAS_PREINDEXING     1
106#define M68K_HAS_EXTB_L          1
107 
108#elif defined(m68040)
109
110#define CPU_MODEL_NAME         "m68040"
111#define M68K_HAS_VBR             1
112#define M68K_HAS_SEPARATE_STACKS 1
113#define M68K_HAS_FPU             1
114#define M68K_HAS_BFFFO           1
115#define M68K_HAS_PREINDEXING     1
116#define M68K_HAS_EXTB_L          1
117 
118#elif defined(m68lc040)
119
120#define CPU_MODEL_NAME         "m68lc040"
121#define M68K_HAS_VBR             1
122#define M68K_HAS_SEPARATE_STACKS 1
123#define M68K_HAS_FPU             0
124#define M68K_HAS_BFFFO           1
125#define M68K_HAS_PREINDEXING     1
126#define M68K_HAS_EXTB_L          1
127 
128#elif defined(m68ec040)
129
130#define CPU_MODEL_NAME         "m68ec040"
131#define M68K_HAS_VBR             1
132#define M68K_HAS_SEPARATE_STACKS 1
133#define M68K_HAS_FPU             0
134#define M68K_HAS_BFFFO           1
135#define M68K_HAS_PREINDEXING     1
136#define M68K_HAS_EXTB_L          1
137
138#elif defined(m68302)
139 /* essentially a m68000 with onboard peripherals */
140#define CPU_MODEL_NAME         "m68302"
141#define M68K_HAS_VBR             0
142#define M68K_HAS_SEPARATE_STACKS 0
143#define M68K_HAS_FPU             0
144#define M68K_HAS_BFFFO           0
145#define M68K_HAS_PREINDEXING     0
146#define M68K_HAS_EXTB_L          0
147
148#elif defined(m68332)
149 
150#define CPU_MODEL_NAME         "m68332"
151#define M68K_HAS_VBR             1
152#define M68K_HAS_SEPARATE_STACKS 0
153#define M68K_HAS_FPU             0
154#define M68K_HAS_BFFFO           0
155#define M68K_HAS_PREINDEXING     0
156#define M68K_HAS_EXTB_L          1
157
158#elif defined(mcpu32)
159 
160#define CPU_MODEL_NAME         "mcpu32"
161#define M68K_HAS_VBR             1
162#define M68K_HAS_SEPARATE_STACKS 0
163#define M68K_HAS_FPU             0
164#define M68K_HAS_BFFFO           0
165#define M68K_HAS_PREINDEXING     1
166#define M68K_HAS_EXTB_L          1
167
168#else
169
170#error "Unsupported CPU Model"
171
172#endif
173
174/*
175 *  Define the name of the CPU family.
176 */
177
178#define CPU_NAME "Motorola MC68xxx"
179
180#ifndef ASM
181
182#define m68k_disable_interrupts( _level ) \
183  asm volatile ( "movew   %%sr,%0\n\t" \
184                 "orw     #0x0700,%%sr" \
185                    : "=d" (_level))
186
187#define m68k_enable_interrupts( _level ) \
188  asm volatile ( "movew   %0,%%sr " : : "d" (_level));
189
190#define m68k_flash_interrupts( _level ) \
191  asm volatile ( "movew   %0,%%sr\n\t" \
192                 "orw     #0x0700,%%sr" \
193                    : : "d" (_level))
194
195#define m68k_get_interrupt_level( _level ) \
196  do { \
197    register unsigned32 _tmpsr; \
198    \
199    asm volatile( "movw  %%sr,%0" : "=d" (_tmpsr)); \
200    _level = (_tmpsr & 0x0700) >> 8; \
201  } while (0)
202   
203#define m68k_set_interrupt_level( _newlevel ) \
204  do { \
205    register unsigned32 _tmpsr; \
206    \
207    asm volatile( "movw  %%sr,%0" : "=d" (_tmpsr)); \
208    _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
209    asm volatile( "movw  %0,%%sr" : : "d" (_tmpsr)); \
210  } while (0)
211
212#if ( M68K_HAS_VBR == 1 )
213#define m68k_get_vbr( vbr ) \
214  asm volatile ( "movec   %%vbr,%0 " : "=r" (vbr))
215
216#define m68k_set_vbr( vbr ) \
217  asm volatile ( "movec   %0,%%vbr " : : "r" (vbr))
218#else
219#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
220#define m68k_set_vbr( _vbr )
221#endif
222
223/*
224 *  The following routine swaps the endian format of an unsigned int.
225 *  It must be static because it is referenced indirectly.
226 */
227
228static inline unsigned int m68k_swap_u32(
229  unsigned int value
230)
231{
232  unsigned int swapped = value;
233
234  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
235  asm volatile( "swap  %0"    : "=d" (swapped) : "0" (swapped) );
236  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
237
238  return( swapped );
239}
240
241/* XXX this is only valid for some m68k family members and should be fixed */
242
243#define m68k_enable_caching() \
244  { register unsigned32 _ctl=0x01; \
245    asm volatile ( "movec   %0,%%cacr" \
246                       : "=d" (_ctl) : "0" (_ctl) ); \
247  }
248
249#define CPU_swap_u32( value )  m68k_swap_u32( value )
250
251#ifdef __cplusplus
252}
253#endif
254
255#endif  /* !ASM */
256
257#endif
258/* end of include file */
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