source: rtems/c/src/exec/score/cpu/m68k/m68k.h @ 3a4ae6c

4.104.114.84.95
Last change on this file since 3a4ae6c was 3a4ae6c, checked in by Joel Sherrill <joel.sherrill@…>, on 09/11/95 at 19:35:39

The word "RTEMS" almost completely removed from the core.

Configuration Table Template file added and all tests
modified to use this. All gvar.h and conftbl.h files
removed from test directories.

Configuration parameter maximum_devices added.

Core semaphore and mutex handlers added and RTEMS API Semaphore
Manager updated to reflect this.

Initialization sequence changed to invoke API specific initialization
routines. Initialization tasks table now owned by RTEMS Tasks Manager.

Added user extension for post-switch.

Utilized user extensions to implement API specific functionality
like signal dispatching.

Added extensions to the System Initialization Thread so that an
API can register a function to be invoked while the system
is being initialized. These are largely equivalent to the
pre-driver and post-driver hooks.

Added the Modules file oar-go32_p5, modified oar-go32, and modified
the file make/custom/go32.cfg to look at an environment varable which
determines what CPU model is being used.

All BSPs updated to reflect named devices and clock driver's IOCTL
used by the Shared Memory Driver. Also merged clock isr into
main file and removed ckisr.c where possible.

Updated spsize to reflect new and moved variables.

Makefiles for the executive source and include files updated to show
break down of files into Core, RTEMS API, and Neither.

Header and inline files installed into subdirectory based on whether
logically in the Core or a part of the RTEMS API.

  • Property mode set to 100644
File size: 7.2 KB
Line 
1/*  m68k.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __M68k_h
18#define __M68k_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  The following define the CPU Family and Model within the family
26 *
27 *  NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
28 *        with the name of the appropriate macro for this target CPU.
29 */
30 
31#ifdef m68k
32#undef m68k
33#endif
34#define m68k
35
36#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
37#undef REPLACE_THIS_WITH_THE_CPU_MODEL
38#endif
39#define REPLACE_THIS_WITH_THE_CPU_MODEL
40
41#ifdef REPLACE_THIS_WITH_THE_BSP
42#undef REPLACE_THIS_WITH_THE_BSP
43#endif
44#define REPLACE_THIS_WITH_THE_BSP
45
46/*
47 *  This section contains the information required to build
48 *  RTEMS for a particular member of the Motorola MC68xxx
49 *  family.  It does this by setting variables to indicate
50 *  which implementation dependent features are present in
51 *  a particular member of the family.
52 *
53 *  Currently recognized:
54 *     m68000        (no FP)
55 *     m68020        (implies FP)
56 *     m68020_nofp   (no FP)
57 *     m68030        (implies FP)
58 *     m68040        (implies FP)
59 *     m68lc040      (no FP)
60 *     m68ec040      (no FP)
61 *
62 *  Primary difference (for RTEMS) between m68040, m680lc040, and
63 *  m68ec040 is the presence or abscense of the FPU.
64 *
65 *  Here is some information on the 040 variants (courtesy of Doug McBride,
66 *  mcbride@rodin.colorado.edu):
67 *
68 *    "The 68040 is a superset of the 68EC040 and the 68LC040.  The
69 *    68EC040 and 68LC040 do not have FPU's.  The 68LC040 and the
70 *    68EC040 have renamed the DLE pin as JS0 which must be tied to
71 *    Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1.  The
72 *    68EC040 has access control units instead of memory management units.
73 *    The 68EC040 should not have the PFLUSH or PTEST instructions executed
74 *    (cause an indeterminate result).  The 68EC040 and 68LC040 do not
75 *    implement the DLE or multiplexed bus modes.  The 68EC040 does not
76 *    implement the output buffer impedance selection mode of operation."
77 */
78 
79#if defined(m68000)
80 
81#define RTEMS_MODEL_NAME         "m68000"
82#define M68K_HAS_VBR             0
83#define M68K_HAS_SEPARATE_STACKS 0
84#define M68K_HAS_FPU             0
85#define M68K_HAS_BFFFO           0
86#define M68K_HAS_PREINDEXING     0
87
88#elif defined(m68020)
89 
90#define RTEMS_MODEL_NAME         "m68020"
91#define M68K_HAS_VBR             1
92#define M68K_HAS_SEPARATE_STACKS 1
93#define M68K_HAS_FPU             1
94#define M68K_HAS_BFFFO           1
95#define M68K_HAS_PREINDEXING     1
96 
97#elif defined(m68020_nofp)
98 
99#define RTEMS_MODEL_NAME         "m68020 w/o fp"
100#define M68K_HAS_VBR             1
101#define M68K_HAS_SEPARATE_STACKS 1
102#define M68K_HAS_FPU             0
103#define M68K_HAS_BFFFO           1
104#define M68K_HAS_PREINDEXING     1
105 
106#elif defined(m68030)
107 
108#define RTEMS_MODEL_NAME         "m68030"
109#define M68K_HAS_VBR             1
110#define M68K_HAS_SEPARATE_STACKS 1
111#define M68K_HAS_FPU             1
112#define M68K_HAS_BFFFO           1
113#define M68K_HAS_PREINDEXING     1
114 
115#elif defined(m68040)
116
117#define RTEMS_MODEL_NAME         "m68040"
118#define M68K_HAS_VBR             1
119#define M68K_HAS_SEPARATE_STACKS 1
120#define M68K_HAS_FPU             1
121#define M68K_HAS_BFFFO           1
122#define M68K_HAS_PREINDEXING     1
123 
124#elif defined(m68lc040)
125
126#define RTEMS_MODEL_NAME         "m68lc040"
127#define M68K_HAS_VBR             1
128#define M68K_HAS_SEPARATE_STACKS 1
129#define M68K_HAS_FPU             0
130#define M68K_HAS_BFFFO           1
131#define M68K_HAS_PREINDEXING     1
132 
133#elif defined(m68ec040)
134
135#define RTEMS_MODEL_NAME         "m68ec040"
136#define M68K_HAS_VBR             1
137#define M68K_HAS_SEPARATE_STACKS 1
138#define M68K_HAS_FPU             0
139#define M68K_HAS_BFFFO           1
140#define M68K_HAS_PREINDEXING     1
141
142#else
143
144#error "Unsupported CPU Model"
145
146#endif
147
148/*
149 *  If defined, this causes some of the macros to initialize their
150 *  variables to zero before doing inline assembly.  This gets rid
151 *  of compile time warnings at the cost of a little execution time
152 *  in some time critical routines.
153 */
154
155#define NO_UNINITIALIZED_WARNINGS
156
157/*
158 *  Define the name of the CPU family.
159 */
160
161#define CPU_NAME "Motorola MC68xxx"
162
163#ifndef ASM
164
165#ifdef NO_UNINITIALIZED_WARNINGS
166#define m68k_disable_interrupts( _level ) \
167  { \
168    (_level) = 0;  /* avoids warnings */ \
169    asm volatile ( "movew   %%sr,%0 ; \
170                    orw     #0x0700,%%sr" \
171                    : "=d" ((_level)) : "0" ((_level)) \
172    ); \
173  }
174#else
175#define m68k_disable_interrupts( _level ) \
176  { \
177    asm volatile ( "movew   %%sr,%0 ; \
178                    orw     #0x0700,%%sr" \
179                    : "=d" ((_level)) : "0" ((_level)) \
180    ); \
181  }
182#endif
183
184#define m68k_enable_interrupts( _level ) \
185  { \
186    asm volatile ( "movew   %0,%%sr " \
187                   : "=d" ((_level)) : "0" ((_level)) \
188    ); \
189  }
190
191#define m68k_flash_interrupts( _level ) \
192  { \
193    asm volatile ( "movew   %0,%%sr ; \
194                    orw     #0x0700,%%sr" \
195                    : "=d" ((_level)) : "0" ((_level)) \
196    ); \
197  }
198
199#define m68k_get_interrupt_level( _level ) \
200  do { \
201    register unsigned32 _tmpsr = 0; \
202    \
203    asm volatile( "movw  %%sr,%0" \
204                   : "=d" (_tmpsr) : "0" (_tmpsr) \
205    ); \
206    \
207    _level = (_tmpsr & 0x0700) >> 8; \
208  } while (0)
209   
210#define m68k_set_interrupt_level( _newlevel ) \
211  { \
212    register unsigned32 _tmpsr = 0; \
213    \
214    asm volatile( "movw  %%sr,%0" \
215                   : "=d" (_tmpsr) : "0" (_tmpsr) \
216    ); \
217    \
218    _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
219    \
220    asm volatile( "movw  %0,%%sr" \
221                   : "=d" (_tmpsr) : "0" (_tmpsr) \
222    ); \
223  }
224
225#if ( M68K_HAS_VBR == 1 )
226#define m68k_get_vbr( vbr ) \
227  { (vbr) = 0; \
228    asm volatile ( "movec   %%vbr,%0 " \
229                       : "=r" (vbr) : "0" (vbr) ); \
230  }
231
232#define m68k_set_vbr( vbr ) \
233  { register m68k_isr *_vbr= (m68k_isr *)(vbr); \
234    asm volatile ( "movec   %0,%%vbr " \
235                       : "=a" (_vbr) : "0" (_vbr) ); \
236  }
237#else
238#define m68k_get_vbr( _vbr ) _vbr = 0
239#define m68k_set_vbr( _vbr )
240#endif
241
242/*
243 *  The following routine swaps the endian format of an unsigned int.
244 *  It must be static because it is referenced indirectly.
245 */
246
247static inline unsigned int m68k_swap_u32(
248  unsigned int value
249)
250{
251  unsigned int swapped = value;
252
253  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
254  asm volatile( "swap  %0"    : "=d" (swapped) : "0" (swapped) );
255  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
256
257  return( swapped );
258}
259
260/* XXX this is only valid for some m68k family members and should be fixed */
261
262#define m68k_enable_caching() \
263  { register unsigned32 _ctl=0x01; \
264    asm volatile ( "movec   %0,%%cacr" \
265                       : "=d" (_ctl) : "0" (_ctl) ); \
266  }
267
268#define CPU_swap_u32( value )  m68k_swap_u32( value )
269
270#ifdef __cplusplus
271}
272#endif
273
274#endif  /* !ASM */
275
276#endif
277/* end of include file */
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