source: rtems/c/src/exec/score/cpu/m68k/m68k.h @ 26e5cd4

4.104.114.84.95
Last change on this file since 26e5cd4 was 26e5cd4, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 13, 1998 at 2:23:37 PM

Patch from Chris Johns <ccj@…>. Comments follow:

Here is a small patch which allows the m68060 to be used. I have not
tested the FP switching stuff which we know is broken. This is taken
against the libchip snapshot but should merge without problems. If you
have any problems please let me know.

There are other smaller issues such as superscalar enable and cache
control which I have not addressed yet. They are different to all other
m68k processors. These can wait IMO.

  • Property mode set to 100644
File size: 10.5 KB
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1/*  m68k.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __M68k_h
18#define __M68k_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  This section contains the information required to build
26 *  RTEMS for a particular member of the Motorola MC68xxx
27 *  family.  It does this by setting variables to indicate
28 *  which implementation dependent features are present in
29 *  a particular member of the family.
30 *
31 *  Currently recognized:
32 *     -m68000
33 *     -m68000 -msoft-float
34 *     -m68020
35 *     -m68020 -msoft-float
36 *     -m68030
37 *     -m68040 -msoft-float
38 *     -m68040
39 *     -m68040 -msoft-float
40 *     -m68060
41 *     -m68060 -msoft-float
42 *     -m68302        (no FP) (deprecated, use -m68000)
43 *     -m68332        (no FP) (deprecated, use -mcpu32)
44 *     -mcpu32        (no FP)
45 *     -m5200         (no FP)
46 *
47 *  As of gcc 2.8.1 and egcs 1.1, there is no distinction made between
48 *  the CPU32 and CPU32+.  The option -mcpu32 generates code which can
49 *  be run on either core.  RTEMS distinguishes between these two cores
50 *  because they have different alignment rules which impact performance.
51 *  If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should
52 *  be defined in your custom file (see make/custom/gen68360.cfg for an
53 *  example of how to do this.  If gcc ever distinguishes between these
54 *  two cores, then RTEMS__mcpu32p__ usage will be replaced with the
55 *  appropriate compiler defined predefine.
56 *
57 *  Here is some information on the 040 variants (courtesy of Doug McBride,
58 *  mcbride@rodin.colorado.edu):
59 *
60 *    "The 68040 is a superset of the 68EC040 and the 68LC040.  The
61 *    68EC040 and 68LC040 do not have FPU's.  The 68LC040 and the
62 *    68EC040 have renamed the DLE pin as JS0 which must be tied to
63 *    Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1.  The
64 *    68EC040 has access control units instead of memory management units.
65 *    The 68EC040 should not have the PFLUSH or PTEST instructions executed
66 *    (cause an indeterminate result).  The 68EC040 and 68LC040 do not
67 *    implement the DLE or multiplexed bus modes.  The 68EC040 does not
68 *    implement the output buffer impedance selection mode of operation."
69 *
70 *  M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
71 *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
72 *  68010, 68302, 68306, 68307).  This instruction is available on the 68020
73 *  up and the cpu32 based models. 
74 *
75 *  M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
76 *  data access (68020, 68030, 68040, 68060, CPU32+).
77 *
78 *  NOTE:
79 *    Eventually it would be nice to evaluate doing a lot of this section
80 *    by having each model specify which core it uses and then go from there.
81 */
82
83#if defined(__mc68020__)
84 
85#define CPU_MODEL_NAME          "m68020"
86#define M68K_HAS_VBR             1
87#define M68K_HAS_SEPARATE_STACKS 1
88#define M68K_HAS_BFFFO           1
89#define M68K_HAS_PREINDEXING     1
90#define M68K_HAS_EXTB_L          1
91#define M68K_HAS_MISALIGNED      1
92# if defined (__HAVE_68881__)
93# define M68K_HAS_FPU            1
94# define M68K_HAS_FPSP_PACKAGE   0
95# else
96# define M68K_HAS_FPU            0
97# define M68K_HAS_FPSP_PACKAGE   0
98# endif
99 
100#elif defined(__mc68030__)
101 
102#define CPU_MODEL_NAME          "m68030"
103#define M68K_HAS_VBR             1
104#define M68K_HAS_SEPARATE_STACKS 1
105#define M68K_HAS_BFFFO           1
106#define M68K_HAS_PREINDEXING     1
107#define M68K_HAS_EXTB_L          1
108#define M68K_HAS_MISALIGNED      1
109# if defined (__HAVE_68881__)
110# define M68K_HAS_FPU            1
111# define M68K_HAS_FPSP_PACKAGE   0
112# else
113# define M68K_HAS_FPU            0
114# define M68K_HAS_FPSP_PACKAGE   0
115# endif
116 
117#elif defined(__mc68040__)
118
119#define CPU_MODEL_NAME          "m68040"
120#define M68K_HAS_VBR             1
121#define M68K_HAS_SEPARATE_STACKS 1
122#define M68K_HAS_BFFFO           1
123#define M68K_HAS_PREINDEXING     1
124#define M68K_HAS_EXTB_L          1
125#define M68K_HAS_MISALIGNED      1
126# if defined (__HAVE_68881__)
127# define M68K_HAS_FPU            1
128# define M68K_HAS_FPSP_PACKAGE   1
129# else
130# define M68K_HAS_FPU            0
131# define M68K_HAS_FPSP_PACKAGE   0
132# endif
133 
134#elif defined(__mc68060__)
135
136#define CPU_MODEL_NAME          "m68060"
137#define M68K_HAS_VBR             1
138#define M68K_HAS_SEPARATE_STACKS 0
139#define M68K_HAS_BFFFO           1
140#define M68K_HAS_PREINDEXING     1
141#define M68K_HAS_EXTB_L          1
142#define M68K_HAS_MISALIGNED      1
143# if defined (__HAVE_68881__)
144# define M68K_HAS_FPU            1
145# define M68K_HAS_FPSP_PACKAGE   1
146# else
147# define M68K_HAS_FPU            0
148# define M68K_HAS_FPSP_PACKAGE   0
149# endif
150 
151#elif defined(__mc68302__)
152#define CPU_MODEL_NAME          "m68302"
153#define M68K_HAS_VBR             0
154#define M68K_HAS_SEPARATE_STACKS 0
155#define M68K_HAS_BFFFO           0
156#define M68K_HAS_PREINDEXING     0
157#define M68K_HAS_EXTB_L          0
158#define M68K_HAS_MISALIGNED      0
159#define M68K_HAS_FPU             0
160#define M68K_HAS_FPSP_PACKAGE    0
161
162  /* gcc and egcs do not distinguish between CPU32 and CPU32+ */
163#elif defined(RTEMS__mcpu32p__)
164 
165#define CPU_MODEL_NAME          "mcpu32+"
166#define M68K_HAS_VBR             1
167#define M68K_HAS_SEPARATE_STACKS 0
168#define M68K_HAS_BFFFO           0
169#define M68K_HAS_PREINDEXING     1
170#define M68K_HAS_EXTB_L          1
171#define M68K_HAS_MISALIGNED      1
172#define M68K_HAS_FPU             0
173#define M68K_HAS_FPSP_PACKAGE    0
174
175#elif defined(__mcpu32__)
176 
177#define CPU_MODEL_NAME          "mcpu32"
178#define M68K_HAS_VBR             1
179#define M68K_HAS_SEPARATE_STACKS 0
180#define M68K_HAS_BFFFO           0
181#define M68K_HAS_PREINDEXING     1
182#define M68K_HAS_EXTB_L          1
183#define M68K_HAS_MISALIGNED      0
184#define M68K_HAS_FPU             0
185#define M68K_HAS_FPSP_PACKAGE    0
186
187#elif defined(__mcf5200__)
188/* Motorola ColdFire V2 core - RISC/68020 hybrid */ 
189#define CPU_MODEL_NAME         "m5200"
190#define M68K_HAS_VBR             1
191#define M68K_HAS_BFFFO           0
192#define M68K_HAS_SEPARATE_STACKS 0
193#define M68K_HAS_PREINDEXING     0
194#define M68K_HAS_EXTB_L          1
195#define M68K_HAS_MISALIGNED      1
196#define M68K_HAS_FPU             0
197#define M68K_HAS_FPSP_PACKAGE    0
198#define M68K_COLDFIRE_ARCH       1
199
200#elif defined(__mc68000__)
201 
202#define CPU_MODEL_NAME          "m68000"
203#define M68K_HAS_VBR             0
204#define M68K_HAS_SEPARATE_STACKS 0
205#define M68K_HAS_BFFFO           0
206#define M68K_HAS_PREINDEXING     0
207#define M68K_HAS_EXTB_L          0
208#define M68K_HAS_MISALIGNED      0
209# if defined (__HAVE_68881__)
210# define M68K_HAS_FPU            1
211# define M68K_HAS_FPSP_PACKAGE   0
212# else
213# define M68K_HAS_FPU            0
214# define M68K_HAS_FPSP_PACKAGE   0
215# endif
216
217#else
218
219#error "Unsupported CPU model -- are you sure you're running a 68k compiler?"
220
221#endif
222
223/*
224 *  If the above did not specify a ColdFire architecture, then set
225 *  this flag to indicate that it is not a ColdFire CPU.
226 */
227
228#if !defined(M68K_COLDFIRE_ARCH)
229#define M68K_COLDFIRE_ARCH       0
230#endif
231
232/*
233 *  Define the name of the CPU family.
234 */
235
236#if ( M68K_COLDFIRE_ARCH == 1 )
237  #define CPU_NAME "Motorola ColdFire"
238#else
239  #define CPU_NAME "Motorola MC68xxx"
240#endif
241
242#ifndef ASM
243
244#if ( M68K_COLDFIRE_ARCH == 1 )
245#define m68k_disable_interrupts( _level ) \
246   do { register unsigned32 _tmpsr = 0x0700; \
247        asm volatile ( "move.w %%sr,%0\n\t" \
248                       "or.l   %0,%1\n\t" \
249                       "move.w %1,%%sr" \
250                       : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) ); \
251   } while( 0 )
252#else
253#define m68k_disable_interrupts( _level ) \
254  asm volatile ( "move.w  %%sr,%0\n\t" \
255                 "or.w    #0x0700,%%sr" \
256                    : "=d" (_level))
257#endif
258
259#define m68k_enable_interrupts( _level ) \
260  asm volatile ( "move.w  %0,%%sr " : : "d" (_level));
261
262#if ( M68K_COLDFIRE_ARCH == 1 )
263#define m68k_flash_interrupts( _level ) \
264   do { register unsigned32 _tmpsr = 0x0700; \
265        asm volatile ( "move.w %2,%%sr\n\t" \
266                       "or.l   %2,%1\n\t" \
267                       "move.w %1,%%sr" \
268                       : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) ); \
269   } while( 0 )
270#else
271#define m68k_flash_interrupts( _level ) \
272  asm volatile ( "move.w  %0,%%sr\n\t" \
273                 "or.w    #0x0700,%%sr" \
274                    : : "d" (_level))
275#endif
276
277#define m68k_get_interrupt_level( _level ) \
278  do { \
279    register unsigned32 _tmpsr; \
280    \
281    asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
282    _level = (_tmpsr & 0x0700) >> 8; \
283  } while (0)
284   
285#define m68k_set_interrupt_level( _newlevel ) \
286  do { \
287    register unsigned32 _tmpsr; \
288    \
289    asm volatile( "move.w  %%sr,%0" : "=d" (_tmpsr)); \
290    _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
291    asm volatile( "move.w  %0,%%sr" : : "d" (_tmpsr)); \
292  } while (0)
293
294#if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 )
295#define m68k_get_vbr( vbr ) \
296  asm volatile ( "movec   %%vbr,%0 " : "=r" (vbr))
297
298#define m68k_set_vbr( vbr ) \
299  asm volatile ( "movec   %0,%%vbr " : : "r" (vbr))
300
301#elif ( M68K_COLDFIRE_ARCH == 1 )
302#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
303
304#define m68k_set_vbr( _vbr ) \
305    asm volatile ("move.l  %%a7,%%d1 \n\t" \
306                  "move.l  %0,%%a7\n\t"    \
307                  "movec   %%a7,%%vbr\n\t" \
308                  "move.l  %%d1,%%a7\n\t"  \
309                  : : "d" (_vbr) : "d1" );
310 
311#else
312#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
313#define m68k_set_vbr( _vbr )
314#endif
315
316/*
317 *  The following routine swaps the endian format of an unsigned int.
318 *  It must be static because it is referenced indirectly.
319 */
320
321static inline unsigned int m68k_swap_u32(
322  unsigned int value
323)
324{
325  unsigned int swapped = value;
326
327  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
328  asm volatile( "swap  %0"    : "=d" (swapped) : "0" (swapped) );
329  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
330
331  return( swapped );
332}
333
334static inline unsigned int m68k_swap_u16(
335  unsigned int value
336)
337{
338  unsigned short swapped = value;
339
340  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
341
342  return( swapped );
343}
344
345/* XXX this is only valid for some m68k family members and should be fixed */
346
347#define m68k_enable_caching() \
348  { register unsigned32 _ctl=0x01; \
349    asm volatile ( "movec   %0,%%cacr" \
350                       : "=d" (_ctl) : "0" (_ctl) ); \
351  }
352
353#define CPU_swap_u32( value )  m68k_swap_u32( value )
354#define CPU_swap_u16( value )  m68k_swap_u16( value )
355
356#endif  /* !ASM */
357
358#ifdef __cplusplus
359}
360#endif
361
362#endif
363/* end of include file */
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