source: rtems/c/src/exec/score/cpu/m68k/m68k.h @ 25804b60

4.104.114.84.9
Last change on this file since 25804b60 was 25804b60, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 20, 1998 at 5:38:53 PM

Patch from Eric Norum <eric@…>:

Here is my attempt at bringing m68k.h into line with the predefined
symbols provided by egcs-1.0.2-prerelease (with R. Kirkham's patch so
that -mcpu32, etc. implies -msoft-float).

  • Property mode set to 100644
File size: 7.4 KB
Line 
1/*  m68k.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __M68k_h
18#define __M68k_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  This section contains the information required to build
26 *  RTEMS for a particular member of the Motorola MC68xxx
27 *  family.  It does this by setting variables to indicate
28 *  which implementation dependent features are present in
29 *  a particular member of the family.
30 *
31 *  Currently recognized:
32 *     -m68000
33 *     -m68000 -msoft-float
34 *     -m68020
35 *     -m68020 -msoft-float
36 *     -m68030
37 *     -m68040 -msoft-float
38 *     -m68040
39 *     -m68040 -msoft-float
40 *     -m68302        (no FP)
41 *     -m68332        (no FP)
42 *     -mcpu32        (no FP)
43 *
44 *  Here is some information on the 040 variants (courtesy of Doug McBride,
45 *  mcbride@rodin.colorado.edu):
46 *
47 *    "The 68040 is a superset of the 68EC040 and the 68LC040.  The
48 *    68EC040 and 68LC040 do not have FPU's.  The 68LC040 and the
49 *    68EC040 have renamed the DLE pin as JS0 which must be tied to
50 *    Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1.  The
51 *    68EC040 has access control units instead of memory management units.
52 *    The 68EC040 should not have the PFLUSH or PTEST instructions executed
53 *    (cause an indeterminate result).  The 68EC040 and 68LC040 do not
54 *    implement the DLE or multiplexed bus modes.  The 68EC040 does not
55 *    implement the output buffer impedance selection mode of operation."
56 *
57 *  M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
58 *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
59 *  68010, 68302, 68306, 68307).  This instruction is available on the 68020
60 *  up and the cpu32 based models. 
61 *
62 *  M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
63 *  data access (68020, 68030, 68040, 68060, CPU32+).
64 *
65 *  NOTE:
66 *    Eventually it would be nice to evaluate doing a lot of this section
67 *    by having each model specify which core it uses and then go from there.
68 */
69
70#if defined(__mc68020__)
71 
72#define CPU_MODEL_NAME          "m68020"
73#define M68K_HAS_VBR             1
74#define M68K_HAS_SEPARATE_STACKS 1
75#define M68K_HAS_BFFFO           1
76#define M68K_HAS_PREINDEXING     1
77#define M68K_HAS_EXTB_L          1
78#define M68K_HAS_MISALIGNED      1
79# if defined (__HAVE_68881__)
80# define M68K_HAS_FPU            1
81# define M68K_HAS_FPSP_PACKAGE   0
82# else
83# define M68K_HAS_FPU            0
84# define M68K_HAS_FPSP_PACKAGE   0
85# endif
86 
87#elif defined(__mc68030__)
88 
89#define CPU_MODEL_NAME          "m68030"
90#define M68K_HAS_VBR             1
91#define M68K_HAS_SEPARATE_STACKS 1
92#define M68K_HAS_BFFFO           1
93#define M68K_HAS_PREINDEXING     1
94#define M68K_HAS_EXTB_L          1
95#define M68K_HAS_MISALIGNED      1
96# if defined (__HAVE_68881__)
97# define M68K_HAS_FPU            1
98# define M68K_HAS_FPSP_PACKAGE   0
99# else
100# define M68K_HAS_FPU            0
101# define M68K_HAS_FPSP_PACKAGE   0
102# endif
103 
104#elif defined(__mc68040__)
105
106#define CPU_MODEL_NAME          "m68040"
107#define M68K_HAS_VBR             1
108#define M68K_HAS_SEPARATE_STACKS 1
109#define M68K_HAS_BFFFO           1
110#define M68K_HAS_PREINDEXING     1
111#define M68K_HAS_EXTB_L          1
112#define M68K_HAS_MISALIGNED      1
113# if defined (__HAVE_68881__)
114# define M68K_HAS_FPU            1
115# define M68K_HAS_FPSP_PACKAGE   1
116# else
117# define M68K_HAS_FPU            0
118# define M68K_HAS_FPSP_PACKAGE   0
119# endif
120 
121#elif defined(__mc68302__)
122#define CPU_MODEL_NAME          "m68302"
123#define M68K_HAS_VBR             0
124#define M68K_HAS_SEPARATE_STACKS 0
125#define M68K_HAS_BFFFO           0
126#define M68K_HAS_PREINDEXING     0
127#define M68K_HAS_EXTB_L          0
128#define M68K_HAS_MISALIGNED      0
129#define M68K_HAS_FPU             0
130#define M68K_HAS_FPSP_PACKAGE    0
131
132#elif defined(__mc68332__)
133 
134#define CPU_MODEL_NAME          "mcpu32"
135#define M68K_HAS_VBR             1
136#define M68K_HAS_SEPARATE_STACKS 0
137#define M68K_HAS_BFFFO           0
138#define M68K_HAS_PREINDEXING     1
139#define M68K_HAS_EXTB_L          1
140#define M68K_HAS_MISALIGNED      0
141#define M68K_HAS_FPU             0
142#define M68K_HAS_FPSP_PACKAGE    0
143
144#elif defined(__mcpu32__)
145 
146#define CPU_MODEL_NAME          "mcpu32+"
147#define M68K_HAS_VBR             1
148#define M68K_HAS_SEPARATE_STACKS 0
149#define M68K_HAS_BFFFO           0
150#define M68K_HAS_PREINDEXING     1
151#define M68K_HAS_EXTB_L          1
152#define M68K_HAS_MISALIGNED      1
153#define M68K_HAS_FPU             0
154#define M68K_HAS_FPSP_PACKAGE    0
155
156#elif defined(__mc68000__)
157 
158#define CPU_MODEL_NAME          "m68000"
159#define M68K_HAS_VBR             0
160#define M68K_HAS_SEPARATE_STACKS 0
161#define M68K_HAS_BFFFO           0
162#define M68K_HAS_PREINDEXING     0
163#define M68K_HAS_EXTB_L          0
164#define M68K_HAS_MISALIGNED      0
165# if defined (__HAVE_68881__)
166# define M68K_HAS_FPU            1
167# define M68K_HAS_FPSP_PACKAGE   0
168# else
169# define M68K_HAS_FPU            0
170# define M68K_HAS_FPSP_PACKAGE   0
171# endif
172
173#else
174
175#error "Unsupported CPU model -- are you sure you're running a 68k compiler?"
176
177#endif
178
179/*
180 *  Define the name of the CPU family.
181 */
182
183#define CPU_NAME "Motorola MC68xxx"
184
185#ifndef ASM
186
187#define m68k_disable_interrupts( _level ) \
188  asm volatile ( "movew   %%sr,%0\n\t" \
189                 "orw     #0x0700,%%sr" \
190                    : "=d" (_level))
191
192#define m68k_enable_interrupts( _level ) \
193  asm volatile ( "movew   %0,%%sr " : : "d" (_level));
194
195#define m68k_flash_interrupts( _level ) \
196  asm volatile ( "movew   %0,%%sr\n\t" \
197                 "orw     #0x0700,%%sr" \
198                    : : "d" (_level))
199
200#define m68k_get_interrupt_level( _level ) \
201  do { \
202    register unsigned32 _tmpsr; \
203    \
204    asm volatile( "movw  %%sr,%0" : "=d" (_tmpsr)); \
205    _level = (_tmpsr & 0x0700) >> 8; \
206  } while (0)
207   
208#define m68k_set_interrupt_level( _newlevel ) \
209  do { \
210    register unsigned32 _tmpsr; \
211    \
212    asm volatile( "movw  %%sr,%0" : "=d" (_tmpsr)); \
213    _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
214    asm volatile( "movw  %0,%%sr" : : "d" (_tmpsr)); \
215  } while (0)
216
217#if ( M68K_HAS_VBR == 1 )
218#define m68k_get_vbr( vbr ) \
219  asm volatile ( "movec   %%vbr,%0 " : "=r" (vbr))
220
221#define m68k_set_vbr( vbr ) \
222  asm volatile ( "movec   %0,%%vbr " : : "r" (vbr))
223#else
224#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
225#define m68k_set_vbr( _vbr )
226#endif
227
228/*
229 *  The following routine swaps the endian format of an unsigned int.
230 *  It must be static because it is referenced indirectly.
231 */
232
233static inline unsigned int m68k_swap_u32(
234  unsigned int value
235)
236{
237  unsigned int swapped = value;
238
239  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
240  asm volatile( "swap  %0"    : "=d" (swapped) : "0" (swapped) );
241  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
242
243  return( swapped );
244}
245
246/* XXX this is only valid for some m68k family members and should be fixed */
247
248#define m68k_enable_caching() \
249  { register unsigned32 _ctl=0x01; \
250    asm volatile ( "movec   %0,%%cacr" \
251                       : "=d" (_ctl) : "0" (_ctl) ); \
252  }
253
254#define CPU_swap_u32( value )  m68k_swap_u32( value )
255
256#endif  /* !ASM */
257
258#ifdef __cplusplus
259}
260#endif
261
262#endif
263/* end of include file */
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