[ac7d5ef0] | 1 | /* m68k.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the Motorola |
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| 4 | * m68xxx processor family. |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * All rights assigned to U.S. Government, 1994. |
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| 9 | * |
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| 10 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 11 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 12 | * notice must appear in all copies of this file and its derivatives. |
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| 13 | * |
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| 14 | * $Id$ |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef __M68k_h |
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| 18 | #define __M68k_h |
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| 19 | |
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| 20 | #ifdef __cplusplus |
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| 21 | extern "C" { |
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| 22 | #endif |
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| 23 | |
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| 24 | /* |
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| 25 | * This section contains the information required to build |
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| 26 | * RTEMS for a particular member of the Motorola MC68xxx |
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| 27 | * family. It does this by setting variables to indicate |
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| 28 | * which implementation dependent features are present in |
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| 29 | * a particular member of the family. |
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| 30 | * |
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| 31 | * Currently recognized: |
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| 32 | * m68000 (no FP) |
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| 33 | * m68020 (implies FP) |
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| 34 | * m68020_nofp (no FP) |
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| 35 | * m68030 (implies FP) |
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| 36 | * m68040 (implies FP) |
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| 37 | * m68lc040 (no FP) |
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| 38 | * m68ec040 (no FP) |
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[f398452] | 39 | * m68302 (no FP) |
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[dce1c1a1] | 40 | * mcpu32 (no FP) (includes m68360) |
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[ac7d5ef0] | 41 | * |
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| 42 | * Primary difference (for RTEMS) between m68040, m680lc040, and |
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[110f4ff7] | 43 | * m68ec040 is the presence or absence of the FPU. |
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[ac7d5ef0] | 44 | * |
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| 45 | * Here is some information on the 040 variants (courtesy of Doug McBride, |
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| 46 | * mcbride@rodin.colorado.edu): |
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| 47 | * |
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| 48 | * "The 68040 is a superset of the 68EC040 and the 68LC040. The |
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| 49 | * 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the |
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| 50 | * 68EC040 have renamed the DLE pin as JS0 which must be tied to |
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| 51 | * Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The |
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| 52 | * 68EC040 has access control units instead of memory management units. |
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| 53 | * The 68EC040 should not have the PFLUSH or PTEST instructions executed |
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| 54 | * (cause an indeterminate result). The 68EC040 and 68LC040 do not |
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| 55 | * implement the DLE or multiplexed bus modes. The 68EC040 does not |
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| 56 | * implement the output buffer impedance selection mode of operation." |
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[9a1ccb3] | 57 | * |
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| 58 | * M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction |
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| 59 | * which is not available for 68000 or 68ec000 cores (68000, 68001, 68008, |
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| 60 | * 68010, 68302, 68306, 68307). This instruction is available on the 68020 |
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| 61 | * up and the cpu32 based models. |
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| 62 | * |
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| 63 | * NOTE: |
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| 64 | * Eventually it would be nice to evaluate doing a lot of this section |
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| 65 | * by having each model specigy which core it uses and then go from there. |
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[ac7d5ef0] | 66 | */ |
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[9a1ccb3] | 67 | |
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[ac7d5ef0] | 68 | #if defined(m68000) |
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| 69 | |
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[5e9b32b] | 70 | #define CPU_MODEL_NAME "m68000" |
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[ac7d5ef0] | 71 | #define M68K_HAS_VBR 0 |
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| 72 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 73 | #define M68K_HAS_FPU 0 |
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| 74 | #define M68K_HAS_BFFFO 0 |
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| 75 | #define M68K_HAS_PREINDEXING 0 |
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[9a1ccb3] | 76 | #define M68K_HAS_EXTB_L 0 |
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[ac7d5ef0] | 77 | |
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| 78 | #elif defined(m68020) |
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| 79 | |
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[5e9b32b] | 80 | #define CPU_MODEL_NAME "m68020" |
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[ac7d5ef0] | 81 | #define M68K_HAS_VBR 1 |
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| 82 | #define M68K_HAS_SEPARATE_STACKS 1 |
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| 83 | #define M68K_HAS_FPU 1 |
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| 84 | #define M68K_HAS_BFFFO 1 |
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| 85 | #define M68K_HAS_PREINDEXING 1 |
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[9a1ccb3] | 86 | #define M68K_HAS_EXTB_L 1 |
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[ac7d5ef0] | 87 | |
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| 88 | #elif defined(m68020_nofp) |
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| 89 | |
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[5e9b32b] | 90 | #define CPU_MODEL_NAME "m68020 w/o fp" |
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[ac7d5ef0] | 91 | #define M68K_HAS_VBR 1 |
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| 92 | #define M68K_HAS_SEPARATE_STACKS 1 |
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| 93 | #define M68K_HAS_FPU 0 |
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| 94 | #define M68K_HAS_BFFFO 1 |
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| 95 | #define M68K_HAS_PREINDEXING 1 |
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[9a1ccb3] | 96 | #define M68K_HAS_EXTB_L 1 |
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[ac7d5ef0] | 97 | |
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| 98 | #elif defined(m68030) |
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| 99 | |
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[5e9b32b] | 100 | #define CPU_MODEL_NAME "m68030" |
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[ac7d5ef0] | 101 | #define M68K_HAS_VBR 1 |
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| 102 | #define M68K_HAS_SEPARATE_STACKS 1 |
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| 103 | #define M68K_HAS_FPU 1 |
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| 104 | #define M68K_HAS_BFFFO 1 |
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| 105 | #define M68K_HAS_PREINDEXING 1 |
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[9a1ccb3] | 106 | #define M68K_HAS_EXTB_L 1 |
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[ac7d5ef0] | 107 | |
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| 108 | #elif defined(m68040) |
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| 109 | |
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[5e9b32b] | 110 | #define CPU_MODEL_NAME "m68040" |
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[ac7d5ef0] | 111 | #define M68K_HAS_VBR 1 |
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| 112 | #define M68K_HAS_SEPARATE_STACKS 1 |
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| 113 | #define M68K_HAS_FPU 1 |
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| 114 | #define M68K_HAS_BFFFO 1 |
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| 115 | #define M68K_HAS_PREINDEXING 1 |
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[9a1ccb3] | 116 | #define M68K_HAS_EXTB_L 1 |
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[ac7d5ef0] | 117 | |
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| 118 | #elif defined(m68lc040) |
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| 119 | |
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[5e9b32b] | 120 | #define CPU_MODEL_NAME "m68lc040" |
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[ac7d5ef0] | 121 | #define M68K_HAS_VBR 1 |
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| 122 | #define M68K_HAS_SEPARATE_STACKS 1 |
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| 123 | #define M68K_HAS_FPU 0 |
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| 124 | #define M68K_HAS_BFFFO 1 |
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| 125 | #define M68K_HAS_PREINDEXING 1 |
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[9a1ccb3] | 126 | #define M68K_HAS_EXTB_L 1 |
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[ac7d5ef0] | 127 | |
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| 128 | #elif defined(m68ec040) |
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| 129 | |
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[5e9b32b] | 130 | #define CPU_MODEL_NAME "m68ec040" |
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[ac7d5ef0] | 131 | #define M68K_HAS_VBR 1 |
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| 132 | #define M68K_HAS_SEPARATE_STACKS 1 |
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| 133 | #define M68K_HAS_FPU 0 |
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| 134 | #define M68K_HAS_BFFFO 1 |
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| 135 | #define M68K_HAS_PREINDEXING 1 |
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[9a1ccb3] | 136 | #define M68K_HAS_EXTB_L 1 |
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[ac7d5ef0] | 137 | |
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[f398452] | 138 | #elif defined(m68302) |
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| 139 | /* essentially a m68000 with onboard peripherals */ |
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| 140 | #define CPU_MODEL_NAME "m68302" |
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| 141 | #define M68K_HAS_VBR 0 |
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| 142 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 143 | #define M68K_HAS_FPU 0 |
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| 144 | #define M68K_HAS_BFFFO 0 |
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| 145 | #define M68K_HAS_PREINDEXING 0 |
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[9a1ccb3] | 146 | #define M68K_HAS_EXTB_L 0 |
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[f398452] | 147 | |
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[38ffa0c] | 148 | #elif defined(m68332) |
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| 149 | |
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[5e9b32b] | 150 | #define CPU_MODEL_NAME "m68332" |
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[38ffa0c] | 151 | #define M68K_HAS_VBR 1 |
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| 152 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 153 | #define M68K_HAS_FPU 0 |
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| 154 | #define M68K_HAS_BFFFO 0 |
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| 155 | #define M68K_HAS_PREINDEXING 0 |
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[9a1ccb3] | 156 | #define M68K_HAS_EXTB_L 1 |
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[38ffa0c] | 157 | |
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[dce1c1a1] | 158 | #elif defined(mcpu32) |
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[110f4ff7] | 159 | |
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[dce1c1a1] | 160 | #define CPU_MODEL_NAME "mcpu32" |
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[110f4ff7] | 161 | #define M68K_HAS_VBR 1 |
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| 162 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 163 | #define M68K_HAS_FPU 0 |
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| 164 | #define M68K_HAS_BFFFO 0 |
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| 165 | #define M68K_HAS_PREINDEXING 1 |
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[9a1ccb3] | 166 | #define M68K_HAS_EXTB_L 1 |
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[110f4ff7] | 167 | |
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[ac7d5ef0] | 168 | #else |
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| 169 | |
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| 170 | #error "Unsupported CPU Model" |
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| 171 | |
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| 172 | #endif |
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| 173 | |
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| 174 | /* |
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| 175 | * Define the name of the CPU family. |
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| 176 | */ |
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| 177 | |
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| 178 | #define CPU_NAME "Motorola MC68xxx" |
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| 179 | |
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| 180 | #ifndef ASM |
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| 181 | |
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| 182 | #define m68k_disable_interrupts( _level ) \ |
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[53fd6e2] | 183 | asm volatile ( "movew %%sr,%0\n\t" \ |
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| 184 | "orw #0x0700,%%sr" \ |
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| 185 | : "=d" (_level)) |
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[ac7d5ef0] | 186 | |
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| 187 | #define m68k_enable_interrupts( _level ) \ |
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[53fd6e2] | 188 | asm volatile ( "movew %0,%%sr " : : "d" (_level)); |
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[ac7d5ef0] | 189 | |
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| 190 | #define m68k_flash_interrupts( _level ) \ |
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[53fd6e2] | 191 | asm volatile ( "movew %0,%%sr\n\t" \ |
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| 192 | "orw #0x0700,%%sr" \ |
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| 193 | : : "d" (_level)) |
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[ac7d5ef0] | 194 | |
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[3a4ae6c] | 195 | #define m68k_get_interrupt_level( _level ) \ |
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| 196 | do { \ |
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[53fd6e2] | 197 | register unsigned32 _tmpsr; \ |
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[3a4ae6c] | 198 | \ |
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[53fd6e2] | 199 | asm volatile( "movw %%sr,%0" : "=d" (_tmpsr)); \ |
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[3a4ae6c] | 200 | _level = (_tmpsr & 0x0700) >> 8; \ |
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| 201 | } while (0) |
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| 202 | |
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[ac7d5ef0] | 203 | #define m68k_set_interrupt_level( _newlevel ) \ |
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[53fd6e2] | 204 | do { \ |
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| 205 | register unsigned32 _tmpsr; \ |
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[ac7d5ef0] | 206 | \ |
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[53fd6e2] | 207 | asm volatile( "movw %%sr,%0" : "=d" (_tmpsr)); \ |
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[ac7d5ef0] | 208 | _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \ |
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[53fd6e2] | 209 | asm volatile( "movw %0,%%sr" : : "d" (_tmpsr)); \ |
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| 210 | } while (0) |
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[ac7d5ef0] | 211 | |
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| 212 | #if ( M68K_HAS_VBR == 1 ) |
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| 213 | #define m68k_get_vbr( vbr ) \ |
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[53fd6e2] | 214 | asm volatile ( "movec %%vbr,%0 " : "=r" (vbr)) |
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[ac7d5ef0] | 215 | |
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| 216 | #define m68k_set_vbr( vbr ) \ |
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[53fd6e2] | 217 | asm volatile ( "movec %0,%%vbr " : : "r" (vbr)) |
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[ac7d5ef0] | 218 | #else |
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[38ffa0c] | 219 | #define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR |
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[ac7d5ef0] | 220 | #define m68k_set_vbr( _vbr ) |
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| 221 | #endif |
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| 222 | |
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| 223 | /* |
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| 224 | * The following routine swaps the endian format of an unsigned int. |
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| 225 | * It must be static because it is referenced indirectly. |
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| 226 | */ |
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| 227 | |
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| 228 | static inline unsigned int m68k_swap_u32( |
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| 229 | unsigned int value |
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| 230 | ) |
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| 231 | { |
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| 232 | unsigned int swapped = value; |
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| 233 | |
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| 234 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
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| 235 | asm volatile( "swap %0" : "=d" (swapped) : "0" (swapped) ); |
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| 236 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
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| 237 | |
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| 238 | return( swapped ); |
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| 239 | } |
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| 240 | |
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| 241 | /* XXX this is only valid for some m68k family members and should be fixed */ |
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| 242 | |
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| 243 | #define m68k_enable_caching() \ |
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| 244 | { register unsigned32 _ctl=0x01; \ |
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| 245 | asm volatile ( "movec %0,%%cacr" \ |
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| 246 | : "=d" (_ctl) : "0" (_ctl) ); \ |
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| 247 | } |
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| 248 | |
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| 249 | #define CPU_swap_u32( value ) m68k_swap_u32( value ) |
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| 250 | |
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| 251 | #ifdef __cplusplus |
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| 252 | } |
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| 253 | #endif |
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| 254 | |
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| 255 | #endif /* !ASM */ |
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| 256 | |
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| 257 | #endif |
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| 258 | /* end of include file */ |
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