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m68360.h @ 9a1ccb3

4.104.114.84.95

Last change on this file since 9a1ccb3 was 9a1ccb3, checked in by Joel Sherrill <joel.sherrill@…>, on 04/22/96 at 16:43:44

added stack allocation fields to the cpu table

added CPU_M68K_EXTB_L model flag

Property mode set to 100644

File size: 27.7 KB

Line
1	/*
2	**************************************************************************
3	**************************************************************************
4
5	MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC)
6
7	HARDWARE DECLARATIONS
8
9	**************************************************************************
10	**************************************************************************
11	*/
12
13	#ifndef __MC68360_h
14	#define __MC68360_h
15
16	/*
17	* $Revision$ $Date$ $Author$
18	*
19	* This program is free software; you can redistribute it and/or modify
20	* it under the terms of the GNU General Public License as published by
21	* the Free Software Foundation; either version 2 of the License, or
22	* (at your option) any later version.
23	*
24	* This program is distributed in the hope that it will be useful,
25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27	* GNU General Public License for more details.
28	*
29	* You should have received a copy of the GNU General Public License
30	* along with this program; if not, write to the Free Software
31	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32	*
33	* W. Eric Norum
34	* Saskatchewan Accelerator Laboratory
35	* University of Saskatchewan
36	* 107 North Road
37	* Saskatoon, Saskatchewan, CANADA
38	* S7N 5C6
39	*
40	* eric@skatter.usask.ca
41	*/
42
43	/*
44	*************************************************************************
45	* REGISTER SUBBLOCKS *
46	*************************************************************************
47	*/
48
49	/*
50	* Memory controller registers
51	*/
52	typedef struct m360MEMCRegisters_ {
53	rtems_unsigned32 br;
54	rtems_unsigned32 or;
55	rtems_unsigned32 _pad[2];
56	} m360MEMCRegisters_t;
57
58	/*
59	* Serial Communications Controller registers
60	*/
61	typedef struct m360SCCRegisters_ {
62	rtems_unsigned32 gsmr_l;
63	rtems_unsigned32 gsmr_h;
64	rtems_unsigned16 psmr;
65	rtems_unsigned16 _pad0;
66	rtems_unsigned16 todr;
67	rtems_unsigned16 dsr;
68	rtems_unsigned16 scce;
69	rtems_unsigned16 _pad1;
70	rtems_unsigned16 sccm;
71	rtems_unsigned8 _pad2;
72	rtems_unsigned8 sccs;
73	rtems_unsigned32 _pad3[2];
74	} m360SCCRegisters_t;
75
76	/*
77	* Serial Management Controller registers
78	*/
79	typedef struct m360SMCRegisters_ {
80	rtems_unsigned16 _pad0;
81	rtems_unsigned16 smcmr;
82	rtems_unsigned16 _pad1;
83	rtems_unsigned8 smce;
84	rtems_unsigned8 _pad2;
85	rtems_unsigned16 _pad3;
86	rtems_unsigned8 smcm;
87	rtems_unsigned8 _pad4;
88	rtems_unsigned32 _pad5;
89	} m360SMCRegisters_t;
90
91
92	/*
93	*************************************************************************
94	* Miscellaneous Parameters *
95	*************************************************************************
96	*/
97	typedef struct m360MiscParms_ {
98	rtems_unsigned16 rev_num;
99	rtems_unsigned16 _res1;
100	rtems_unsigned32 _res2;
101	rtems_unsigned32 _res3;
102	} m360MiscParms_t;
103
104	/*
105	*************************************************************************
106	* RISC Timers *
107	*************************************************************************
108	*/
109	typedef struct m360TimerParms_ {
110	rtems_unsigned16 tm_base;
111	rtems_unsigned16 _tm_ptr;
112	rtems_unsigned16 _r_tmr;
113	rtems_unsigned16 _r_tmv;
114	rtems_unsigned32 tm_cmd;
115	rtems_unsigned32 tm_cnt;
116	} m360TimerParms_t;
117
118	/*
119	* RISC Controller Configuration Register (RCCR)
120	* All other bits in this register are either reserved or
121	* used only with a Motorola-supplied RAM microcode packge.
122	*/
123	#define M360_RCCR_TIME (1<<15) /* Enable timer */
124	#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
125
126	/*
127	* Command register
128	* Set up this register before issuing a M360_CR_OP_SET_TIMER command.
129	*/
130	#define M360_TM_CMD_V (1<<31) /* Set to enable timer */
131	#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */
132	#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
133	#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
134
135	/*
136	*************************************************************************
137	* DMA Controllers *
138	*************************************************************************
139	*/
140	typedef struct m360IDMAparms_ {
141	rtems_unsigned16 ibase;
142	rtems_unsigned16 ibptr;
143	rtems_unsigned32 _istate;
144	rtems_unsigned32 _itemp;
145	} m360IDMAparms_t;
146
147	/*
148	*************************************************************************
149	* Serial Communication Controllers *
150	*************************************************************************
151	*/
152	typedef struct m360SCCparms_ {
153	rtems_unsigned16 rbase;
154	rtems_unsigned16 tbase;
155	rtems_unsigned8 rfcr;
156	rtems_unsigned8 tfcr;
157	rtems_unsigned16 mrblr;
158	rtems_unsigned32 _rstate;
159	rtems_unsigned32 _pad0;
160	rtems_unsigned16 _rbptr;
161	rtems_unsigned16 _pad1;
162	rtems_unsigned32 _pad2;
163	rtems_unsigned32 _tstate;
164	rtems_unsigned32 _pad3;
165	rtems_unsigned16 _tbptr;
166	rtems_unsigned16 _pad4;
167	rtems_unsigned32 _pad5;
168	rtems_unsigned32 _rcrc;
169	rtems_unsigned32 _tcrc;
170	union {
171	struct {
172	rtems_unsigned32 _res0;
173	rtems_unsigned32 _res1;
174	rtems_unsigned16 max_idl;
175	rtems_unsigned16 _idlc;
176	rtems_unsigned16 brkcr;
177	rtems_unsigned16 parec;
178	rtems_unsigned16 frmec;
179	rtems_unsigned16 nosec;
180	rtems_unsigned16 brkec;
181	rtems_unsigned16 brklen;
182	rtems_unsigned16 uaddr[2];
183	rtems_unsigned16 _rtemp;
184	rtems_unsigned16 toseq;
185	rtems_unsigned16 character[8];
186	rtems_unsigned16 rccm;
187	rtems_unsigned16 rccr;
188	rtems_unsigned16 rlbc;
189	} uart;
190	} un;
191	} m360SCCparms_t;
192
193	typedef struct m360SCCENparms_ {
194	rtems_unsigned16 rbase;
195	rtems_unsigned16 tbase;
196	rtems_unsigned8 rfcr;
197	rtems_unsigned8 tfcr;
198	rtems_unsigned16 mrblr;
199	rtems_unsigned32 _rstate;
200	rtems_unsigned32 _pad0;
201	rtems_unsigned16 _rbptr;
202	rtems_unsigned16 _pad1;
203	rtems_unsigned32 _pad2;
204	rtems_unsigned32 _tstate;
205	rtems_unsigned32 _pad3;
206	rtems_unsigned16 _tbptr;
207	rtems_unsigned16 _pad4;
208	rtems_unsigned32 _pad5;
209	rtems_unsigned32 _rcrc;
210	rtems_unsigned32 _tcrc;
211	union {
212	struct {
213	rtems_unsigned32 _res0;
214	rtems_unsigned32 _res1;
215	rtems_unsigned16 max_idl;
216	rtems_unsigned16 _idlc;
217	rtems_unsigned16 brkcr;
218	rtems_unsigned16 parec;
219	rtems_unsigned16 frmec;
220	rtems_unsigned16 nosec;
221	rtems_unsigned16 brkec;
222	rtems_unsigned16 brklen;
223	rtems_unsigned16 uaddr[2];
224	rtems_unsigned16 _rtemp;
225	rtems_unsigned16 toseq;
226	rtems_unsigned16 character[8];
227	rtems_unsigned16 rccm;
228	rtems_unsigned16 rccr;
229	rtems_unsigned16 rlbc;
230	} uart;
231	struct {
232	rtems_unsigned32 c_pres;
233	rtems_unsigned32 c_mask;
234	rtems_unsigned32 crcec;
235	rtems_unsigned32 alec;
236	rtems_unsigned32 disfc;
237	rtems_unsigned16 pads;
238	rtems_unsigned16 ret_lim;
239	rtems_unsigned16 _ret_cnt;
240	rtems_unsigned16 mflr;
241	rtems_unsigned16 minflr;
242	rtems_unsigned16 maxd1;
243	rtems_unsigned16 maxd2;
244	rtems_unsigned16 _maxd;
245	rtems_unsigned16 dma_cnt;
246	rtems_unsigned16 _max_b;
247	rtems_unsigned16 gaddr1;
248	rtems_unsigned16 gaddr2;
249	rtems_unsigned16 gaddr3;
250	rtems_unsigned16 gaddr4;
251	rtems_unsigned32 _tbuf0data0;
252	rtems_unsigned32 _tbuf0data1;
253	rtems_unsigned32 _tbuf0rba0;
254	rtems_unsigned32 _tbuf0crc;
255	rtems_unsigned16 _tbuf0bcnt;
256	rtems_unsigned16 paddr_h;
257	rtems_unsigned16 paddr_m;
258	rtems_unsigned16 paddr_l;
259	rtems_unsigned16 p_per;
260	rtems_unsigned16 _rfbd_ptr;
261	rtems_unsigned16 _tfbd_ptr;
262	rtems_unsigned16 _tlbd_ptr;
263	rtems_unsigned32 _tbuf1data0;
264	rtems_unsigned32 _tbuf1data1;
265	rtems_unsigned32 _tbuf1rba0;
266	rtems_unsigned32 _tbuf1crc;
267	rtems_unsigned16 _tbuf1bcnt;
268	rtems_unsigned16 _tx_len;
269	rtems_unsigned16 iaddr1;
270	rtems_unsigned16 iaddr2;
271	rtems_unsigned16 iaddr3;
272	rtems_unsigned16 iaddr4;
273	rtems_unsigned16 _boff_cnt;
274	rtems_unsigned16 taddr_l;
275	rtems_unsigned16 taddr_m;
276	rtems_unsigned16 taddr_h;
277	} ethernet;
278	} un;
279	} m360SCCENparms_t;
280
281	/*
282	* Receive and transmit function code register bits
283	* These apply to the function code registers of all devices, not just SCC.
284	*/
285	#define M360_RFCR_MOT (1<<4)
286	#define M360_RFCR_DMA_SPACE 0x8
287	#define M360_TFCR_MOT (1<<4)
288	#define M360_TFCR_DMA_SPACE 0x8
289
290	/*
291	*************************************************************************
292	* Serial Management Controllers *
293	*************************************************************************
294	*/
295	typedef struct m360SMCparms_ {
296	rtems_unsigned16 rbase;
297	rtems_unsigned16 tbase;
298	rtems_unsigned8 rfcr;
299	rtems_unsigned8 tfcr;
300	rtems_unsigned16 mrblr;
301	rtems_unsigned32 _rstate;
302	rtems_unsigned32 _pad0;
303	rtems_unsigned16 _rbptr;
304	rtems_unsigned16 _pad1;
305	rtems_unsigned32 _pad2;
306	rtems_unsigned32 _tstate;
307	rtems_unsigned32 _pad3;
308	rtems_unsigned16 _tbptr;
309	rtems_unsigned16 _pad4;
310	rtems_unsigned32 _pad5;
311	union {
312	struct {
313	rtems_unsigned16 max_idl;
314	rtems_unsigned16 _pad0;
315	rtems_unsigned16 brklen;
316	rtems_unsigned16 brkec;
317	rtems_unsigned16 brkcr;
318	rtems_unsigned16 _r_mask;
319	} uart;
320	struct {
321	rtems_unsigned16 _pad0[5];
322	} transparent;
323	} un;
324	} m360SMCparms_t;
325
326	/*
327	* Mode register
328	*/
329	#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */
330	#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */
331	#define M360_SMCMR_PARITY (1<<9) /* Enable parity */
332	#define M360_SMCMR_EVEN (1<<8) /* Even parity */
333	#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */
334	#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */
335	#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
336	#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
337	#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */
338	#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */
339	#define M360_SMCMR_REN (1<<0) /* Enable receiver */
340
341	/*
342	* Event and mask registers (SMCE, SMCM)
343	*/
344	#define M360_SMCE_BRK (1<<4)
345	#define M360_SMCE_BSY (1<<2)
346	#define M360_SMCE_TX (1<<1)
347	#define M360_SMCE_RX (1<<0)
348
349	/*
350	*************************************************************************
351	* Serial Peripheral Interface *
352	*************************************************************************
353	*/
354	typedef struct m360SPIparms_ {
355	rtems_unsigned16 rbase;
356	rtems_unsigned16 tbase;
357	rtems_unsigned8 rfcr;
358	rtems_unsigned8 tfcr;
359	rtems_unsigned16 mrblr;
360	rtems_unsigned32 _rstate;
361	rtems_unsigned32 _pad0;
362	rtems_unsigned16 _rbptr;
363	rtems_unsigned16 _pad1;
364	rtems_unsigned32 _pad2;
365	rtems_unsigned32 _tstate;
366	rtems_unsigned32 _pad3;
367	rtems_unsigned16 _tbptr;
368	rtems_unsigned16 _pad4;
369	rtems_unsigned32 _pad5;
370	} m360SPIparms_t;
371
372	/*
373	* Mode register (SPMODE)
374	*/
375	#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */
376	#define M360_SPMODE_CI (1<<13) /* Clock invert */
377	#define M360_SPMODE_CP (1<<12) /* Clock phase */
378	#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
379	#define M360_SPMODE_REV (1<<10) /* Reverse data */
380	#define M360_SPMODE_MASTER (1<<9) /* SPI is master */
381	#define M360_SPMODE_EN (1<<8) /* Enable SPI */
382	#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */
383	#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */
384
385	/*
386	* Mode register (SPCOM)
387	*/
388	#define M360_SPCOM_STR (1<<7) /* Start transmit */
389
390	/*
391	* Event and mask registers (SPIE, SPIM)
392	*/
393	#define M360_SPIE_MME (1<<5) /* Multi-master error */
394	#define M360_SPIE_TXE (1<<4) /* Tx error */
395	#define M360_SPIE_BSY (1<<2) /* Busy condition*/
396	#define M360_SPIE_TXB (1<<1) /* Tx buffer */
397	#define M360_SPIE_RXB (1<<0) /* Rx buffer */
398
399	/*
400	*************************************************************************
401	* SDMA (SCC, SMC, SPI) Buffer Descriptors *
402	*************************************************************************
403	*/
404	typedef struct m360BufferDescriptor_ {
405	rtems_unsigned16 status;
406	rtems_unsigned16 length;
407	volatile void *buffer;
408	} m360BufferDescriptor_t;
409
410	/*
411	* Bits in receive buffer descriptor status word
412	*/
413	#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
414	#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
415	#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
416	#define M360_BD_LAST (1<<11) /* Ethernet, SPI */
417	#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */
418	#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
419	#define M360_BD_ADDRESS (1<<10) /* SCC UART */
420	#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
421	#define M360_BD_MISS (1<<8) /* Ethernet */
422	#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */
423	#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
424	#define M360_BD_LONG (1<<5) /* Ethernet */
425	#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */
426	#define M360_BD_NONALIGNED (1<<4) /* Ethernet */
427	#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
428	#define M360_BD_SHORT (1<<3) /* Ethernet */
429	#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
430	#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */
431	#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
432	#define M360_BD_COLLISION (1<<0) /* Ethernet */
433	#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */
434	#define M360_BD_MASTER_ERROR (1<<0) /* SPI */
435
436	/*
437	* Bits in transmit buffer descriptor status word
438	* Many bits have the same meaning as those in receiver buffer descriptors.
439	*/
440	#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
441	#define M360_BD_PAD (1<<14) /* Ethernet */
442	#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */
443	#define M360_BD_TX_CRC (1<<10) /* Ethernet */
444	#define M360_BD_DEFER (1<<9) /* Ethernet */
445	#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */
446	#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
447	#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */
448	#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */
449	#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */
450	#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
451	#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
452	#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */
453	#define M360_BD_CTS_LOST (1<<0) /* SCC UART */
454
455	/*
456	*************************************************************************
457	* IDMA Buffer Descriptors *
458	*************************************************************************
459	*/
460	typedef struct m360IDMABufferDescriptor_ {
461	rtems_unsigned16 status;
462	rtems_unsigned16 _pad;
463	rtems_unsigned32 length;
464	void *source;
465	void *destination;
466	} m360IDMABufferDescriptor_t;
467
468	/*
469	*************************************************************************
470	* RISC Communication Processor Module Command Register (CR) *
471	*************************************************************************
472	*/
473	#define M360_CR_RST (1<<15) /* Reset communication processor */
474	#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
475	#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
476	#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
477	#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
478	#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
479	#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */
480	#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */
481	#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
482	#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
483	#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
484	#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */
485	#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
486	#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */
487	#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
488	#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */
489	#define M360_CR_CHAN_SCC2 (4<<4)
490	#define M360_CR_CHAN_SPI (5<<4)
491	#define M360_CR_CHAN_TIMER (5<<4)
492	#define M360_CR_CHAN_SCC3 (8<<4)
493	#define M360_CR_CHAN_SMC1 (9<<4)
494	#define M360_CR_CHAN_IDMA1 (9<<4)
495	#define M360_CR_CHAN_SCC4 (12<<4)
496	#define M360_CR_CHAN_SMC2 (13<<4)
497	#define M360_CR_CHAN_IDMA2 (13<<4)
498	#define M360_CR_FLG (1<<0) /* Command flag */
499
500	/*
501	*************************************************************************
502	* System Protection Control Register (SYPCR) *
503	*************************************************************************
504	*/
505	#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */
506	#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */
507	#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */
508	#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */
509	#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */
510	#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */
511	#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */
512	#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */
513
514	/*
515	*************************************************************************
516	* Memory Control Registers *
517	*************************************************************************
518	*/
519	#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */
520	#define M360_GMR_RFEN (1<<23) /* Refresh enable */
521	#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */
522	#define M360_GMR_PGS(x) ((x)<<18) /* Page size */
523	#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */
524	#define M360_GMR_DPS_16BIT (1<<16)
525	#define M360_GMR_DPS_8BIT (2<<16)
526	#define M360_GMR_DPS_DSACK (3<<16)
527	#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */
528	#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */
529	#define M360_GMR_SYNC (1<<13) /* Synchronous external access */
530	#define M360_GMR_EMWS (1<<12) /* External master wait state */
531	#define M360_GMR_OPAR (1<<11) /* Odd parity */
532	#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */
533	#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */
534	#define M360_GMR_NCS (1<<8) /* No CPU space */
535	#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */
536	#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */
537	#define M360_GMR_GAMX (1<<5) /* Global address mux enable */
538
539	#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */
540	#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */
541	#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */
542	#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */
543	#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */
544	#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */
545	#define M360_MEMC_BR_WP (1<<1) /* Write Protect */
546	#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */
547
548	#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */
549	#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1)
550	#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */
551	#define M360_MEMC_OR_4KB 0x0FFFF000
552	#define M360_MEMC_OR_8KB 0x0FFFE000
553	#define M360_MEMC_OR_16KB 0x0FFFC000
554	#define M360_MEMC_OR_32KB 0x0FFF8000
555	#define M360_MEMC_OR_64KB 0x0FFF0000
556	#define M360_MEMC_OR_128KB 0x0FFE0000
557	#define M360_MEMC_OR_256KB 0x0FFC0000
558	#define M360_MEMC_OR_512KB 0x0FF80000
559	#define M360_MEMC_OR_1MB 0x0FF00000
560	#define M360_MEMC_OR_2MB 0x0FE00000
561	#define M360_MEMC_OR_4MB 0x0FC00000
562	#define M360_MEMC_OR_8MB 0x0F800000
563	#define M360_MEMC_OR_16MB 0x0F000000
564	#define M360_MEMC_OR_32MB 0x0E000000
565	#define M360_MEMC_OR_64MB 0x0C000000
566	#define M360_MEMC_OR_128MB 0x08000000
567	#define M360_MEMC_OR_256MB 0x00000000
568	#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */
569	#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */
570	#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */
571	#define M360_MEMC_OR_32BIT (0<<1) /* Port size */
572	#define M360_MEMC_OR_16BIT (1<<1)
573	#define M360_MEMC_OR_8BIT (2<<1)
574	#define M360_MEMC_OR_DSACK (3<<1)
575	#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */
576
577	/*
578	*************************************************************************
579	* SI Mode Register (SIMODE) *
580	*************************************************************************
581	*/
582	#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
583	#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
584	#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
585	#define M360_SI_SMC2_BRG2 (1<<28)
586	#define M360_SI_SMC2_BRG3 (2<<28)
587	#define M360_SI_SMC2_BRG4 (3<<28)
588	#define M360_SI_SMC2_CLK5 (0<<28)
589	#define M360_SI_SMC2_CLK6 (1<<28)
590	#define M360_SI_SMC2_CLK7 (2<<28)
591	#define M360_SI_SMC2_CLK8 (3<<28)
592	#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
593	#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
594	#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
595	#define M360_SI_SMC1_BRG2 (1<<12)
596	#define M360_SI_SMC1_BRG3 (2<<12)
597	#define M360_SI_SMC1_BRG4 (3<<12)
598	#define M360_SI_SMC1_CLK1 (0<<12)
599	#define M360_SI_SMC1_CLK2 (1<<12)
600	#define M360_SI_SMC1_CLK3 (2<<12)
601	#define M360_SI_SMC1_CLK4 (3<<12)
602
603	/*
604	*************************************************************************
605	* SDMA Configuration Register (SDMA) *
606	*************************************************************************
607	*/
608	#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */
609	#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */
610	#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */
611	#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */
612	#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */
613
614	/*
615	*************************************************************************
616	* Baud (sic) Rate Generators *
617	*************************************************************************
618	*/
619	#define M360_BRG_RST (1<<17) /* Reset generator */
620	#define M360_BRG_EN (1<<16) /* Enable generator */
621	#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
622	#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
623	#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
624	#define M360_BRG_ATB (1<<13) /* Autobaud */
625	#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */
626	#define M360_BRG_57600 (26<<1)
627	#define M360_BRG_38400 (40<<1)
628	#define M360_BRG_19200 (80<<1)
629	#define M360_BRG_9600 (162<<1)
630	#define M360_BRG_4800 (324<<1)
631	#define M360_BRG_2400 (650<<1)
632	#define M360_BRG_1200 (1301<<1)
633	#define M360_BRG_600 (2603<<1)
634	#define M360_BRG_300 ((324<<1) \| 1)
635	#define M360_BRG_150 ((650<<1) \| 1)
636	#define M360_BRG_75 ((1301<<1) \| 1)
637
638	/*
639	*************************************************************************
640	* MC68360 DUAL-PORT RAM AND REGISTERS *
641	*************************************************************************
642	*/
643	typedef struct m360_ {
644	/*
645	* Dual-port RAM
646	*/
647	rtems_unsigned8 dpram0[0x400]; /* Microcode program */
648	rtems_unsigned8 dpram1[0x200];
649	rtems_unsigned8 dpram2[0x100]; /* Microcode scratch */
650	rtems_unsigned8 dpram3[0x100]; /* Not on REV A or B masks */
651	rtems_unsigned8 _rsv0[0xC00-0x800];
652	m360SCCENparms_t scc1p;
653	rtems_unsigned8 _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)];
654	m360MiscParms_t miscp;
655	rtems_unsigned8 _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)];
656	m360SCCparms_t scc2p;
657	rtems_unsigned8 _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)];
658	m360SPIparms_t spip;
659	rtems_unsigned8 _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)];
660	m360TimerParms_t tmp;
661	rtems_unsigned8 _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)];
662	m360SCCparms_t scc3p;
663	rtems_unsigned8 _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)];
664	m360IDMAparms_t idma1p;
665	rtems_unsigned8 _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)];
666	m360SMCparms_t smc1p;
667	rtems_unsigned8 _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)];
668	m360SCCparms_t scc4p;
669	rtems_unsigned8 _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)];
670	m360IDMAparms_t idma2p;
671	rtems_unsigned8 _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)];
672	m360SMCparms_t smc2p;
673	rtems_unsigned8 _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)];
674
675	/*
676	* SIM Block
677	*/
678	rtems_unsigned32 mcr;
679	rtems_unsigned32 _pad00;
680	rtems_unsigned8 avr;
681	rtems_unsigned8 rsr;
682	rtems_unsigned16 _pad01;
683	rtems_unsigned8 clkocr;
684	rtems_unsigned8 _pad02;
685	rtems_unsigned16 _pad03;
686	rtems_unsigned16 pllcr;
687	rtems_unsigned16 _pad04;
688	rtems_unsigned16 cdvcr;
689	rtems_unsigned16 pepar;
690	rtems_unsigned32 _pad05[2];
691	rtems_unsigned16 _pad06;
692	rtems_unsigned8 sypcr;
693	rtems_unsigned8 swiv;
694	rtems_unsigned16 _pad07;
695	rtems_unsigned16 picr;
696	rtems_unsigned16 _pad08;
697	rtems_unsigned16 pitr;
698	rtems_unsigned16 _pad09;
699	rtems_unsigned8 _pad10;
700	rtems_unsigned8 swsr;
701	rtems_unsigned32 bkar;
702	rtems_unsigned32 bcar;
703	rtems_unsigned32 _pad11[2];
704
705	/*
706	* MEMC Block
707	*/
708	rtems_unsigned32 gmr;
709	rtems_unsigned16 mstat;
710	rtems_unsigned16 _pad12;
711	rtems_unsigned32 _pad13[2];
712	m360MEMCRegisters_t memc[8];
713	rtems_unsigned8 _pad14[0xF0-0xD0];
714	rtems_unsigned8 _pad15[0x100-0xF0];
715	rtems_unsigned8 _pad16[0x500-0x100];
716
717	/*
718	* IDMA1 Block
719	*/
720	rtems_unsigned16 iccr;
721	rtems_unsigned16 _pad17;
722	rtems_unsigned16 cmr1;
723	rtems_unsigned16 _pad18;
724	rtems_unsigned32 sapr1;
725	rtems_unsigned32 dapr1;
726	rtems_unsigned32 bcr1;
727	rtems_unsigned8 fcr1;
728	rtems_unsigned8 _pad19;
729	rtems_unsigned8 cmar1;
730	rtems_unsigned8 _pad20;
731	rtems_unsigned8 csr1;
732	rtems_unsigned8 _pad21;
733	rtems_unsigned16 _pad22;
734
735	/*
736	* SDMA Block
737	*/
738	rtems_unsigned8 sdsr;
739	rtems_unsigned8 _pad23;
740	rtems_unsigned16 sdcr;
741	rtems_unsigned32 sdar;
742
743	/*
744	* IDMA2 Block
745	*/
746	rtems_unsigned16 _pad24;
747	rtems_unsigned16 cmr2;
748	rtems_unsigned32 sapr2;
749	rtems_unsigned32 dapr2;
750	rtems_unsigned32 bcr2;
751	rtems_unsigned8 fcr2;
752	rtems_unsigned8 _pad26;
753	rtems_unsigned8 cmar2;
754	rtems_unsigned8 _pad27;
755	rtems_unsigned8 csr2;
756	rtems_unsigned8 _pad28;
757	rtems_unsigned16 _pad29;
758	rtems_unsigned32 _pad30;
759
760	/*
761	* CPIC Block
762	*/
763	rtems_unsigned32 cicr;
764	rtems_unsigned32 cipr;
765	rtems_unsigned32 cimr;
766	rtems_unsigned32 cisr;
767
768	/*
769	* Parallel I/O Block
770	*/
771	rtems_unsigned16 padir;
772	rtems_unsigned16 papar;
773	rtems_unsigned16 paodr;
774	rtems_unsigned16 padat;
775	rtems_unsigned32 _pad31[2];
776	rtems_unsigned16 pcdir;
777	rtems_unsigned16 pcpar;
778	rtems_unsigned16 pcso;
779	rtems_unsigned16 pcdat;
780	rtems_unsigned16 pcint;
781	rtems_unsigned16 _pad32;
782	rtems_unsigned32 _pad33[5];
783
784	/*
785	* TIMER Block
786	*/
787	rtems_unsigned16 tgcr;
788	rtems_unsigned16 _pad34;
789	rtems_unsigned32 _pad35[3];
790	rtems_unsigned16 tmr1;
791	rtems_unsigned16 tmr2;
792	rtems_unsigned16 trr1;
793	rtems_unsigned16 trr2;
794	rtems_unsigned16 tcr1;
795	rtems_unsigned16 tcr2;
796	rtems_unsigned16 tcn1;
797	rtems_unsigned16 tcn2;
798	rtems_unsigned16 tmr3;
799	rtems_unsigned16 tmr4;
800	rtems_unsigned16 trr3;
801	rtems_unsigned16 trr4;
802	rtems_unsigned16 tcr3;
803	rtems_unsigned16 tcr4;
804	rtems_unsigned16 tcn3;
805	rtems_unsigned16 tcn4;
806	rtems_unsigned16 ter1;
807	rtems_unsigned16 ter2;
808	rtems_unsigned16 ter3;
809	rtems_unsigned16 ter4;
810	rtems_unsigned32 _pad36[2];
811
812	/*
813	* CP Block
814	*/
815	rtems_unsigned16 cr;
816	rtems_unsigned16 _pad37;
817	rtems_unsigned16 rccr;
818	rtems_unsigned16 _pad38;
819	rtems_unsigned32 _pad39[3];
820	rtems_unsigned16 _pad40;
821	rtems_unsigned16 rter;
822	rtems_unsigned16 _pad41;
823	rtems_unsigned16 rtmr;
824	rtems_unsigned32 _pad42[5];
825
826	/*
827	* BRG Block
828	*/
829	rtems_unsigned32 brgc1;
830	rtems_unsigned32 brgc2;
831	rtems_unsigned32 brgc3;
832	rtems_unsigned32 brgc4;
833
834	/*
835	* SCC Block
836	*/
837	m360SCCRegisters_t scc1;
838	m360SCCRegisters_t scc2;
839	m360SCCRegisters_t scc3;
840	m360SCCRegisters_t scc4;
841
842	/*
843	* SMC Block
844	*/
845	m360SMCRegisters_t smc1;
846	m360SMCRegisters_t smc2;
847
848	/*
849	* SPI Block
850	*/
851	rtems_unsigned16 spmode;
852	rtems_unsigned16 _pad43[2];
853	rtems_unsigned8 spie;
854	rtems_unsigned8 _pad44;
855	rtems_unsigned16 _pad45;
856	rtems_unsigned8 spim;
857	rtems_unsigned8 _pad46[2];
858	rtems_unsigned8 spcom;
859	rtems_unsigned16 _pad47[2];
860
861	/*
862	* PIP Block
863	*/
864	rtems_unsigned16 pipc;
865	rtems_unsigned16 _pad48;
866	rtems_unsigned16 ptpr;
867	rtems_unsigned32 pbdir;
868	rtems_unsigned32 pbpar;
869	rtems_unsigned16 _pad49;
870	rtems_unsigned16 pbodr;
871	rtems_unsigned32 pbdat;
872	rtems_unsigned32 _pad50[6];
873
874	/*
875	* SI Block
876	*/
877	rtems_unsigned32 simode;
878	rtems_unsigned8 sigmr;
879	rtems_unsigned8 _pad51;
880	rtems_unsigned8 sistr;
881	rtems_unsigned8 sicmr;
882	rtems_unsigned32 _pad52;
883	rtems_unsigned32 sicr;
884	rtems_unsigned16 _pad53;
885	rtems_unsigned16 sirp[2];
886	rtems_unsigned16 _pad54;
887	rtems_unsigned32 _pad55[2];
888	rtems_unsigned8 siram[256];
889	} m360_t;
890
891	extern volatile m360_t m360;
892
893	#endif /* __MC68360_h */

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source: rtems/c/src/exec/score/cpu/m68k/m68360.h @ 9a1ccb3

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