source: rtems/c/src/exec/score/cpu/m68k/cpu_asm.s @ 60b791ad

4.104.114.84.95
Last change on this file since 60b791ad was 60b791ad, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 17, 1998 at 11:46:28 PM

updated copyright to 1998

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File size: 9.1 KB
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1/*  cpu_asm.s
2 *
3 *  This file contains all assembly code for the MC68020 implementation
4 *  of RTEMS.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17
18#include <asm.h>
19
20        .text
21
22/*  void _CPU_Context_switch( run_context, heir_context )
23 *
24 *  This routine performs a normal non-FP context.
25 */
26
27        .align  4
28        .global SYM (_CPU_Context_switch)
29
30.set RUNCONTEXT_ARG,   4                   | save context argument
31.set HEIRCONTEXT_ARG,  8                   | restore context argument
32
33SYM (_CPU_Context_switch):
34          moval    a7@(RUNCONTEXT_ARG),a0| a0 = running thread context
35          movw     sr,d1                 | d1 = status register
36          movml    d1-d7/a2-a7,a0@       | save context
37
38          moval    a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context
39restore:  movml    a0@,d1-d7/a2-a7     | restore context
40          movw     d1,sr                  | restore status register
41          rts
42
43/*PAGE
44 *  void __CPU_Context_save_fp_context( &fp_context_ptr )
45 *  void __CPU_Context_restore_fp_context( &fp_context_ptr )
46 *
47 *  These routines are used to context switch a MC68881 or MC68882.
48 *
49 *  NOTE:  Context save and restore code is based upon the code shown
50 *         on page 6-38 of the MC68881/68882 Users Manual (rev 1).
51 *
52 *         CPU_FP_CONTEXT_SIZE is higher than expected to account for the
53 *         -1 pushed at end of this sequence.
54 *
55 *         Neither of these entries is required if we have software FPU
56 *         emulation.  But if we don't have an FPU or emulation, then
57 *         we need the stub versions of these routines.
58 */
59
60#if (CPU_SOFTWARE_FP == FALSE)
61
62.set FPCONTEXT_ARG,   4                    | save FP context argument
63
64        .align  4
65        .global SYM (_CPU_Context_save_fp)
66SYM (_CPU_Context_save_fp):
67#if ( M68K_HAS_FPU == 1 )
68        moval    a7@(FPCONTEXT_ARG),a1    | a1 = &ptr to context area
69        moval    a1@,a0                   | a0 = Save context area
70        fsave    a0@-                     | save 68881/68882 state frame
71        tstb     a0@                      | check for a null frame
72        beq      nosv                     | Yes, skip save of user model
73        fmovem   fp0-fp7,a0@-             | save data registers (fp0-fp7)
74        fmovem   fpc/fps/fpi,a0@-         | and save control registers
75        movl     #-1,a0@-                 | place not-null flag on stack
76nosv:   movl     a0,a1@                   | save pointer to saved context
77#endif
78        rts
79
80        .align  4
81        .global SYM (_CPU_Context_restore_fp)
82SYM (_CPU_Context_restore_fp):
83#if ( M68K_HAS_FPU == 1 )
84        moval    a7@(FPCONTEXT_ARG),a1    | a1 = &ptr to context area
85        moval    a1@,a0                   | a0 = address of saved context
86        tstb     a0@                      | Null context frame?
87        beq      norst                    | Yes, skip fp restore
88        addql    #4,a0                    | throwaway non-null flag
89        fmovem   a0@+,fpc/fps/fpi         | restore control registers
90        fmovem   a0@+,fp0-fp7             | restore data regs (fp0-fp7)
91norst:  frestore a0@+                     | restore the fp state frame
92        movl     a0,a1@                   | save pointer to saved context
93#endif
94        rts
95#endif
96
97/*PAGE
98 *  void _ISR_Handler()
99 *
100 *  This routine provides the RTEMS interrupt management.
101 *
102 *  NOTE:
103 *    Upon entry, the master stack will contain an interrupt stack frame
104 *    back to the interrupted thread and the interrupt stack will contain
105 *    a throwaway interrupt stack frame.  If dispatching is enabled, this
106 *    is the outer most interrupt, and (a context switch is necessary or
107 *    the current thread has signals), then set up the master stack to
108 *    transfer control to the interrupt dispatcher.
109 */
110
111/*  m68000 notes:
112 *
113 *  with this approach, lower interrupts (1-5 for efi68k) may
114 *  execute twice if a higher priority interrupt is
115 *  acknowledged before _Thread_Dispatch_disable is
116 *  increamented and the higher priority interrupt
117 *  preforms a context switch after executing. The lower
118 *  priority intterrupt will execute (1) at the end of the
119 *  higher priority interrupt in the new context if
120 *  permitted by the new interrupt level mask, and (2) when
121 *  the original context regains the cpu.
122 *
123 *  XXX: Code for switching to a software maintained interrupt stack is
124 *       not in place.
125 */
126 
127#if ( M68K_HAS_VBR == 1)
128.set SR_OFFSET,    0                     | Status register offset
129.set PC_OFFSET,    2                     | Program Counter offset
130.set FVO_OFFSET,   6                     | Format/vector offset
131#else
132.set SR_OFFSET,    2                     | Status register offset
133.set PC_OFFSET,    4                     | Program Counter offset
134.set FVO_OFFSET,   0                     | Format/vector offset placed in the stack
135#endif /* M68K_HAS_VBR */
136 
137.set SAVED,        16                    | space for saved registers
138
139        .align  4
140        .global SYM (_ISR_Handler)
141
142SYM (_ISR_Handler):
143        addql   #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
144        addql   #1,SYM (_ISR_Nest_level) | one nest level deeper
145        moveml  d0-d1/a0-a1,a7@-         | save d0-d1,a0-a1
146
147/*
148 *  NOTE FOR CPUs WITHOUT HARDWARE INTERRUPT STACK:
149 *
150 *  After the interrupted codes registers have been saved, it is save
151 *  to switch to the software maintained interrupt stack.
152 *
153 *  PLEASE, if you have a m68k without a dedicated interrupt stack,
154 *          implement the stack switching code.
155 */
156
157        movew   a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
158        andl    #0x0fff,d0               | d0 = vector offset in vbr
159
160#if ( M68K_HAS_PREINDEXING == 1 )
161        movel   @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR
162#else
163        movel   # SYM (_ISR_Vector_table),a0   | a0 = base of RTEMS table
164        addal   d0,a0                    | a0 = address of vector
165        movel   (a0),a0                  | a0 = address of user routine
166#endif
167
168        lsrl    #2,d0                    | d0 = vector number
169        movel   d0,a7@-                  | push vector number
170        jbsr    a0@                      | invoke the user ISR
171        addql   #4,a7                    | remove vector number
172
173        subql   #1,SYM (_ISR_Nest_level) | one less nest level
174        subql   #1,SYM (_Thread_Dispatch_disable_level)
175                                         | unnest multitasking
176        bne     exit                     | If dispatch disabled, exit
177
178#if ( M68K_HAS_SEPARATE_STACKS == 1 )
179        movew   #0xf000,d0               | isolate format nibble
180        andw    a7@(SAVED+FVO_OFFSET),d0 | get F/VO
181        cmpiw   #0x1000,d0               | is it a throwaway isf?
182        bne     exit                     | NOT outer level, so branch
183#endif
184
185        tstl    SYM (_Context_Switch_necessary)
186                                         | Is thread switch necessary?
187        bne     bframe                   | Yes, invoke dispatcher
188
189        tstl    SYM (_ISR_Signals_to_thread_executing)
190                                         | signals sent to Run_thread
191                                         |   while in interrupt handler?
192        beq     exit                     | No, then exit
193
194
195bframe: clrl    SYM (_ISR_Signals_to_thread_executing)
196                                         | If sent, will be processed
197#if ( M68K_HAS_SEPARATE_STACKS == 1 )
198        movec   msp,a0                   | a0 = master stack pointer
199        movew   #0,a0@-                  | push format word
200        movel   # SYM (_ISR_Dispatch),a0@- | push return addr
201        | filter out the trace bit to stop single step debugging breaking
202        movew   a0@(6+SR_OFFSET),d0
203        andw    #0x7FFF,d0
204        movew   d0,a0@-                  | push thread sr
205        movec   a0,msp                   | set master stack pointer
206#else
207
208        | filter out the trace bit to stop single step debugging breaking
209        movew   a7@(16+SR_OFFSET),d0
210        andw    #0x7FFF,d0
211        movew   d0,sr
212        jsr SYM (_Thread_Dispatch)
213#endif
214
215exit:   moveml  a7@+,d0-d1/a0-a1         | restore d0-d1,a0-a1
216#if ( M68K_HAS_VBR == 0 )
217        addql   #2,a7                    | pop format/id
218#endif /* M68K_HAS_VBR */
219        rte                              | return to thread
220                                         |   OR _Isr_dispatch
221
222/*PAGE
223 *  void _ISR_Dispatch()
224 *
225 *  Entry point from the outermost interrupt service routine exit.
226 *  The current stack is the supervisor mode stack if this processor
227 *  has separate stacks.
228 *
229 *    1.  save all registers not preserved across C calls.
230 *    2.  invoke the _Thread_Dispatch routine to switch tasks
231 *        or a signal to the currently executing task.
232 *    3.  restore all registers not preserved across C calls.
233 *    4.  return from interrupt
234 */
235
236        .global SYM (_ISR_Dispatch)
237SYM (_ISR_Dispatch):
238        movml   d0-d1/a0-a1,a7@-
239        jsr     SYM (_Thread_Dispatch)
240        movml   a7@+,d0-d1/a0-a1
241#if ( M68K_HAS_VBR == 0 )
242        addql   #2,a7                    | pop format/id
243#endif /* M68K_HAS_VBR */
244        rte
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