source: rtems/c/src/exec/score/cpu/m68k/cpu_asm.s @ 11290355

4.104.114.84.9
Last change on this file since 11290355 was 11290355, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 29, 1995 at 5:19:16 PM

all targets compile .. tony's patches in place

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File size: 9.1 KB
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1/*  cpu_asm.s
2 *
3 *  This file contains all assembly code for the MC68020 implementation
4 *  of RTEMS.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17
18#include <asm.h>
19
20        .text
21
22/*  void _CPU_Context_switch( run_context, heir_context )
23 *
24 *  This routine performs a normal non-FP context.
25 */
26
27        .align  4
28        .global SYM (_CPU_Context_switch)
29
30.set RUNCONTEXT_ARG,   4                   | save context argument
31.set HEIRCONTEXT_ARG,  8                   | restore context argument
32
33SYM (_CPU_Context_switch):
34          moval    a7@(RUNCONTEXT_ARG),a0| a0 = running thread context
35          movw     sr,d1                 | d1 = status register
36          movml    d1-d7/a2-a7,a0@       | save context
37
38          moval    a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context
39restore:  movml    a0@,d1-d7/a2-a7     | restore context
40          movw     d1,sr                  | restore status register
41          rts
42
43/*PAGE
44 *  void __CPU_Context_save_fp_context( &fp_context_ptr )
45 *  void __CPU_Context_restore_fp_context( &fp_context_ptr )
46 *
47 *  These routines are used to context switch a MC68881 or MC68882.
48 *
49 *  NOTE:  Context save and restore code is based upon the code shown
50 *         on page 6-38 of the MC68881/68882 Users Manual (rev 1).
51 *
52 *         CPU_FP_CONTEXT_SIZE is higher than expected to account for the
53 *         -1 pushed at end of this sequence.
54 */
55
56.set FPCONTEXT_ARG,   4                    | save FP context argument
57
58        .align  4
59        .global SYM (_CPU_Context_save_fp)
60SYM (_CPU_Context_save_fp):
61#if ( M68K_HAS_FPU == 1 )
62        moval    a7@(FPCONTEXT_ARG),a1    | a1 = &ptr to context area
63        moval    a1@,a0                   | a0 = Save context area
64        fsave    a0@-                     | save 68881/68882 state frame
65        tstb     a0@                      | check for a null frame
66        beq      nosv                     | Yes, skip save of user model
67        fmovem   fp0-fp7,a0@-             | save data registers (fp0-fp7)
68        fmovem   fpc/fps/fpi,a0@-         | and save control registers
69        movl     #-1,a0@-                 | place not-null flag on stack
70nosv:   movl     a0,a1@                   | save pointer to saved context
71#endif
72        rts
73
74        .align  4
75        .global SYM (_CPU_Context_restore_fp)
76SYM (_CPU_Context_restore_fp):
77#if ( M68K_HAS_FPU == 1 )
78        moval    a7@(FPCONTEXT_ARG),a1    | a1 = &ptr to context area
79        moval    a1@,a0                   | a0 = address of saved context
80        tstb     a0@                      | Null context frame?
81        beq      norst                    | Yes, skip fp restore
82        addql    #4,a0                    | throwaway non-null flag
83        fmovem   a0@+,fpc/fps/fpi         | restore control registers
84        fmovem   a0@+,fp0-fp7             | restore data regs (fp0-fp7)
85norst:  frestore a0@+                     | restore the fp state frame
86        movl     a0,a1@                   | save pointer to saved context
87#endif
88        rts
89
90/*PAGE
91 *  void _ISR_Handler()
92 *
93 *  This routine provides the RTEMS interrupt management.
94 *
95 *  NOTE:
96 *    Upon entry, the master stack will contain an interrupt stack frame
97 *    back to the interrupted thread and the interrupt stack will contain
98 *    a throwaway interrupt stack frame.  If dispatching is enabled, this
99 *    is the outer most interrupt, and (a context switch is necessary or
100 *    the current thread has signals), then set up the master stack to
101 *    transfer control to the interrupt dispatcher.
102 */
103
104/*  m68000 notes:
105 *
106 *  with this approach, lower interrupts (1-5 for efi68k) may
107 *  execute twice if a higher priority interrupt is
108 *  acknowledged before _Thread_Dispatch_disable is
109 *  increamented and the higher priority interrupt
110 *  preforms a context switch after executing. The lower
111 *  priority intterrupt will execute (1) at the end of the
112 *  higher priority interrupt in the new context if
113 *  permitted by the new interrupt level mask, and (2) when
114 *  the original context regains the cpu.
115 *
116 *  XXX: Code for switching to a software maintained interrupt stack is
117 *       not in place.
118 */
119 
120#if ( M68K_HAS_VBR == 1)
121.set SR_OFFSET,    0                     | Status register offset
122.set PC_OFFSET,    2                     | Program Counter offset
123.set FVO_OFFSET,   6                     | Format/vector offset
124#else
125.set JSR_OFFSET,   0                     | return address from jsr table
126.set SR_OFFSET,    4
127.set PC_OFFSET,    6
128#endif /* M68K_HAS_VBR */
129 
130.set SAVED,        16                    | space for saved registers
131
132        .align  4
133        .global SYM (_ISR_Handler)
134
135SYM (_ISR_Handler):
136        addql   #1,SYM (_ISR_Nest_level) | one nest level deeper
137        addql   #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
138        moveml  d0-d1/a0-a1,a7@-         | save d0-d1,a0-a1
139
140/*
141 *  NOTE FOR CPUs WITHOUT HARDWARE INTERRUPT STACK:
142 *
143 *  After the interrupted codes registers have been saved, it is save
144 *  to switch to the software maintained interrupt stack.
145 */
146
147#if ( M68K_HAS_VBR == 0)
148        movel   a7@(SAVED+JSR_OFFSET),d0 | assume the exception table at 0x0000
149        addql   #6,d0                    | points to a jump table (jsr) in RAM
150        subl    #_VBR,d0                 | VBR is the location of the jump table
151        divs    #3,d0
152        lsll    #1,d0
153        extl    d0
154#else
155        movew   a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
156        andl    #0x0fff,d0               | d0 = vector offset in vbr
157#endif
158
159#if ( M68K_HAS_PREINDEXING == 1 )
160        movel   @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR
161#else
162        movel   # SYM (_ISR_Vector_table),a0   | a0 = base of RTEMS table
163        addal   d0,a0                    | a0 = address of vector
164        movel   (a0),a0                  | a0 = address of user routine
165#endif
166
167        lsrl    #2,d0                    | d0 = vector number
168        movel   d0,a7@-                  | push vector number
169        jbsr    a0@                      | invoke the user ISR
170        addql   #4,a7                    | remove vector number
171
172/*
173 *   The following entry should be unnecessary once the support is
174 *   in place to know what vector we got on a 68000 core.
175 */
176
177        .global SYM (_ISR_Exit)
178SYM (_ISR_Exit):
179
180        subql   #1,SYM (_ISR_Nest_level) | one less nest level
181        subql   #1,SYM (_Thread_Dispatch_disable_level)
182                                         | unnest multitasking
183        bne     exit                     | If dispatch disabled, exit
184
185#if ( M68K_HAS_SEPARATE_STACKS == 1 )
186        movew   #0xf000,d0               | isolate format nibble
187        andw    a7@(SAVED+FVO_OFFSET),d0 | get F/VO
188        cmpiw   #0x1000,d0               | is it a throwaway isf?
189        bne     exit                     | NOT outer level, so branch
190#endif
191
192        tstl    SYM (_Context_Switch_necessary)
193                                         | Is thread switch necessary?
194        bne     bframe                   | Yes, invoke dispatcher
195
196        tstl    SYM (_ISR_Signals_to_thread_executing)
197                                         | signals sent to Run_thread
198                                         |   while in interrupt handler?
199        beq     exit                     | No, then exit
200
201
202bframe: clrl    SYM (_ISR_Signals_to_thread_executing)
203                                         | If sent, will be processed
204#if ( M68K_HAS_SEPARATE_STACKS == 1 )
205        movec   msp,a0                   | a0 = master stack pointer
206        movew   #0,a0@-                  | push format word
207        movel   # SYM (_ISR_Dispatch),a0@- | push return addr
208        movew   a0@(6+SR_OFFSET),a0@-    | push thread sr
209        movec   a0,msp                   | set master stack pointer
210#else
211
212        movew   a7@(16+SR_OFFSET),sr
213        jsr     SYM (_Thread_Dispatch)
214
215#endif
216
217exit:   moveml  a7@+,d0-d1/a0-a1         | restore d0-d1,a0-a1
218#if ( M68K_HAS_VBR == 0)
219        addql   #4,a7                    | pop vector address
220#endif /* M68K_HAS_VBR */
221        rte                              | return to thread
222                                         |   OR _Isr_dispatch
223
224/*PAGE
225 *  void _ISR_Dispatch()
226 *
227 *  Entry point from the outermost interrupt service routine exit.
228 *  The current stack is the supervisor mode stack if this processor
229 *  has separate stacks.
230 *
231 *    1.  save all registers not preserved across C calls.
232 *    2.  invoke the _Thread_Dispatch routine to switch tasks
233 *        or a signal to the currently executing task.
234 *    3.  restore all registers not preserved across C calls.
235 *    4.  return from interrupt
236 */
237
238        .global SYM (_ISR_Dispatch)
239SYM (_ISR_Dispatch):
240        movml   d0-d1/a0-a1,a7@-
241        jsr     SYM (_Thread_Dispatch)
242        movml   a7@+,d0-d1/a0-a1
243#if ( M68K_HAS_VBR == 0)
244        addql   #4,a7                    | pop vector address
245#endif /* M68K_HAS_VBR */
246        rte
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