[ac7d5ef0] | 1 | /* cpu_asm.s |
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| 2 | * |
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| 3 | * This file contains all assembly code for the MC68020 implementation |
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| 4 | * of RTEMS. |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * All rights assigned to U.S. Government, 1994. |
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| 9 | * |
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| 10 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 11 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 12 | * notice must appear in all copies of this file and its derivatives. |
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| 13 | * |
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| 14 | * $Id$ |
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| 15 | */ |
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| 16 | |
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| 17 | |
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| 18 | #include <asm.h> |
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| 19 | |
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| 20 | .text |
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| 21 | |
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| 22 | /* void _CPU_Context_switch( run_context, heir_context ) |
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| 23 | * |
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| 24 | * This routine performs a normal non-FP context. |
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| 25 | */ |
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| 26 | |
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| 27 | .align 4 |
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| 28 | .global SYM (_CPU_Context_switch) |
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| 29 | |
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| 30 | .set RUNCONTEXT_ARG, 4 | save context argument |
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| 31 | .set HEIRCONTEXT_ARG, 8 | restore context argument |
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| 32 | |
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| 33 | SYM (_CPU_Context_switch): |
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| 34 | moval a7@(RUNCONTEXT_ARG),a0| a0 = running thread context |
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| 35 | movw sr,d1 | d1 = status register |
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| 36 | movml d1-d7/a2-a7,a0@ | save context |
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| 37 | |
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| 38 | moval a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context |
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| 39 | restore: movml a0@,d1-d7/a2-a7 | restore context |
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| 40 | movw d1,sr | restore status register |
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| 41 | rts |
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| 42 | |
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| 43 | /*PAGE |
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| 44 | * void __CPU_Context_save_fp_context( &fp_context_ptr ) |
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| 45 | * void __CPU_Context_restore_fp_context( &fp_context_ptr ) |
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| 46 | * |
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| 47 | * These routines are used to context switch a MC68881 or MC68882. |
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| 48 | * |
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| 49 | * NOTE: Context save and restore code is based upon the code shown |
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| 50 | * on page 6-38 of the MC68881/68882 Users Manual (rev 1). |
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| 51 | * |
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| 52 | * CPU_FP_CONTEXT_SIZE is higher than expected to account for the |
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| 53 | * -1 pushed at end of this sequence. |
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| 54 | */ |
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| 55 | |
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| 56 | .set FPCONTEXT_ARG, 4 | save FP context argument |
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| 57 | |
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| 58 | .align 4 |
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| 59 | .global SYM (_CPU_Context_save_fp) |
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| 60 | SYM (_CPU_Context_save_fp): |
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| 61 | #if ( M68K_HAS_FPU == 1 ) |
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| 62 | moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area |
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| 63 | moval a1@,a0 | a0 = Save context area |
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| 64 | fsave a0@- | save 68881/68882 state frame |
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| 65 | tstb a0@ | check for a null frame |
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| 66 | beq nosv | Yes, skip save of user model |
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| 67 | fmovem fp0-fp7,a0@- | save data registers (fp0-fp7) |
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| 68 | fmovem fpc/fps/fpi,a0@- | and save control registers |
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| 69 | movl #-1,a0@- | place not-null flag on stack |
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| 70 | nosv: movl a0,a1@ | save pointer to saved context |
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| 71 | #endif |
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| 72 | rts |
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| 73 | |
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| 74 | .align 4 |
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| 75 | .global SYM (_CPU_Context_restore_fp) |
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| 76 | SYM (_CPU_Context_restore_fp): |
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| 77 | #if ( M68K_HAS_FPU == 1 ) |
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| 78 | moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area |
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| 79 | moval a1@,a0 | a0 = address of saved context |
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| 80 | tstb a0@ | Null context frame? |
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| 81 | beq norst | Yes, skip fp restore |
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| 82 | addql #4,a0 | throwaway non-null flag |
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| 83 | fmovem a0@+,fpc/fps/fpi | restore control registers |
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| 84 | fmovem a0@+,fp0-fp7 | restore data regs (fp0-fp7) |
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| 85 | norst: frestore a0@+ | restore the fp state frame |
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| 86 | movl a0,a1@ | save pointer to saved context |
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| 87 | #endif |
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| 88 | rts |
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| 89 | |
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| 90 | /*PAGE |
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| 91 | * void _ISR_Handler() |
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| 92 | * |
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| 93 | * This routine provides the RTEMS interrupt management. |
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| 94 | * |
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| 95 | * NOTE: |
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| 96 | * Upon entry, the master stack will contain an interrupt stack frame |
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| 97 | * back to the interrupted thread and the interrupt stack will contain |
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| 98 | * a throwaway interrupt stack frame. If dispatching is enabled, this |
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| 99 | * is the outer most interrupt, and (a context switch is necessary or |
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| 100 | * the current thread has signals), then set up the master stack to |
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| 101 | * transfer control to the interrupt dispatcher. |
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| 102 | */ |
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| 103 | |
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| 104 | .set SR_OFFSET, 0 | Status register offset |
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| 105 | .set PC_OFFSET, 2 | Program Counter offset |
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| 106 | .set FVO_OFFSET, 6 | Format/vector offset |
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| 107 | |
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| 108 | .set SAVED, 16 | space for saved registers |
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| 109 | |
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| 110 | .align 4 |
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| 111 | .global SYM (_ISR_Handler) |
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| 112 | |
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| 113 | SYM (_ISR_Handler): |
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| 114 | moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 |
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| 115 | addql #1,SYM (_ISR_Nest_level) | one nest level deeper |
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| 116 | addql #1,SYM (_Thread_Dispatch_disable_level) |
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| 117 | | disable multitasking |
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| 118 | movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO |
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| 119 | andl #0x0fff,d0 | d0 = vector offset in vbr |
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| 120 | |
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| 121 | #if ( M68K_HAS_PREINDEXING == 1 ) |
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| 122 | movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR |
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| 123 | #else |
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| 124 | movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table |
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| 125 | addal d0,a0 | a0 = address of vector |
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| 126 | movel @(a0),a0 | a0 = address of user routine |
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| 127 | #warning "UNTESTED CODE!!!" |
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| 128 | #endif |
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| 129 | |
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| 130 | lsrl #2,d0 | d0 = vector number |
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| 131 | movel d0,a7@- | push vector number |
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| 132 | jbsr a0@ | invoke the user ISR |
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| 133 | addql #4,a7 | remove vector number |
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| 134 | |
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[9e86dd7d] | 135 | /* |
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| 136 | * The following entry should be unnecessary once the support is |
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| 137 | * in place to know what vector we got on a 68000 core. |
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| 138 | */ |
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| 139 | |
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| 140 | .global SYM (_ISR_Exit) |
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| 141 | SYM (_ISR_Exit): |
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| 142 | |
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[ac7d5ef0] | 143 | subql #1,SYM (_ISR_Nest_level) | one less nest level |
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| 144 | subql #1,SYM (_Thread_Dispatch_disable_level) |
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| 145 | | unnest multitasking |
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| 146 | bne exit | If dispatch disabled, exit |
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| 147 | |
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[9e86dd7d] | 148 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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[ac7d5ef0] | 149 | movew #0xf000,d0 | isolate format nibble |
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| 150 | andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO |
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| 151 | cmpiw #0x1000,d0 | is it a throwaway isf? |
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| 152 | bne exit | NOT outer level, so branch |
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[9e86dd7d] | 153 | #endif |
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[ac7d5ef0] | 154 | |
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| 155 | tstl SYM (_Context_Switch_necessary) |
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| 156 | | Is thread switch necessary? |
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| 157 | bne bframe | Yes, invoke dispatcher |
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| 158 | |
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| 159 | tstl SYM (_ISR_Signals_to_thread_executing) |
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| 160 | | signals sent to Run_thread |
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| 161 | | while in interrupt handler? |
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| 162 | beq exit | No, then exit |
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| 163 | |
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| 164 | |
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| 165 | bframe: clrl SYM (_ISR_Signals_to_thread_executing) |
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| 166 | | If sent, will be processed |
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| 167 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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[9e86dd7d] | 168 | movec msp,a0 | a0 = master stack pointer |
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| 169 | movew #0,a0@- | push format word |
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[ac7d5ef0] | 170 | movel # SYM (_ISR_Dispatch),a0@- | push return addr |
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[9e86dd7d] | 171 | movew a0@(6+SR_OFFSET),a0@- | push thread sr |
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| 172 | movec a0,msp | set master stack pointer |
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[ac7d5ef0] | 173 | #else |
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[9e86dd7d] | 174 | |
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| 175 | movew a7@(16+SR_OFFSET),sr |
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| 176 | jsr SYM (_Thread_Dispatch) |
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| 177 | |
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[ac7d5ef0] | 178 | #endif |
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| 179 | |
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[9e86dd7d] | 180 | exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 |
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[ac7d5ef0] | 181 | rte | return to thread |
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| 182 | | OR _Isr_dispatch |
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| 183 | |
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| 184 | /*PAGE |
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| 185 | * void _ISR_Dispatch() |
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| 186 | * |
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| 187 | * Entry point from the outermost interrupt service routine exit. |
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| 188 | * The current stack is the supervisor mode stack if this processor |
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| 189 | * has separate stacks. |
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| 190 | * |
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| 191 | * 1. save all registers not preserved across C calls. |
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| 192 | * 2. invoke the _Thread_Dispatch routine to switch tasks |
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| 193 | * or a signal to the currently executing task. |
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| 194 | * 3. restore all registers not preserved across C calls. |
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| 195 | * 4. return from interrupt |
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| 196 | */ |
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| 197 | |
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| 198 | .global SYM (_ISR_Dispatch) |
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| 199 | SYM (_ISR_Dispatch): |
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| 200 | movml d0-d1/a0-a1,a7@- |
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| 201 | jsr SYM (_Thread_Dispatch) |
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| 202 | movml a7@+,d0-d1/a0-a1 |
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| 203 | rte |
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| 204 | |
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| 205 | |
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| 206 | |
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| 207 | |
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| 208 | |
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| 209 | |
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| 210 | |
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| 214 | |
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