source: rtems/c/src/exec/score/cpu/m68k/cpu.h @ c80add4

4.104.114.84.95
Last change on this file since c80add4 was c80add4, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 25, 1998 at 6:46:47 PM

m68k software interrupt stack support from Chris Johns and Eric Norum.

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File size: 15.7 KB
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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/m68k.h>              /* pick up machine definitions */
25#ifndef ASM
26#include <rtems/score/m68ktypes.h>
27#endif
28
29/* conditional compilation parameters */
30
31#define CPU_INLINE_ENABLE_DISPATCH       TRUE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  Use the m68k's hardware interrupt stack support and have the
36 *  interrupt manager allocate the memory for it.
37 */
38
39#if ( M68K_HAS_SEPARATE_STACKS == 1)
40#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
41#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
42#define CPU_ALLOCATE_INTERRUPT_STACK     1
43#else
44#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
45#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
46#define CPU_ALLOCATE_INTERRUPT_STACK     1
47#endif
48
49/*
50 *  Some family members have no FP, some have an FPU such as the
51 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
52 *
53 *  NOTE:  If on a CPU without hardware FP, then one can use software
54 *         emulation.  The gcc software FP emulation code has data which
55 *         must be contexted switched on a per task basis.
56 */
57
58#if ( M68K_HAS_FPU == 1 )
59#define CPU_HARDWARE_FP     TRUE
60#define CPU_SOFTWARE_FP     FALSE
61#else
62#define CPU_HARDWARE_FP     FALSE
63#if defined(__GCC__)
64#define CPU_SOFTWARE_FP     TRUE
65#else
66#define CPU_SOFTWARE_FP     FALSE
67#endif
68#endif
69
70/*
71 *  All tasks are not by default floating point tasks on this CPU.
72 *  The IDLE task does not have a floating point context on this CPU.
73 *  It is safe to use the deferred floating point context switch
74 *  algorithm on this CPU.
75 */
76
77#define CPU_ALL_TASKS_ARE_FP             FALSE
78#define CPU_IDLE_TASK_IS_FP              FALSE
79#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
80
81#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
82#define CPU_STACK_GROWS_UP               FALSE
83#define CPU_STRUCTURE_ALIGNMENT
84
85/*
86 *  Define what is required to specify how the network to host conversion
87 *  routines are handled.
88 */
89
90#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
91#define CPU_BIG_ENDIAN                           TRUE
92#define CPU_LITTLE_ENDIAN                        FALSE
93
94#ifndef ASM
95/* structures */
96
97/*
98 *  Basic integer context for the m68k family.
99 */
100
101typedef struct {
102  unsigned32  sr;                /* (sr) status register */
103  unsigned32  d2;                /* (d2) data register 2 */
104  unsigned32  d3;                /* (d3) data register 3 */
105  unsigned32  d4;                /* (d4) data register 4 */
106  unsigned32  d5;                /* (d5) data register 5 */
107  unsigned32  d6;                /* (d6) data register 6 */
108  unsigned32  d7;                /* (d7) data register 7 */
109  void       *a2;                /* (a2) address register 2 */
110  void       *a3;                /* (a3) address register 3 */
111  void       *a4;                /* (a4) address register 4 */
112  void       *a5;                /* (a5) address register 5 */
113  void       *a6;                /* (a6) address register 6 */
114  void       *a7_msp;            /* (a7) master stack pointer */
115}   Context_Control;
116
117/*
118 *  Floating point context ares
119 */
120
121#if (CPU_SOFTWARE_FP == TRUE)
122
123/*
124 *  This is the same as gcc's view of the software FP condition code
125 *  register _fpCCR.  The implementation of the emulation code is
126 *  in the gcc-VERSION/config/m68k directory.  This structure is
127 *  correct as of gcc 2.7.2.2.
128 */
129
130typedef struct {
131  unsigned16   _exception_bits;
132  unsigned16   _trap_enable_bits;
133  unsigned16   _sticky_bits;
134  unsigned16   _rounding_mode;
135  unsigned16   _format;
136  unsigned16   _last_operation;
137  union {
138    float sf;
139    double df;
140  } _operand1;
141  union {
142    float sf;
143    double df;
144  } _operand2;
145} Context_Control_fp;
146
147#else
148
149/*
150 *  FP context save area for the M68881/M68882 numeric coprocessors.
151 */
152
153typedef struct {
154  unsigned8   fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
155                                    /*    96 bytes for FMOVEM FP0-7      */
156                                    /*    12 bytes for FMOVEM CREGS      */
157                                    /*     4 bytes for non-null flag     */
158} Context_Control_fp;
159#endif
160
161/*
162 *  The following structure defines the set of information saved
163 *  on the current stack by RTEMS upon receipt of each interrupt.
164 */
165
166typedef struct {
167  unsigned32   TBD;   /* XXX Fix for this CPU */
168} CPU_Interrupt_frame;
169
170/*
171 *  The following table contains the information required to configure
172 *  the m68k specific parameters.
173 */
174
175typedef struct {
176  void       (*pretasking_hook)( void );
177  void       (*predriver_hook)( void );
178  void       (*postdriver_hook)( void );
179  void       (*idle_task)( void );
180  boolean      do_zero_of_workspace;
181  unsigned32   interrupt_stack_size;
182  unsigned32   extra_mpci_receive_server_stack;
183  void *     (*stack_allocate_hook)( unsigned32 );
184  void       (*stack_free_hook)( void* );
185  /* end of fields required on all CPUs */
186
187  m68k_isr    *interrupt_vector_table;
188}   rtems_cpu_table;
189
190/* variables */
191
192SCORE_EXTERN void                   *_CPU_Interrupt_stack_low;
193SCORE_EXTERN void                   *_CPU_Interrupt_stack_high;
194
195extern char                         _VBR[]; 
196
197#if ( M68K_HAS_VBR == 0 )
198
199/*
200 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
201 * pushed onto the stack. This is not is the same order as VBR processors.
202 * The ISR handler takes the format and uses it for dispatching the user
203 * handler.
204 *
205 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
206 *
207 */
208
209typedef struct {
210  unsigned16 move_a7;            /* move #FORMAT_ID,%a7@- */
211  unsigned16 format_id;
212  unsigned16 jmp;                /* jmp  _ISR_Handlers */
213  unsigned32 isr_handler;
214} _CPU_ISR_handler_entry;
215
216#define M68K_MOVE_A7 0x3F3C
217#define M68K_JMP     0x4EF9
218
219      /* points to jsr-exception-table in targets wo/ VBR register */
220SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; 
221
222#endif /* M68K_HAS_VBR */
223#endif /* ASM */
224
225/* constants */
226
227/*
228 *  This defines the number of levels and the mask used to pick those
229 *  bits out of a thread mode.
230 */
231
232#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
233#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
234
235/*
236 *  context size area for floating point
237 */
238
239#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
240
241/*
242 *  extra stack required by the MPCI receive server thread
243 */
244
245#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
246
247/*
248 *  m68k family supports 256 distinct vectors.
249 */
250
251#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
252#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
253
254/*
255 *  Minimum size of a thread's stack.
256 */
257
258#define CPU_STACK_MINIMUM_SIZE           2048
259
260/*
261 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
262 */
263
264#define CPU_ALIGNMENT                    4
265#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
266#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
267
268/*
269 *  On m68k thread stacks require no further alignment after allocation
270 *  from the Workspace.
271 */
272
273#define CPU_STACK_ALIGNMENT        0
274
275#ifndef ASM
276
277/* macros */
278
279/*
280 *  ISR handler macros
281 *
282 *  These macros perform the following functions:
283 *     + disable all maskable CPU interrupts
284 *     + restore previous interrupt level (enable)
285 *     + temporarily restore interrupts (flash)
286 *     + set a particular level
287 */
288
289#define _CPU_ISR_Disable( _level ) \
290  m68k_disable_interrupts( _level )
291
292#define _CPU_ISR_Enable( _level ) \
293  m68k_enable_interrupts( _level )
294
295#define _CPU_ISR_Flash( _level ) \
296  m68k_flash_interrupts( _level )
297
298#define _CPU_ISR_Set_level( _newlevel ) \
299   m68k_set_interrupt_level( _newlevel )
300
301unsigned32 _CPU_ISR_Get_level( void );
302
303/* end of ISR handler macros */
304
305/*
306 *  Context handler macros
307 *
308 *  These macros perform the following functions:
309 *     + initialize a context area
310 *     + restart the current thread
311 *     + calculate the initial pointer into a FP context area
312 *     + initialize an FP context area
313 */
314
315#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
316                                 _isr, _entry_point, _is_fp ) \
317   do { \
318     unsigned32 _stack; \
319     \
320     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
321     _stack                  = (unsigned32)(_stack_base) + (_size) - 4; \
322     (_the_context)->a7_msp  = (void *)_stack; \
323     *(void **)_stack        = (void *)(_entry_point); \
324   } while ( 0 )
325
326#define _CPU_Context_Restart_self( _the_context ) \
327  { asm volatile( "movew %0,%%sr ; " \
328                  "moval %1,%%a7 ; " \
329                  "rts"  \
330        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
331        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
332  }
333
334/*
335 *  Floating Point Context Area Support routines
336 */
337
338#if (CPU_SOFTWARE_FP == TRUE)
339
340/*
341 *  This software FP implementation is only for GCC.
342 */
343
344#define _CPU_Context_Fp_start( _base, _offset ) \
345   ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
346
347
348#define _CPU_Context_Initialize_fp( _fp_area ) \
349   { \
350   Context_Control_fp *_fp; \
351   _fp = *(Context_Control_fp **)_fp_area; \
352   _fp->_exception_bits = 0; \
353   _fp->_trap_enable_bits = 0; \
354   _fp->_sticky_bits = 0; \
355   _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
356   _fp->_format = 0;         /* NIL */ \
357   _fp->_last_operation = 0;  /* NOOP */ \
358   _fp->_operand1.df = 0; \
359   _fp->_operand2.df = 0; \
360   }
361#else
362#define _CPU_Context_Fp_start( _base, _offset ) \
363   ((void *) \
364     _Addresses_Add_offset( \
365        (_base), \
366        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
367     ) \
368   )
369
370#define _CPU_Context_Initialize_fp( _fp_area ) \
371   { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
372     \
373     *(--(_fp_context)) = 0; \
374     *(_fp_area) = (unsigned8 *)(_fp_context); \
375   }
376#endif
377
378/* end of Context handler macros */
379
380/*
381 *  Fatal Error manager macros
382 *
383 *  These macros perform the following functions:
384 *    + disable interrupts and halt the CPU
385 */
386
387#define _CPU_Fatal_halt( _error ) \
388  { asm volatile( "movl  %0,%%d0; " \
389                  "orw   #0x0700,%%sr; " \
390                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
391  }
392
393/* end of Fatal Error manager macros */
394
395/*
396 *  Bitfield handler macros
397 *
398 *  These macros perform the following functions:
399 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
400 *
401 *  NOTE:
402 *
403 *    It appears that on the M68020 bitfield are always 32 bits wide
404 *    when in a register.  This code forces the bitfield to be in
405 *    memory (it really always is anyway). This allows us to
406 *    have a real 16 bit wide bitfield which operates "correctly."
407 */
408
409#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
410#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
411
412#if ( M68K_HAS_BFFFO == 1 )
413
414#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
415  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
416#else
417
418/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
419   _CPU_Priority_bits_index is not needed), handles the 0 case, and
420   does not molest _value -- jsg */
421#if ( M68K_HAS_EXTB_L == 1 )
422#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
423  { \
424    extern const unsigned char __BFFFOtable[256]; \
425    register int dumby; \
426    \
427    asm volatile ( "   move.w  %2,%1\n"        \
428       "   lsr.w   #8,%1\n"        \
429       "   beq.s   1f\n"           \
430       "   move.b  (%3,%1.w),%0\n" \
431       "   extb.l  %0\n"           \
432       "   bra.s   0f\n"           \
433       "1: moveq.l #8,%0\n"        \
434       "   add.b   (%3,%2.w),%0\n" \
435       "0:\n"                      \
436       : "=&d" ((_output)), "=&d" ((dumby)) \
437       : "d" ((_value)), "ao" ((__BFFFOtable)) \
438       : "cc" ) ; \
439  }
440#else
441#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
442  { \
443    extern const unsigned char __BFFFOtable[256]; \
444    register int dumby; \
445    \
446    asm volatile ( "   move.w  %2,%1\n"        \
447       "   lsr.w   #8,%1\n"        \
448       "   beq.s   1f\n"           \
449       "   move.b  (%3,%1.w),%0\n" \
450       "   and.l   #0x000000ff,%0\n"\
451       "   bra.s   0f\n"           \
452       "1: moveq.l #8,%0\n"        \
453       "   add.b   (%3,%2.w),%0\n" \
454       "0:\n"                      \
455       : "=&d" ((_output)), "=&d" ((dumby)) \
456       : "d" ((_value)), "ao" ((__BFFFOtable)) \
457       : "cc" ) ; \
458  }
459#endif /* M68K_HAS_EXTB_L */
460
461#endif
462
463/* end of Bitfield handler macros */
464
465/*
466 *  Priority handler macros
467 *
468 *  These macros perform the following functions:
469 *    + return a mask with the bit for this major/minor portion of
470 *      of thread priority set.
471 *    + translate the bit number returned by "Bitfield_find_first_bit"
472 *      into an index into the thread ready chain bit maps
473 */
474
475#define _CPU_Priority_Mask( _bit_number ) \
476  ( 0x8000 >> (_bit_number) )
477
478#define _CPU_Priority_bits_index( _priority ) \
479  (_priority)
480
481/* end of Priority handler macros */
482
483/* functions */
484
485/*
486 *  _CPU_Initialize
487 *
488 *  This routine performs CPU dependent initialization.
489 */
490
491void _CPU_Initialize(
492  rtems_cpu_table  *cpu_table,
493  void      (*thread_dispatch)
494);
495
496/*
497 *  _CPU_ISR_install_raw_handler
498 *
499 *  This routine installs a "raw" interrupt handler directly into the
500 *  processor's vector table.
501 */
502 
503void _CPU_ISR_install_raw_handler(
504  unsigned32  vector,
505  proc_ptr    new_handler,
506  proc_ptr   *old_handler
507);
508
509/*
510 *  _CPU_ISR_install_vector
511 *
512 *  This routine installs an interrupt vector.
513 */
514
515void _CPU_ISR_install_vector(
516  unsigned32       vector,
517  proc_ptr         new_handler,
518  proc_ptr        *old_handler
519);
520
521/*
522 *  _CPU_Install_interrupt_stack
523 *
524 *  This routine installs the hardware interrupt stack pointer.
525 */
526
527void _CPU_Install_interrupt_stack( void );
528
529/*
530 *  _CPU_Context_switch
531 *
532 *  This routine switches from the run context to the heir context.
533 */
534
535void _CPU_Context_switch(
536  Context_Control  *run,
537  Context_Control  *heir
538);
539
540/*
541 *  _CPU_Context_save_fp
542 *
543 *  This routine saves the floating point context passed to it.
544 */
545
546void _CPU_Context_save_fp(
547  void **fp_context_ptr
548);
549
550/*
551 *  _CPU_Context_restore_fp
552 *
553 *  This routine restores the floating point context passed to it.
554 */
555
556void _CPU_Context_restore_fp(
557  void **fp_context_ptr
558);
559
560#if (M68K_HAS_FPSP_PACKAGE == 1)
561/*
562 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
563 *
564 *  NOTES: 
565 *
566 *  Motorola 68k family CPU's before the 68040 used a coprocessor
567 *  (68881 or 68882) to handle floating point.  The 68040 has internal
568 *  floating point support -- but *not* the complete support provided by
569 *  the 68881 or 68882.  The leftover functions are taken care of by the
570 *  M68040 Floating Point Support Package.  Quoting from the MC68040
571 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
572 *
573 *    "When used with the M68040FPSP, the MC68040 FPU is fully
574 *    compliant with IEEE floating-point standards."
575 *
576 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
577 *  is invoked early in the application code to insure that proper FP
578 *  behavior is installed.  This is not left to the BSP to call, since
579 *  this would force all applications using that BSP to use FPSP which
580 *  is not necessarily desirable.
581 *
582 *  There is a similar package for the 68060 but RTEMS does not yet
583 *  support the 68060.
584 */
585
586void M68KFPSPInstallExceptionHandlers (void);
587
588SCORE_EXTERN int (*_FPSP_install_raw_handler)(
589  unsigned32 vector,
590  proc_ptr new_handler,
591  proc_ptr *old_handler
592);
593
594#endif
595
596
597#endif
598
599#ifdef __cplusplus
600}
601#endif
602
603#endif
604/* end of include file */
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