1 | /* cpu.h |
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2 | * |
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3 | * This include file contains information pertaining to the Motorola |
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4 | * m68xxx processor family. |
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5 | * |
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6 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * All rights assigned to U.S. Government, 1994. |
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9 | * |
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10 | * This material may be reproduced by or for the U.S. Government pursuant |
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11 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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12 | * notice must appear in all copies of this file and its derivatives. |
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13 | * |
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14 | * $Id$ |
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15 | */ |
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16 | |
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17 | #ifndef __CPU_h |
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18 | #define __CPU_h |
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19 | |
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20 | #ifdef __cplusplus |
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21 | extern "C" { |
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22 | #endif |
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23 | |
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24 | /* |
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25 | * If defined, this causes some of the macros to initialize their |
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26 | * variables to zero before doing inline assembly. This gets rid |
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27 | * of compile time warnings at the cost of a little execution time |
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28 | * in some time critical routines. |
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29 | */ |
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30 | |
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31 | #define NO_UNINITIALIZED_WARNINGS |
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32 | |
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33 | #include <m68k.h> |
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34 | |
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35 | /* conditional compilation parameters */ |
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36 | |
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37 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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38 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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39 | |
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40 | /* |
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41 | * Use the m68k's hardware interrupt stack support and have the |
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42 | * interrupt manager allocate the memory for it. |
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43 | */ |
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44 | |
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45 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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46 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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47 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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48 | |
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49 | /* |
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50 | * Some family members have no FP, some have an FPU such as the |
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51 | * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). |
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52 | */ |
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53 | |
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54 | #if ( M68K_HAS_FPU == 1 ) |
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55 | #define CPU_HARDWARE_FP TRUE |
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56 | #else |
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57 | #define CPU_HARDWARE_FP FALSE |
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58 | #endif |
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59 | |
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60 | /* |
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61 | * All tasks are not by default floating point tasks on this CPU. |
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62 | * The IDLE task does not have a floating point context on this CPU. |
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63 | * It is safe to use the deferred floating point context switch |
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64 | * algorithm on this CPU. |
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65 | */ |
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66 | |
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67 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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68 | #define CPU_IDLE_TASK_IS_FP FALSE |
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69 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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70 | |
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71 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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72 | #define CPU_STACK_GROWS_UP FALSE |
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73 | #define CPU_STRUCTURE_ALIGNMENT |
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74 | |
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75 | /* structures */ |
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76 | |
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77 | /* |
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78 | * Basic integer context for the m68k family. |
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79 | */ |
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80 | |
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81 | typedef struct { |
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82 | unsigned32 sr; /* (sr) status register */ |
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83 | unsigned32 d2; /* (d2) data register 2 */ |
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84 | unsigned32 d3; /* (d3) data register 3 */ |
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85 | unsigned32 d4; /* (d4) data register 4 */ |
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86 | unsigned32 d5; /* (d5) data register 5 */ |
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87 | unsigned32 d6; /* (d6) data register 6 */ |
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88 | unsigned32 d7; /* (d7) data register 7 */ |
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89 | void *a2; /* (a2) address register 2 */ |
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90 | void *a3; /* (a3) address register 3 */ |
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91 | void *a4; /* (a4) address register 4 */ |
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92 | void *a5; /* (a5) address register 5 */ |
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93 | void *a6; /* (a6) address register 6 */ |
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94 | void *a7_msp; /* (a7) master stack pointer */ |
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95 | } Context_Control; |
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96 | |
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97 | /* |
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98 | * FP context save area for the M68881/M68882 numeric coprocessors. |
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99 | */ |
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100 | |
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101 | typedef struct { |
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102 | unsigned8 fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */ |
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103 | /* 96 bytes for FMOVEM FP0-7 */ |
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104 | /* 12 bytes for FMOVEM CREGS */ |
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105 | /* 4 bytes for non-null flag */ |
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106 | } Context_Control_fp; |
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107 | |
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108 | /* |
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109 | * The following structure defines the set of information saved |
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110 | * on the current stack by RTEMS upon receipt of each interrupt. |
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111 | */ |
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112 | |
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113 | typedef struct { |
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114 | unsigned32 TBD; /* XXX Fix for this CPU */ |
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115 | } CPU_Interrupt_frame; |
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116 | |
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117 | /* |
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118 | * The following table contains the information required to configure |
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119 | * the m68k specific parameters. |
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120 | */ |
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121 | |
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122 | typedef struct { |
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123 | void (*pretasking_hook)( void ); |
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124 | void (*predriver_hook)( void ); |
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125 | void (*postdriver_hook)( void ); |
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126 | void (*idle_task)( void ); |
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127 | boolean do_zero_of_workspace; |
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128 | unsigned32 interrupt_stack_size; |
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129 | unsigned32 extra_system_initialization_stack; |
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130 | m68k_isr *interrupt_vector_table; |
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131 | } rtems_cpu_table; |
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132 | |
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133 | /* variables */ |
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134 | |
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135 | EXTERN void *_CPU_Interrupt_stack_low; |
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136 | EXTERN void *_CPU_Interrupt_stack_high; |
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137 | |
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138 | /* constants */ |
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139 | |
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140 | /* |
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141 | * This defines the number of levels and the mask used to pick those |
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142 | * bits out of a thread mode. |
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143 | */ |
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144 | |
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145 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ |
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146 | #define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ |
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147 | |
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148 | /* |
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149 | * context size area for floating point |
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150 | */ |
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151 | |
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152 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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153 | |
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154 | /* |
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155 | * extra stack required by system initialization thread |
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156 | */ |
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157 | |
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158 | #define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 1024 |
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159 | |
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160 | /* |
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161 | * m68k family supports 256 distinct vectors. |
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162 | */ |
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163 | |
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164 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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165 | |
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166 | /* |
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167 | * Minimum size of a thread's stack. |
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168 | * |
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169 | * NOTE: 256 bytes is probably too low in most cases. |
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170 | */ |
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171 | |
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172 | #define CPU_STACK_MINIMUM_SIZE 256 |
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173 | |
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174 | /* |
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175 | * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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176 | */ |
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177 | |
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178 | #define CPU_ALIGNMENT 4 |
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179 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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180 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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181 | |
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182 | /* |
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183 | * On m68k thread stacks require no further alignment after allocation |
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184 | * from the Workspace. |
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185 | */ |
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186 | |
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187 | #define CPU_STACK_ALIGNMENT 0 |
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188 | |
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189 | /* macros */ |
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190 | |
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191 | /* |
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192 | * ISR handler macros |
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193 | * |
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194 | * These macros perform the following functions: |
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195 | * + disable all maskable CPU interrupts |
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196 | * + restore previous interrupt level (enable) |
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197 | * + temporarily restore interrupts (flash) |
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198 | * + set a particular level |
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199 | */ |
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200 | |
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201 | #define _CPU_ISR_Disable( _level ) \ |
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202 | m68k_disable_interrupts( _level ) |
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203 | |
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204 | #define _CPU_ISR_Enable( _level ) \ |
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205 | m68k_enable_interrupts( _level ) |
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206 | |
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207 | #define _CPU_ISR_Flash( _level ) \ |
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208 | m68k_flash_interrupts( _level ) |
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209 | |
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210 | #define _CPU_ISR_Set_level( _newlevel ) \ |
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211 | m68k_set_interrupt_level( _newlevel ) |
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212 | |
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213 | /* end of ISR handler macros */ |
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214 | |
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215 | /* |
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216 | * Context handler macros |
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217 | * |
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218 | * These macros perform the following functions: |
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219 | * + initialize a context area |
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220 | * + restart the current thread |
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221 | * + calculate the initial pointer into a FP context area |
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222 | * + initialize an FP context area |
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223 | */ |
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224 | |
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225 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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226 | _isr, _entry_point ) \ |
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227 | do { \ |
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228 | void *_stack; \ |
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229 | \ |
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230 | (_the_context)->sr = 0x3000 | ((_isr) << 8); \ |
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231 | _stack = (void *)(_stack_base) + (_size) - 4; \ |
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232 | (_the_context)->a7_msp = _stack; \ |
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233 | *(void **)_stack = (_entry_point); \ |
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234 | } while ( 0 ) |
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235 | |
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236 | #define _CPU_Context_Restart_self( _the_context ) \ |
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237 | { asm volatile( "movew %0,%%sr ; " \ |
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238 | "moval %1,%%a7 ; " \ |
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239 | "rts" \ |
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240 | : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \ |
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241 | : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \ |
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242 | } |
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243 | |
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244 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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245 | ((void *) \ |
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246 | _Addresses_Add_offset( \ |
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247 | (_base), \ |
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248 | (_offset) + CPU_CONTEXT_FP_SIZE - 4 \ |
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249 | ) \ |
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250 | ) |
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251 | |
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252 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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253 | { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \ |
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254 | \ |
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255 | *(--(_fp_context)) = 0; \ |
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256 | *(_fp_area) = (unsigned8 *)(_fp_context); \ |
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257 | } |
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258 | |
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259 | /* end of Context handler macros */ |
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260 | |
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261 | /* |
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262 | * Fatal Error manager macros |
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263 | * |
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264 | * These macros perform the following functions: |
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265 | * + disable interrupts and halt the CPU |
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266 | */ |
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267 | |
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268 | #define _CPU_Fatal_halt( _error ) \ |
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269 | { asm volatile( "movl %0,%%d0; " \ |
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270 | "orw #0x0700,%%sr; " \ |
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271 | "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ |
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272 | } |
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273 | |
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274 | /* end of Fatal Error manager macros */ |
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275 | |
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276 | /* |
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277 | * Bitfield handler macros |
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278 | * |
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279 | * These macros perform the following functions: |
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280 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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281 | * |
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282 | * NOTE: |
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283 | * |
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284 | * It appears that on the M68020 bitfield are always 32 bits wide |
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285 | * when in a register. This code forces the bitfield to be in |
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286 | * memory (it really always is anyway). This allows us to |
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287 | * have a real 16 bit wide bitfield which operates "correctly." |
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288 | */ |
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289 | |
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290 | #if ( M68K_HAS_BFFFO == 1 ) |
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291 | #ifdef NO_UNINITIALIZED_WARNINGS |
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292 | |
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293 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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294 | { \ |
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295 | register void *__base = (void *)&(_value); \ |
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296 | \ |
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297 | (_output) = 0; /* avoids warnings */ \ |
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298 | asm volatile( "bfffo (%0),#0,#16,%1" \ |
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299 | : "=a" (__base), "=d" ((_output)) \ |
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300 | : "0" (__base), "1" ((_output)) ) ; \ |
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301 | } |
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302 | #else |
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303 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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304 | { \ |
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305 | register void *__base = (void *)&(_value); \ |
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306 | \ |
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307 | asm volatile( "bfffo (%0),#0,#16,%1" \ |
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308 | : "=a" (__base), "=d" ((_output)) \ |
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309 | : "0" (__base), "1" ((_output)) ) ; \ |
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310 | } |
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311 | #endif |
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312 | |
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313 | #else |
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314 | |
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315 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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316 | (_output) = 0 /* avoids warnings */ |
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317 | |
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318 | #warning "FIX ME... NEEDS A SOFTWARE BFFFO IMPLEMENTATION" |
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319 | #warning "SEE no_cpu/cpu.h FOR POSSIBLE ALGORITHMS" |
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320 | |
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321 | #endif |
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322 | |
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323 | /* end of Bitfield handler macros */ |
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324 | |
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325 | /* |
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326 | * Priority handler macros |
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327 | * |
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328 | * These macros perform the following functions: |
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329 | * + return a mask with the bit for this major/minor portion of |
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330 | * of thread priority set. |
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331 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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332 | * into an index into the thread ready chain bit maps |
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333 | */ |
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334 | |
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335 | #define _CPU_Priority_Mask( _bit_number ) \ |
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336 | ( 0x8000 >> (_bit_number) ) |
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337 | |
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338 | #define _CPU_Priority_Bits_index( _priority ) \ |
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339 | (_priority) |
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340 | |
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341 | /* end of Priority handler macros */ |
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342 | |
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343 | /* functions */ |
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344 | |
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345 | /* |
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346 | * _CPU_Initialize |
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347 | * |
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348 | * This routine performs CPU dependent initialization. |
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349 | */ |
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350 | |
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351 | void _CPU_Initialize( |
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352 | rtems_cpu_table *cpu_table, |
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353 | void (*thread_dispatch) |
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354 | ); |
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355 | |
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356 | /* |
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357 | * _CPU_ISR_install_vector |
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358 | * |
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359 | * This routine installs an interrupt vector. |
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360 | */ |
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361 | |
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362 | void _CPU_ISR_install_vector( |
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363 | unsigned32 vector, |
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364 | proc_ptr new_handler, |
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365 | proc_ptr *old_handler |
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366 | ); |
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367 | |
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368 | /* |
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369 | * _CPU_Install_interrupt_stack |
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370 | * |
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371 | * This routine installs the hardware interrupt stack pointer. |
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372 | */ |
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373 | |
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374 | void _CPU_Install_interrupt_stack( void ); |
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375 | |
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376 | /* |
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377 | * _CPU_Context_switch |
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378 | * |
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379 | * This routine switches from the run context to the heir context. |
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380 | */ |
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381 | |
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382 | void _CPU_Context_switch( |
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383 | Context_Control *run, |
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384 | Context_Control *heir |
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385 | ); |
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386 | |
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387 | /* |
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388 | * _CPU_Context_save_fp |
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389 | * |
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390 | * This routine saves the floating point context passed to it. |
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391 | */ |
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392 | |
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393 | void _CPU_Context_restore_fp( |
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394 | void **fp_context_ptr |
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395 | ); |
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396 | |
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397 | /* |
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398 | * _CPU_Context_restore_fp |
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399 | * |
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400 | * This routine restores the floating point context passed to it. |
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401 | */ |
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402 | |
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403 | void _CPU_Context_save_fp( |
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404 | void **fp_context_ptr |
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405 | ); |
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406 | |
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407 | #ifdef __cplusplus |
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408 | } |
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409 | #endif |
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410 | |
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411 | #endif |
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412 | /* end of include file */ |
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