source: rtems/c/src/exec/score/cpu/m68k/cpu.h @ 937a6f3c

4.104.114.84.95
Last change on this file since 937a6f3c was 937a6f3c, checked in by Joel Sherrill <joel.sherrill@…>, on 06/03/98 at 19:00:17

Added CPU_ISR_PASSES_FRAME_POINTER so some ports could pass just the
vector number to user ISR's and other ports could pass both the vector
number and a pointer to the ISF.

  • Property mode set to 100644
File size: 15.9 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/m68k.h>              /* pick up machine definitions */
25#ifndef ASM
26#include <rtems/score/m68ktypes.h>
27#endif
28
29/* conditional compilation parameters */
30
31#define CPU_INLINE_ENABLE_DISPATCH       TRUE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  Use the m68k's hardware interrupt stack support and have the
36 *  interrupt manager allocate the memory for it.
37 */
38
39#if ( M68K_HAS_SEPARATE_STACKS == 1)
40#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
41#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
42#define CPU_ALLOCATE_INTERRUPT_STACK     1
43#else
44#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
45#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
46#define CPU_ALLOCATE_INTERRUPT_STACK     1
47#endif
48
49/*
50 *  Does the RTEMS invoke the user's ISR with the vector number and
51 *  a pointer to the saved interrupt frame (1) or just the vector
52 *  number (0)?
53 */
54
55#define CPU_ISR_PASSES_FRAME_POINTER 0
56
57/*
58 *  Some family members have no FP, some have an FPU such as the
59 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
60 *
61 *  NOTE:  If on a CPU without hardware FP, then one can use software
62 *         emulation.  The gcc software FP emulation code has data which
63 *         must be contexted switched on a per task basis.
64 */
65
66#if ( M68K_HAS_FPU == 1 )
67#define CPU_HARDWARE_FP     TRUE
68#define CPU_SOFTWARE_FP     FALSE
69#else
70#define CPU_HARDWARE_FP     FALSE
71#if defined(__GCC__)
72#define CPU_SOFTWARE_FP     TRUE
73#else
74#define CPU_SOFTWARE_FP     FALSE
75#endif
76#endif
77
78/*
79 *  All tasks are not by default floating point tasks on this CPU.
80 *  The IDLE task does not have a floating point context on this CPU.
81 *  It is safe to use the deferred floating point context switch
82 *  algorithm on this CPU.
83 */
84
85#define CPU_ALL_TASKS_ARE_FP             FALSE
86#define CPU_IDLE_TASK_IS_FP              FALSE
87#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
88
89#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
90#define CPU_STACK_GROWS_UP               FALSE
91#define CPU_STRUCTURE_ALIGNMENT
92
93/*
94 *  Define what is required to specify how the network to host conversion
95 *  routines are handled.
96 */
97
98#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
99#define CPU_BIG_ENDIAN                           TRUE
100#define CPU_LITTLE_ENDIAN                        FALSE
101
102#ifndef ASM
103/* structures */
104
105/*
106 *  Basic integer context for the m68k family.
107 */
108
109typedef struct {
110  unsigned32  sr;                /* (sr) status register */
111  unsigned32  d2;                /* (d2) data register 2 */
112  unsigned32  d3;                /* (d3) data register 3 */
113  unsigned32  d4;                /* (d4) data register 4 */
114  unsigned32  d5;                /* (d5) data register 5 */
115  unsigned32  d6;                /* (d6) data register 6 */
116  unsigned32  d7;                /* (d7) data register 7 */
117  void       *a2;                /* (a2) address register 2 */
118  void       *a3;                /* (a3) address register 3 */
119  void       *a4;                /* (a4) address register 4 */
120  void       *a5;                /* (a5) address register 5 */
121  void       *a6;                /* (a6) address register 6 */
122  void       *a7_msp;            /* (a7) master stack pointer */
123}   Context_Control;
124
125/*
126 *  Floating point context ares
127 */
128
129#if (CPU_SOFTWARE_FP == TRUE)
130
131/*
132 *  This is the same as gcc's view of the software FP condition code
133 *  register _fpCCR.  The implementation of the emulation code is
134 *  in the gcc-VERSION/config/m68k directory.  This structure is
135 *  correct as of gcc 2.7.2.2.
136 */
137
138typedef struct {
139  unsigned16   _exception_bits;
140  unsigned16   _trap_enable_bits;
141  unsigned16   _sticky_bits;
142  unsigned16   _rounding_mode;
143  unsigned16   _format;
144  unsigned16   _last_operation;
145  union {
146    float sf;
147    double df;
148  } _operand1;
149  union {
150    float sf;
151    double df;
152  } _operand2;
153} Context_Control_fp;
154
155#else
156
157/*
158 *  FP context save area for the M68881/M68882 numeric coprocessors.
159 */
160
161typedef struct {
162  unsigned8   fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
163                                    /*    96 bytes for FMOVEM FP0-7      */
164                                    /*    12 bytes for FMOVEM CREGS      */
165                                    /*     4 bytes for non-null flag     */
166} Context_Control_fp;
167#endif
168
169/*
170 *  The following structure defines the set of information saved
171 *  on the current stack by RTEMS upon receipt of each interrupt.
172 */
173
174typedef struct {
175  unsigned32   TBD;   /* XXX Fix for this CPU */
176} CPU_Interrupt_frame;
177
178/*
179 *  The following table contains the information required to configure
180 *  the m68k specific parameters.
181 */
182
183typedef struct {
184  void       (*pretasking_hook)( void );
185  void       (*predriver_hook)( void );
186  void       (*postdriver_hook)( void );
187  void       (*idle_task)( void );
188  boolean      do_zero_of_workspace;
189  unsigned32   interrupt_stack_size;
190  unsigned32   extra_mpci_receive_server_stack;
191  void *     (*stack_allocate_hook)( unsigned32 );
192  void       (*stack_free_hook)( void* );
193  /* end of fields required on all CPUs */
194
195  m68k_isr    *interrupt_vector_table;
196}   rtems_cpu_table;
197
198/* variables */
199
200SCORE_EXTERN void                   *_CPU_Interrupt_stack_low;
201SCORE_EXTERN void                   *_CPU_Interrupt_stack_high;
202
203extern char                         _VBR[];
204
205#if ( M68K_HAS_VBR == 0 )
206
207/*
208 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
209 * pushed onto the stack. This is not is the same order as VBR processors.
210 * The ISR handler takes the format and uses it for dispatching the user
211 * handler.
212 *
213 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
214 *
215 */
216
217typedef struct {
218  unsigned16 move_a7;            /* move #FORMAT_ID,%a7@- */
219  unsigned16 format_id;
220  unsigned16 jmp;                /* jmp  _ISR_Handlers */
221  unsigned32 isr_handler;
222} _CPU_ISR_handler_entry;
223
224#define M68K_MOVE_A7 0x3F3C
225#define M68K_JMP     0x4EF9
226
227      /* points to jsr-exception-table in targets wo/ VBR register */
228SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
229
230#endif /* M68K_HAS_VBR */
231#endif /* ASM */
232
233/* constants */
234
235/*
236 *  This defines the number of levels and the mask used to pick those
237 *  bits out of a thread mode.
238 */
239
240#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
241#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
242
243/*
244 *  context size area for floating point
245 */
246
247#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
248
249/*
250 *  extra stack required by the MPCI receive server thread
251 */
252
253#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
254
255/*
256 *  m68k family supports 256 distinct vectors.
257 */
258
259#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
260#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
261
262/*
263 *  Minimum size of a thread's stack.
264 */
265
266#define CPU_STACK_MINIMUM_SIZE           2048
267
268/*
269 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
270 */
271
272#define CPU_ALIGNMENT                    4
273#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
274#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
275
276/*
277 *  On m68k thread stacks require no further alignment after allocation
278 *  from the Workspace.
279 */
280
281#define CPU_STACK_ALIGNMENT        0
282
283#ifndef ASM
284
285/* macros */
286
287/*
288 *  ISR handler macros
289 *
290 *  These macros perform the following functions:
291 *     + disable all maskable CPU interrupts
292 *     + restore previous interrupt level (enable)
293 *     + temporarily restore interrupts (flash)
294 *     + set a particular level
295 */
296
297#define _CPU_ISR_Disable( _level ) \
298  m68k_disable_interrupts( _level )
299
300#define _CPU_ISR_Enable( _level ) \
301  m68k_enable_interrupts( _level )
302
303#define _CPU_ISR_Flash( _level ) \
304  m68k_flash_interrupts( _level )
305
306#define _CPU_ISR_Set_level( _newlevel ) \
307   m68k_set_interrupt_level( _newlevel )
308
309unsigned32 _CPU_ISR_Get_level( void );
310
311/* end of ISR handler macros */
312
313/*
314 *  Context handler macros
315 *
316 *  These macros perform the following functions:
317 *     + initialize a context area
318 *     + restart the current thread
319 *     + calculate the initial pointer into a FP context area
320 *     + initialize an FP context area
321 */
322
323#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
324                                 _isr, _entry_point, _is_fp ) \
325   do { \
326     unsigned32 _stack; \
327     \
328     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
329     _stack                  = (unsigned32)(_stack_base) + (_size) - 4; \
330     (_the_context)->a7_msp  = (void *)_stack; \
331     *(void **)_stack        = (void *)(_entry_point); \
332   } while ( 0 )
333
334#define _CPU_Context_Restart_self( _the_context ) \
335  { asm volatile( "movew %0,%%sr ; " \
336                  "moval %1,%%a7 ; " \
337                  "rts"  \
338        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
339        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
340  }
341
342/*
343 *  Floating Point Context Area Support routines
344 */
345
346#if (CPU_SOFTWARE_FP == TRUE)
347
348/*
349 *  This software FP implementation is only for GCC.
350 */
351
352#define _CPU_Context_Fp_start( _base, _offset ) \
353   ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
354
355
356#define _CPU_Context_Initialize_fp( _fp_area ) \
357   { \
358   Context_Control_fp *_fp; \
359   _fp = *(Context_Control_fp **)_fp_area; \
360   _fp->_exception_bits = 0; \
361   _fp->_trap_enable_bits = 0; \
362   _fp->_sticky_bits = 0; \
363   _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
364   _fp->_format = 0;         /* NIL */ \
365   _fp->_last_operation = 0;  /* NOOP */ \
366   _fp->_operand1.df = 0; \
367   _fp->_operand2.df = 0; \
368   }
369#else
370#define _CPU_Context_Fp_start( _base, _offset ) \
371   ((void *) \
372     _Addresses_Add_offset( \
373        (_base), \
374        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
375     ) \
376   )
377
378#define _CPU_Context_Initialize_fp( _fp_area ) \
379   { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
380     \
381     *(--(_fp_context)) = 0; \
382     *(_fp_area) = (unsigned8 *)(_fp_context); \
383   }
384#endif
385
386/* end of Context handler macros */
387
388/*
389 *  Fatal Error manager macros
390 *
391 *  These macros perform the following functions:
392 *    + disable interrupts and halt the CPU
393 */
394
395#define _CPU_Fatal_halt( _error ) \
396  { asm volatile( "movl  %0,%%d0; " \
397                  "orw   #0x0700,%%sr; " \
398                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
399  }
400
401/* end of Fatal Error manager macros */
402
403/*
404 *  Bitfield handler macros
405 *
406 *  These macros perform the following functions:
407 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
408 *
409 *  NOTE:
410 *
411 *    It appears that on the M68020 bitfield are always 32 bits wide
412 *    when in a register.  This code forces the bitfield to be in
413 *    memory (it really always is anyway). This allows us to
414 *    have a real 16 bit wide bitfield which operates "correctly."
415 */
416
417#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
418#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
419
420#if ( M68K_HAS_BFFFO == 1 )
421
422#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
423  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
424#else
425
426/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
427   _CPU_Priority_bits_index is not needed), handles the 0 case, and
428   does not molest _value -- jsg */
429#if ( M68K_HAS_EXTB_L == 1 )
430#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
431  { \
432    extern const unsigned char __BFFFOtable[256]; \
433    register int dumby; \
434    \
435    asm volatile ( "   move.w  %2,%1\n"        \
436       "   lsr.w   #8,%1\n"        \
437       "   beq.s   1f\n"           \
438       "   move.b  (%3,%1.w),%0\n" \
439       "   extb.l  %0\n"           \
440       "   bra.s   0f\n"           \
441       "1: moveq.l #8,%0\n"        \
442       "   add.b   (%3,%2.w),%0\n" \
443       "0:\n"                      \
444       : "=&d" ((_output)), "=&d" ((dumby)) \
445       : "d" ((_value)), "ao" ((__BFFFOtable)) \
446       : "cc" ) ; \
447  }
448#else
449#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
450  { \
451    extern const unsigned char __BFFFOtable[256]; \
452    register int dumby; \
453    \
454    asm volatile ( "   move.w  %2,%1\n"        \
455       "   lsr.w   #8,%1\n"        \
456       "   beq.s   1f\n"           \
457       "   move.b  (%3,%1.w),%0\n" \
458       "   and.l   #0x000000ff,%0\n"\
459       "   bra.s   0f\n"           \
460       "1: moveq.l #8,%0\n"        \
461       "   add.b   (%3,%2.w),%0\n" \
462       "0:\n"                      \
463       : "=&d" ((_output)), "=&d" ((dumby)) \
464       : "d" ((_value)), "ao" ((__BFFFOtable)) \
465       : "cc" ) ; \
466  }
467#endif /* M68K_HAS_EXTB_L */
468
469#endif
470
471/* end of Bitfield handler macros */
472
473/*
474 *  Priority handler macros
475 *
476 *  These macros perform the following functions:
477 *    + return a mask with the bit for this major/minor portion of
478 *      of thread priority set.
479 *    + translate the bit number returned by "Bitfield_find_first_bit"
480 *      into an index into the thread ready chain bit maps
481 */
482
483#define _CPU_Priority_Mask( _bit_number ) \
484  ( 0x8000 >> (_bit_number) )
485
486#define _CPU_Priority_bits_index( _priority ) \
487  (_priority)
488
489/* end of Priority handler macros */
490
491/* functions */
492
493/*
494 *  _CPU_Initialize
495 *
496 *  This routine performs CPU dependent initialization.
497 */
498
499void _CPU_Initialize(
500  rtems_cpu_table  *cpu_table,
501  void      (*thread_dispatch)
502);
503
504/*
505 *  _CPU_ISR_install_raw_handler
506 *
507 *  This routine installs a "raw" interrupt handler directly into the
508 *  processor's vector table.
509 */
510 
511void _CPU_ISR_install_raw_handler(
512  unsigned32  vector,
513  proc_ptr    new_handler,
514  proc_ptr   *old_handler
515);
516
517/*
518 *  _CPU_ISR_install_vector
519 *
520 *  This routine installs an interrupt vector.
521 */
522
523void _CPU_ISR_install_vector(
524  unsigned32       vector,
525  proc_ptr         new_handler,
526  proc_ptr        *old_handler
527);
528
529/*
530 *  _CPU_Install_interrupt_stack
531 *
532 *  This routine installs the hardware interrupt stack pointer.
533 */
534
535void _CPU_Install_interrupt_stack( void );
536
537/*
538 *  _CPU_Context_switch
539 *
540 *  This routine switches from the run context to the heir context.
541 */
542
543void _CPU_Context_switch(
544  Context_Control  *run,
545  Context_Control  *heir
546);
547
548/*
549 *  _CPU_Context_save_fp
550 *
551 *  This routine saves the floating point context passed to it.
552 */
553
554void _CPU_Context_save_fp(
555  void **fp_context_ptr
556);
557
558/*
559 *  _CPU_Context_restore_fp
560 *
561 *  This routine restores the floating point context passed to it.
562 */
563
564void _CPU_Context_restore_fp(
565  void **fp_context_ptr
566);
567
568#if (M68K_HAS_FPSP_PACKAGE == 1)
569/*
570 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
571 *
572 *  NOTES: 
573 *
574 *  Motorola 68k family CPU's before the 68040 used a coprocessor
575 *  (68881 or 68882) to handle floating point.  The 68040 has internal
576 *  floating point support -- but *not* the complete support provided by
577 *  the 68881 or 68882.  The leftover functions are taken care of by the
578 *  M68040 Floating Point Support Package.  Quoting from the MC68040
579 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
580 *
581 *    "When used with the M68040FPSP, the MC68040 FPU is fully
582 *    compliant with IEEE floating-point standards."
583 *
584 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
585 *  is invoked early in the application code to insure that proper FP
586 *  behavior is installed.  This is not left to the BSP to call, since
587 *  this would force all applications using that BSP to use FPSP which
588 *  is not necessarily desirable.
589 *
590 *  There is a similar package for the 68060 but RTEMS does not yet
591 *  support the 68060.
592 */
593
594void M68KFPSPInstallExceptionHandlers (void);
595
596SCORE_EXTERN int (*_FPSP_install_raw_handler)(
597  unsigned32 vector,
598  proc_ptr new_handler,
599  proc_ptr *old_handler
600);
601
602#endif
603
604
605#endif
606
607#ifdef __cplusplus
608}
609#endif
610
611#endif
612/* end of include file */
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