source: rtems/c/src/exec/score/cpu/m68k/cpu.h @ 88d594a

4.104.114.84.95
Last change on this file since 88d594a was 88d594a, checked in by Joel Sherrill <joel.sherrill@…>, on May 24, 1995 at 9:39:42 PM

Fully tested on all in-house targets

  • Property mode set to 100644
File size: 10.5 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  If defined, this causes some of the macros to initialize their
26 *  variables to zero before doing inline assembly.  This gets rid
27 *  of compile time warnings at the cost of a little execution time
28 *  in some time critical routines.
29 */
30
31#define NO_UNINITIALIZED_WARNINGS
32
33#include <rtems/m68k.h>
34#ifndef ASM
35#include <rtems/m68ktypes.h>
36#endif
37
38/* conditional compilation parameters */
39
40#define CPU_INLINE_ENABLE_DISPATCH       TRUE
41#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
42
43/*
44 *  Use the m68k's hardware interrupt stack support and have the
45 *  interrupt manager allocate the memory for it.
46 */
47
48#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
49#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
50#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
51
52/*
53 *  Some family members have no FP, some have an FPU such as the
54 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
55 */
56
57#if ( M68K_HAS_FPU == 1 )
58#define CPU_HARDWARE_FP     TRUE
59#else
60#define CPU_HARDWARE_FP     FALSE
61#endif
62
63/*
64 *  All tasks are not by default floating point tasks on this CPU.
65 *  The IDLE task does not have a floating point context on this CPU.
66 *  It is safe to use the deferred floating point context switch
67 *  algorithm on this CPU.
68 */
69
70#define CPU_ALL_TASKS_ARE_FP             FALSE
71#define CPU_IDLE_TASK_IS_FP              FALSE
72#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
73
74#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
75#define CPU_STACK_GROWS_UP               FALSE
76#define CPU_STRUCTURE_ALIGNMENT
77
78/* structures */
79
80/*
81 *  Basic integer context for the m68k family.
82 */
83
84typedef struct {
85  unsigned32  sr;                /* (sr) status register */
86  unsigned32  d2;                /* (d2) data register 2 */
87  unsigned32  d3;                /* (d3) data register 3 */
88  unsigned32  d4;                /* (d4) data register 4 */
89  unsigned32  d5;                /* (d5) data register 5 */
90  unsigned32  d6;                /* (d6) data register 6 */
91  unsigned32  d7;                /* (d7) data register 7 */
92  void       *a2;                /* (a2) address register 2 */
93  void       *a3;                /* (a3) address register 3 */
94  void       *a4;                /* (a4) address register 4 */
95  void       *a5;                /* (a5) address register 5 */
96  void       *a6;                /* (a6) address register 6 */
97  void       *a7_msp;            /* (a7) master stack pointer */
98}   Context_Control;
99
100/*
101 *  FP context save area for the M68881/M68882 numeric coprocessors.
102 */
103
104typedef struct {
105  unsigned8   fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
106                                    /*    96 bytes for FMOVEM FP0-7      */
107                                    /*    12 bytes for FMOVEM CREGS      */
108                                    /*     4 bytes for non-null flag     */
109} Context_Control_fp;
110
111/*
112 *  The following structure defines the set of information saved
113 *  on the current stack by RTEMS upon receipt of each interrupt.
114 */
115
116typedef struct {
117  unsigned32   TBD;   /* XXX Fix for this CPU */
118} CPU_Interrupt_frame;
119
120/*
121 *  The following table contains the information required to configure
122 *  the m68k specific parameters.
123 */
124
125typedef struct {
126  void       (*pretasking_hook)( void );
127  void       (*predriver_hook)( void );
128  void       (*postdriver_hook)( void );
129  void       (*idle_task)( void );
130  boolean      do_zero_of_workspace;
131  unsigned32   interrupt_stack_size;
132  unsigned32   extra_system_initialization_stack;
133  m68k_isr    *interrupt_vector_table;
134}   rtems_cpu_table;
135
136/* variables */
137
138EXTERN void               *_CPU_Interrupt_stack_low;
139EXTERN void               *_CPU_Interrupt_stack_high;
140
141/* constants */
142
143/*
144 *  This defines the number of levels and the mask used to pick those
145 *  bits out of a thread mode.
146 */
147
148#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
149#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
150
151/*
152 *  context size area for floating point
153 */
154
155#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
156
157/*
158 *  extra stack required by system initialization thread
159 */
160
161#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 1024
162
163/*
164 *  m68k family supports 256 distinct vectors.
165 */
166
167#define CPU_INTERRUPT_NUMBER_OF_VECTORS  256
168
169/*
170 *  Minimum size of a thread's stack.
171 *
172 *  NOTE:  256 bytes is probably too low in most cases.
173 */
174
175#define CPU_STACK_MINIMUM_SIZE           256
176
177/*
178 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
179 */
180
181#define CPU_ALIGNMENT                    4
182#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
183#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
184
185/*
186 *  On m68k thread stacks require no further alignment after allocation
187 *  from the Workspace.
188 */
189
190#define CPU_STACK_ALIGNMENT        0
191
192/* macros */
193
194/*
195 *  ISR handler macros
196 *
197 *  These macros perform the following functions:
198 *     + disable all maskable CPU interrupts
199 *     + restore previous interrupt level (enable)
200 *     + temporarily restore interrupts (flash)
201 *     + set a particular level
202 */
203
204#define _CPU_ISR_Disable( _level ) \
205  m68k_disable_interrupts( _level )
206
207#define _CPU_ISR_Enable( _level ) \
208  m68k_enable_interrupts( _level )
209
210#define _CPU_ISR_Flash( _level ) \
211  m68k_flash_interrupts( _level )
212
213#define _CPU_ISR_Set_level( _newlevel ) \
214   m68k_set_interrupt_level( _newlevel )
215
216/* end of ISR handler macros */
217
218/*
219 *  Context handler macros
220 *
221 *  These macros perform the following functions:
222 *     + initialize a context area
223 *     + restart the current thread
224 *     + calculate the initial pointer into a FP context area
225 *     + initialize an FP context area
226 */
227
228#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
229                                 _isr, _entry_point ) \
230   do { \
231     void   *_stack; \
232     \
233     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
234     _stack                  = (void *)(_stack_base) + (_size) - 4; \
235     (_the_context)->a7_msp  = _stack; \
236     *(void **)_stack = (_entry_point); \
237   } while ( 0 )
238
239#define _CPU_Context_Restart_self( _the_context ) \
240  { asm volatile( "movew %0,%%sr ; " \
241                  "moval %1,%%a7 ; " \
242                  "rts"  \
243        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
244        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
245  }
246
247#define _CPU_Context_Fp_start( _base, _offset ) \
248   ((void *) \
249     _Addresses_Add_offset( \
250        (_base), \
251        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
252     ) \
253   )
254
255#define _CPU_Context_Initialize_fp( _fp_area ) \
256   { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
257     \
258     *(--(_fp_context)) = 0; \
259     *(_fp_area) = (unsigned8 *)(_fp_context); \
260   }
261
262/* end of Context handler macros */
263
264/*
265 *  Fatal Error manager macros
266 *
267 *  These macros perform the following functions:
268 *    + disable interrupts and halt the CPU
269 */
270
271#define _CPU_Fatal_halt( _error ) \
272  { asm volatile( "movl  %0,%%d0; " \
273                  "orw   #0x0700,%%sr; " \
274                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
275  }
276
277/* end of Fatal Error manager macros */
278
279/*
280 *  Bitfield handler macros
281 *
282 *  These macros perform the following functions:
283 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
284 *
285 *  NOTE:
286 *
287 *    It appears that on the M68020 bitfield are always 32 bits wide
288 *    when in a register.  This code forces the bitfield to be in
289 *    memory (it really always is anyway). This allows us to
290 *    have a real 16 bit wide bitfield which operates "correctly."
291 */
292
293#if ( M68K_HAS_BFFFO == 1 )
294#ifdef NO_UNINITIALIZED_WARNINGS
295
296#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
297  { \
298    register void *__base = (void *)&(_value); \
299    \
300    (_output) = 0;  /* avoids warnings */ \
301    asm volatile( "bfffo (%0),#0,#16,%1" \
302                   : "=a" (__base), "=d" ((_output)) \
303                   : "0"  (__base), "1" ((_output))  ) ; \
304  }
305#else
306#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
307  { \
308    register void *__base = (void *)&(_value); \
309    \
310    asm volatile( "bfffo (%0),#0,#16,%1" \
311                   : "=a" (__base), "=d" ((_output)) \
312                   : "0"  (__base), "1" ((_output))  ) ; \
313  }
314#endif
315
316#else
317
318#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
319  (_output) = 0   /* avoids warnings */
320
321#warning "FIX ME... NEEDS A SOFTWARE BFFFO IMPLEMENTATION"
322#warning "SEE no_cpu/cpu.h FOR POSSIBLE ALGORITHMS"
323
324#endif
325
326/* end of Bitfield handler macros */
327
328/*
329 *  Priority handler macros
330 *
331 *  These macros perform the following functions:
332 *    + return a mask with the bit for this major/minor portion of
333 *      of thread priority set.
334 *    + translate the bit number returned by "Bitfield_find_first_bit"
335 *      into an index into the thread ready chain bit maps
336 */
337
338#define _CPU_Priority_Mask( _bit_number ) \
339  ( 0x8000 >> (_bit_number) )
340
341#define _CPU_Priority_Bits_index( _priority ) \
342  (_priority)
343
344/* end of Priority handler macros */
345
346/* functions */
347
348/*
349 *  _CPU_Initialize
350 *
351 *  This routine performs CPU dependent initialization.
352 */
353
354void _CPU_Initialize(
355  rtems_cpu_table  *cpu_table,
356  void      (*thread_dispatch)
357);
358
359/*
360 *  _CPU_ISR_install_vector
361 *
362 *  This routine installs an interrupt vector.
363 */
364
365void _CPU_ISR_install_vector(
366  unsigned32       vector,
367  proc_ptr         new_handler,
368  proc_ptr        *old_handler
369);
370
371/*
372 *  _CPU_Install_interrupt_stack
373 *
374 *  This routine installs the hardware interrupt stack pointer.
375 */
376
377void _CPU_Install_interrupt_stack( void );
378
379/*
380 *  _CPU_Context_switch
381 *
382 *  This routine switches from the run context to the heir context.
383 */
384
385void _CPU_Context_switch(
386  Context_Control  *run,
387  Context_Control  *heir
388);
389
390/*
391 *  _CPU_Context_save_fp
392 *
393 *  This routine saves the floating point context passed to it.
394 */
395
396void _CPU_Context_restore_fp(
397  void **fp_context_ptr
398);
399
400/*
401 *  _CPU_Context_restore_fp
402 *
403 *  This routine restores the floating point context passed to it.
404 */
405
406void _CPU_Context_save_fp(
407  void **fp_context_ptr
408);
409
410#ifdef __cplusplus
411}
412#endif
413
414#endif
415/* end of include file */
Note: See TracBrowser for help on using the repository browser.