source: rtems/c/src/exec/score/cpu/m68k/cpu.h @ 860e77a

4.104.114.84.95
Last change on this file since 860e77a was 860e77a, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 29, 1997 at 12:09:49 AM

Fixed comments.

Fixed so this file can be included from assembly code.

  • Property mode set to 100644
File size: 12.8 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/m68k.h>              /* pick up machine definitions */
25#ifndef ASM
26#include <rtems/score/m68ktypes.h>
27#endif
28
29/* conditional compilation parameters */
30
31#define CPU_INLINE_ENABLE_DISPATCH       TRUE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  Use the m68k's hardware interrupt stack support and have the
36 *  interrupt manager allocate the memory for it.
37 *
38 *  NOTE:  The definitions when M68K_HAS_SEPARATE_STACKS is 0 should
39 *         change when the software interrupt stack support is implemented.
40 */
41
42#if ( M68K_HAS_SEPARATE_STACKS == 1)
43#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
44#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
45#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
46#else
47#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
48#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
49#define CPU_ALLOCATE_INTERRUPT_STACK     FALSE
50#endif
51
52/*
53 *  Some family members have no FP, some have an FPU such as the
54 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
55 */
56
57#if ( M68K_HAS_FPU == 1 )
58#define CPU_HARDWARE_FP     TRUE
59#else
60#define CPU_HARDWARE_FP     FALSE
61#endif
62
63/*
64 *  All tasks are not by default floating point tasks on this CPU.
65 *  The IDLE task does not have a floating point context on this CPU.
66 *  It is safe to use the deferred floating point context switch
67 *  algorithm on this CPU.
68 */
69
70#define CPU_ALL_TASKS_ARE_FP             FALSE
71#define CPU_IDLE_TASK_IS_FP              FALSE
72#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
73
74#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
75#define CPU_STACK_GROWS_UP               FALSE
76#define CPU_STRUCTURE_ALIGNMENT
77
78#ifndef ASM
79/* structures */
80
81/*
82 *  Basic integer context for the m68k family.
83 */
84
85typedef struct {
86  unsigned32  sr;                /* (sr) status register */
87  unsigned32  d2;                /* (d2) data register 2 */
88  unsigned32  d3;                /* (d3) data register 3 */
89  unsigned32  d4;                /* (d4) data register 4 */
90  unsigned32  d5;                /* (d5) data register 5 */
91  unsigned32  d6;                /* (d6) data register 6 */
92  unsigned32  d7;                /* (d7) data register 7 */
93  void       *a2;                /* (a2) address register 2 */
94  void       *a3;                /* (a3) address register 3 */
95  void       *a4;                /* (a4) address register 4 */
96  void       *a5;                /* (a5) address register 5 */
97  void       *a6;                /* (a6) address register 6 */
98  void       *a7_msp;            /* (a7) master stack pointer */
99}   Context_Control;
100
101/*
102 *  FP context save area for the M68881/M68882 numeric coprocessors.
103 */
104
105typedef struct {
106  unsigned8   fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
107                                    /*    96 bytes for FMOVEM FP0-7      */
108                                    /*    12 bytes for FMOVEM CREGS      */
109                                    /*     4 bytes for non-null flag     */
110} Context_Control_fp;
111
112/*
113 *  The following structure defines the set of information saved
114 *  on the current stack by RTEMS upon receipt of each interrupt.
115 */
116
117typedef struct {
118  unsigned32   TBD;   /* XXX Fix for this CPU */
119} CPU_Interrupt_frame;
120
121/*
122 *  The following table contains the information required to configure
123 *  the m68k specific parameters.
124 */
125
126typedef struct {
127  void       (*pretasking_hook)( void );
128  void       (*predriver_hook)( void );
129  void       (*postdriver_hook)( void );
130  void       (*idle_task)( void );
131  boolean      do_zero_of_workspace;
132  unsigned32   interrupt_stack_size;
133  unsigned32   extra_mpci_receive_server_stack;
134  void *     (*stack_allocate_hook)( unsigned32 );
135  void       (*stack_free_hook)( void* );
136  /* end of fields required on all CPUs */
137
138  m68k_isr    *interrupt_vector_table;
139}   rtems_cpu_table;
140
141/* variables */
142
143SCORE_EXTERN void                   *_CPU_Interrupt_stack_low;
144SCORE_EXTERN void                   *_CPU_Interrupt_stack_high;
145
146extern char                         _VBR[]; 
147
148#if ( M68K_HAS_VBR == 0 )
149
150/*
151 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
152 * pushed onto the stack. This is not is the same order as VBR processors.
153 * The ISR handler takes the format and uses it for dispatching the user
154 * handler.
155 *
156 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
157 *
158 */
159
160typedef struct {
161  unsigned16 move_a7;            /* move #FORMAT_ID,%a7@- */
162  unsigned16 format_id;
163  unsigned16 jmp;                /* jmp  _ISR_Handlers */
164  unsigned32 isr_handler;
165} _CPU_ISR_handler_entry;
166
167#define M68K_MOVE_A7 0x3F3C
168#define M68K_JMP     0x4EF9
169
170      /* points to jsr-exception-table in targets wo/ VBR register */
171SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; 
172
173#endif /* M68K_HAS_VBR */
174#endif /* ASM */
175
176/* constants */
177
178/*
179 *  This defines the number of levels and the mask used to pick those
180 *  bits out of a thread mode.
181 */
182
183#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
184#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
185
186/*
187 *  context size area for floating point
188 */
189
190#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
191
192/*
193 *  extra stack required by the MPCI receive server thread
194 */
195
196#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
197
198/*
199 *  m68k family supports 256 distinct vectors.
200 */
201
202#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
203#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
204
205/*
206 *  Minimum size of a thread's stack.
207 */
208
209#define CPU_STACK_MINIMUM_SIZE           2048
210
211/*
212 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
213 */
214
215#define CPU_ALIGNMENT                    4
216#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
217#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
218
219/*
220 *  On m68k thread stacks require no further alignment after allocation
221 *  from the Workspace.
222 */
223
224#define CPU_STACK_ALIGNMENT        0
225
226#ifndef ASM
227
228/* macros */
229
230/*
231 *  ISR handler macros
232 *
233 *  These macros perform the following functions:
234 *     + disable all maskable CPU interrupts
235 *     + restore previous interrupt level (enable)
236 *     + temporarily restore interrupts (flash)
237 *     + set a particular level
238 */
239
240#define _CPU_ISR_Disable( _level ) \
241  m68k_disable_interrupts( _level )
242
243#define _CPU_ISR_Enable( _level ) \
244  m68k_enable_interrupts( _level )
245
246#define _CPU_ISR_Flash( _level ) \
247  m68k_flash_interrupts( _level )
248
249#define _CPU_ISR_Set_level( _newlevel ) \
250   m68k_set_interrupt_level( _newlevel )
251
252unsigned32 _CPU_ISR_Get_level( void );
253
254/* end of ISR handler macros */
255
256/*
257 *  Context handler macros
258 *
259 *  These macros perform the following functions:
260 *     + initialize a context area
261 *     + restart the current thread
262 *     + calculate the initial pointer into a FP context area
263 *     + initialize an FP context area
264 */
265
266#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
267                                 _isr, _entry_point, _is_fp ) \
268   do { \
269     unsigned32 _stack; \
270     \
271     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
272     _stack                  = (unsigned32)(_stack_base) + (_size) - 4; \
273     (_the_context)->a7_msp  = (void *)_stack; \
274     *(void **)_stack        = (void *)(_entry_point); \
275   } while ( 0 )
276
277#define _CPU_Context_Restart_self( _the_context ) \
278  { asm volatile( "movew %0,%%sr ; " \
279                  "moval %1,%%a7 ; " \
280                  "rts"  \
281        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
282        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
283  }
284
285#define _CPU_Context_Fp_start( _base, _offset ) \
286   ((void *) \
287     _Addresses_Add_offset( \
288        (_base), \
289        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
290     ) \
291   )
292
293#define _CPU_Context_Initialize_fp( _fp_area ) \
294   { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
295     \
296     *(--(_fp_context)) = 0; \
297     *(_fp_area) = (unsigned8 *)(_fp_context); \
298   }
299
300/* end of Context handler macros */
301
302/*
303 *  Fatal Error manager macros
304 *
305 *  These macros perform the following functions:
306 *    + disable interrupts and halt the CPU
307 */
308
309#define _CPU_Fatal_halt( _error ) \
310  { asm volatile( "movl  %0,%%d0; " \
311                  "orw   #0x0700,%%sr; " \
312                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
313  }
314
315/* end of Fatal Error manager macros */
316
317/*
318 *  Bitfield handler macros
319 *
320 *  These macros perform the following functions:
321 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
322 *
323 *  NOTE:
324 *
325 *    It appears that on the M68020 bitfield are always 32 bits wide
326 *    when in a register.  This code forces the bitfield to be in
327 *    memory (it really always is anyway). This allows us to
328 *    have a real 16 bit wide bitfield which operates "correctly."
329 */
330
331#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
332#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
333
334#if ( M68K_HAS_BFFFO == 1 )
335
336#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
337  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
338#else
339
340/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
341   _CPU_Priority_bits_index is not needed), handles the 0 case, and
342   does not molest _value -- jsg */
343#if ( M68K_HAS_EXTB_L == 1 )
344#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
345  { \
346    extern const unsigned char __BFFFOtable[256]; \
347    register int dumby; \
348    \
349    asm volatile ( "   move.w  %2,%1\n"        \
350       "   lsr.w   #8,%1\n"        \
351       "   beq.s   1f\n"           \
352       "   move.b  (%3,%1.w),%0\n" \
353       "   extb.l  %0\n"           \
354       "   bra.s   0f\n"           \
355       "1: moveq.l #8,%0\n"        \
356       "   add.b   (%3,%2.w),%0\n" \
357       "0:\n"                      \
358       : "=&d" ((_output)), "=&d" ((dumby)) \
359       : "d" ((_value)), "ao" ((__BFFFOtable)) \
360       : "cc" ) ; \
361  }
362#else
363#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
364  { \
365    extern const unsigned char __BFFFOtable[256]; \
366    register int dumby; \
367    \
368    asm volatile ( "   move.w  %2,%1\n"        \
369       "   lsr.w   #8,%1\n"        \
370       "   beq.s   1f\n"           \
371       "   move.b  (%3,%1.w),%0\n" \
372       "   and.l   #0x000000ff,%0\n"\
373       "   bra.s   0f\n"           \
374       "1: moveq.l #8,%0\n"        \
375       "   add.b   (%3,%2.w),%0\n" \
376       "0:\n"                      \
377       : "=&d" ((_output)), "=&d" ((dumby)) \
378       : "d" ((_value)), "ao" ((__BFFFOtable)) \
379       : "cc" ) ; \
380  }
381#endif /* M68K_HAS_EXTB_L */
382
383#endif
384
385/* end of Bitfield handler macros */
386
387/*
388 *  Priority handler macros
389 *
390 *  These macros perform the following functions:
391 *    + return a mask with the bit for this major/minor portion of
392 *      of thread priority set.
393 *    + translate the bit number returned by "Bitfield_find_first_bit"
394 *      into an index into the thread ready chain bit maps
395 */
396
397#define _CPU_Priority_Mask( _bit_number ) \
398  ( 0x8000 >> (_bit_number) )
399
400#define _CPU_Priority_bits_index( _priority ) \
401  (_priority)
402
403/* end of Priority handler macros */
404
405/* functions */
406
407/*
408 *  _CPU_Initialize
409 *
410 *  This routine performs CPU dependent initialization.
411 */
412
413void _CPU_Initialize(
414  rtems_cpu_table  *cpu_table,
415  void      (*thread_dispatch)
416);
417
418/*
419 *  _CPU_ISR_install_raw_handler
420 *
421 *  This routine installs a "raw" interrupt handler directly into the
422 *  processor's vector table.
423 */
424 
425void _CPU_ISR_install_raw_handler(
426  unsigned32  vector,
427  proc_ptr    new_handler,
428  proc_ptr   *old_handler
429);
430
431/*
432 *  _CPU_ISR_install_vector
433 *
434 *  This routine installs an interrupt vector.
435 */
436
437void _CPU_ISR_install_vector(
438  unsigned32       vector,
439  proc_ptr         new_handler,
440  proc_ptr        *old_handler
441);
442
443/*
444 *  _CPU_Install_interrupt_stack
445 *
446 *  This routine installs the hardware interrupt stack pointer.
447 */
448
449void _CPU_Install_interrupt_stack( void );
450
451/*
452 *  _CPU_Context_switch
453 *
454 *  This routine switches from the run context to the heir context.
455 */
456
457void _CPU_Context_switch(
458  Context_Control  *run,
459  Context_Control  *heir
460);
461
462/*
463 *  _CPU_Context_save_fp
464 *
465 *  This routine saves the floating point context passed to it.
466 */
467
468void _CPU_Context_restore_fp(
469  void **fp_context_ptr
470);
471
472/*
473 *  _CPU_Context_restore_fp
474 *
475 *  This routine restores the floating point context passed to it.
476 */
477
478void _CPU_Context_save_fp(
479  void **fp_context_ptr
480);
481#endif
482
483#ifdef __cplusplus
484}
485#endif
486
487#endif
488/* end of include file */
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