source: rtems/c/src/exec/score/cpu/m68k/cpu.h @ 6764c84

4.104.114.84.95
Last change on this file since 6764c84 was 6764c84, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 2, 1996 at 10:42:30 PM

minor changes to eliminate warnings from C++ compilers per user suggesstions.

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/m68k.h>
25#ifndef ASM
26#include <rtems/score/m68ktypes.h>
27#endif
28
29/* conditional compilation parameters */
30
31#define CPU_INLINE_ENABLE_DISPATCH       TRUE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  Use the m68k's hardware interrupt stack support and have the
36 *  interrupt manager allocate the memory for it.
37 *
38 *  NOTE:  The definitions when M68K_HAS_SEPARATE_STACKS is 0 should
39 *         change when the software interrupt stack support is implemented.
40 */
41
42#if ( M68K_HAS_SEPARATE_STACKS == 1)
43#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
44#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
45#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
46#else
47#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
48#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
49#define CPU_ALLOCATE_INTERRUPT_STACK     FALSE
50#endif
51
52/*
53 *  Some family members have no FP, some have an FPU such as the
54 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
55 */
56
57#if ( M68K_HAS_FPU == 1 )
58#define CPU_HARDWARE_FP     TRUE
59#else
60#define CPU_HARDWARE_FP     FALSE
61#endif
62
63/*
64 *  All tasks are not by default floating point tasks on this CPU.
65 *  The IDLE task does not have a floating point context on this CPU.
66 *  It is safe to use the deferred floating point context switch
67 *  algorithm on this CPU.
68 */
69
70#define CPU_ALL_TASKS_ARE_FP             FALSE
71#define CPU_IDLE_TASK_IS_FP              FALSE
72#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
73
74#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
75#define CPU_STACK_GROWS_UP               FALSE
76#define CPU_STRUCTURE_ALIGNMENT
77
78/* structures */
79
80/*
81 *  Basic integer context for the m68k family.
82 */
83
84typedef struct {
85  unsigned32  sr;                /* (sr) status register */
86  unsigned32  d2;                /* (d2) data register 2 */
87  unsigned32  d3;                /* (d3) data register 3 */
88  unsigned32  d4;                /* (d4) data register 4 */
89  unsigned32  d5;                /* (d5) data register 5 */
90  unsigned32  d6;                /* (d6) data register 6 */
91  unsigned32  d7;                /* (d7) data register 7 */
92  void       *a2;                /* (a2) address register 2 */
93  void       *a3;                /* (a3) address register 3 */
94  void       *a4;                /* (a4) address register 4 */
95  void       *a5;                /* (a5) address register 5 */
96  void       *a6;                /* (a6) address register 6 */
97  void       *a7_msp;            /* (a7) master stack pointer */
98}   Context_Control;
99
100/*
101 *  FP context save area for the M68881/M68882 numeric coprocessors.
102 */
103
104typedef struct {
105  unsigned8   fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
106                                    /*    96 bytes for FMOVEM FP0-7      */
107                                    /*    12 bytes for FMOVEM CREGS      */
108                                    /*     4 bytes for non-null flag     */
109} Context_Control_fp;
110
111/*
112 *  The following structure defines the set of information saved
113 *  on the current stack by RTEMS upon receipt of each interrupt.
114 */
115
116typedef struct {
117  unsigned32   TBD;   /* XXX Fix for this CPU */
118} CPU_Interrupt_frame;
119
120/*
121 *  The following table contains the information required to configure
122 *  the m68k specific parameters.
123 */
124
125typedef struct {
126  void       (*pretasking_hook)( void );
127  void       (*predriver_hook)( void );
128  void       (*postdriver_hook)( void );
129  void       (*idle_task)( void );
130  boolean      do_zero_of_workspace;
131  unsigned32   interrupt_stack_size;
132  unsigned32   extra_mpci_receive_server_stack;
133  void *     (*stack_allocate_hook)( unsigned32 );
134  void       (*stack_free_hook)( void* );
135  /* end of fields required on all CPUs */
136
137  m68k_isr    *interrupt_vector_table;
138}   rtems_cpu_table;
139
140/* variables */
141
142SCORE_EXTERN void                   *_CPU_Interrupt_stack_low;
143SCORE_EXTERN void                   *_CPU_Interrupt_stack_high;
144
145extern char                         _VBR[]; 
146
147#if ( M68K_HAS_VBR == 0 )
148
149/*
150 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
151 * pushed onto the stack. This is not is the same order as VBR processors.
152 * The ISR handler takes the format and uses it for dispatching the user
153 * handler.
154 *
155 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
156 *
157 */
158
159typedef struct {
160  unsigned16 move_a7;            /* move #FORMAT_ID,%a7@- */
161  unsigned16 format_id;
162  unsigned16 jmp;                /* jmp  _ISR_Handlers */
163  unsigned32 isr_handler;
164} _CPU_ISR_handler_entry;
165
166#define M68K_MOVE_A7 0x3F3C
167#define M68K_JMP     0x4EF9
168
169      /* points to jsr-exception-table in targets wo/ VBR register */
170SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; 
171
172#endif /* M68K_HAS_VBR */
173
174/* constants */
175
176/*
177 *  This defines the number of levels and the mask used to pick those
178 *  bits out of a thread mode.
179 */
180
181#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
182#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
183
184/*
185 *  context size area for floating point
186 */
187
188#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
189
190/*
191 *  extra stack required by the MPCI receive server thread
192 */
193
194#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
195
196/*
197 *  m68k family supports 256 distinct vectors.
198 */
199
200#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
201#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
202
203/*
204 *  Minimum size of a thread's stack.
205 */
206
207#define CPU_STACK_MINIMUM_SIZE           2048
208
209/*
210 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
211 */
212
213#define CPU_ALIGNMENT                    4
214#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
215#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
216
217/*
218 *  On m68k thread stacks require no further alignment after allocation
219 *  from the Workspace.
220 */
221
222#define CPU_STACK_ALIGNMENT        0
223
224/* macros */
225
226/*
227 *  ISR handler macros
228 *
229 *  These macros perform the following functions:
230 *     + disable all maskable CPU interrupts
231 *     + restore previous interrupt level (enable)
232 *     + temporarily restore interrupts (flash)
233 *     + set a particular level
234 */
235
236#define _CPU_ISR_Disable( _level ) \
237  m68k_disable_interrupts( _level )
238
239#define _CPU_ISR_Enable( _level ) \
240  m68k_enable_interrupts( _level )
241
242#define _CPU_ISR_Flash( _level ) \
243  m68k_flash_interrupts( _level )
244
245#define _CPU_ISR_Set_level( _newlevel ) \
246   m68k_set_interrupt_level( _newlevel )
247
248unsigned32 _CPU_ISR_Get_level( void );
249
250/* end of ISR handler macros */
251
252/*
253 *  Context handler macros
254 *
255 *  These macros perform the following functions:
256 *     + initialize a context area
257 *     + restart the current thread
258 *     + calculate the initial pointer into a FP context area
259 *     + initialize an FP context area
260 */
261
262#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
263                                 _isr, _entry_point, _is_fp ) \
264   do { \
265     unsigned32 _stack; \
266     \
267     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
268     _stack                  = (unsigned32)(_stack_base) + (_size) - 4; \
269     (_the_context)->a7_msp  = (void *)_stack; \
270     *(void **)_stack        = (void *)(_entry_point); \
271   } while ( 0 )
272
273#define _CPU_Context_Restart_self( _the_context ) \
274  { asm volatile( "movew %0,%%sr ; " \
275                  "moval %1,%%a7 ; " \
276                  "rts"  \
277        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
278        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
279  }
280
281#define _CPU_Context_Fp_start( _base, _offset ) \
282   ((void *) \
283     _Addresses_Add_offset( \
284        (_base), \
285        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
286     ) \
287   )
288
289#define _CPU_Context_Initialize_fp( _fp_area ) \
290   { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
291     \
292     *(--(_fp_context)) = 0; \
293     *(_fp_area) = (unsigned8 *)(_fp_context); \
294   }
295
296/* end of Context handler macros */
297
298/*
299 *  Fatal Error manager macros
300 *
301 *  These macros perform the following functions:
302 *    + disable interrupts and halt the CPU
303 */
304
305#define _CPU_Fatal_halt( _error ) \
306  { asm volatile( "movl  %0,%%d0; " \
307                  "orw   #0x0700,%%sr; " \
308                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
309  }
310
311/* end of Fatal Error manager macros */
312
313/*
314 *  Bitfield handler macros
315 *
316 *  These macros perform the following functions:
317 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
318 *
319 *  NOTE:
320 *
321 *    It appears that on the M68020 bitfield are always 32 bits wide
322 *    when in a register.  This code forces the bitfield to be in
323 *    memory (it really always is anyway). This allows us to
324 *    have a real 16 bit wide bitfield which operates "correctly."
325 */
326
327#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
328#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
329
330#if ( M68K_HAS_BFFFO == 1 )
331
332#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
333  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
334#else
335
336/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
337   _CPU_Priority_bits_index is not needed), handles the 0 case, and
338   does not molest _value -- jsg */
339#if ( M68K_HAS_EXTB_L == 1 )
340#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
341  { \
342    extern const unsigned char __BFFFOtable[256]; \
343    register int dumby; \
344    \
345    asm volatile ( "   move.w  %2,%1\n"        \
346       "   lsr.w   #8,%1\n"        \
347       "   beq.s   1f\n"           \
348       "   move.b  (%3,%1.w),%0\n" \
349       "   extb.l  %0\n"           \
350       "   bra.s   0f\n"           \
351       "1: moveq.l #8,%0\n"        \
352       "   add.b   (%3,%2.w),%0\n" \
353       "0:\n"                      \
354       : "=&d" ((_output)), "=&d" ((dumby)) \
355       : "d" ((_value)), "ao" ((__BFFFOtable)) \
356       : "cc" ) ; \
357  }
358#else
359#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
360  { \
361    extern const unsigned char __BFFFOtable[256]; \
362    register int dumby; \
363    \
364    asm volatile ( "   move.w  %2,%1\n"        \
365       "   lsr.w   #8,%1\n"        \
366       "   beq.s   1f\n"           \
367       "   move.b  (%3,%1.w),%0\n" \
368       "   and.l   #0x000000ff,%0\n"\
369       "   bra.s   0f\n"           \
370       "1: moveq.l #8,%0\n"        \
371       "   add.b   (%3,%2.w),%0\n" \
372       "0:\n"                      \
373       : "=&d" ((_output)), "=&d" ((dumby)) \
374       : "d" ((_value)), "ao" ((__BFFFOtable)) \
375       : "cc" ) ; \
376  }
377#endif /* M68K_HAS_EXTB_L */
378
379#endif
380
381/* end of Bitfield handler macros */
382
383/*
384 *  Priority handler macros
385 *
386 *  These macros perform the following functions:
387 *    + return a mask with the bit for this major/minor portion of
388 *      of thread priority set.
389 *    + translate the bit number returned by "Bitfield_find_first_bit"
390 *      into an index into the thread ready chain bit maps
391 */
392
393#define _CPU_Priority_Mask( _bit_number ) \
394  ( 0x8000 >> (_bit_number) )
395
396#define _CPU_Priority_bits_index( _priority ) \
397  (_priority)
398
399/* end of Priority handler macros */
400
401/* functions */
402
403/*
404 *  _CPU_Initialize
405 *
406 *  This routine performs CPU dependent initialization.
407 */
408
409void _CPU_Initialize(
410  rtems_cpu_table  *cpu_table,
411  void      (*thread_dispatch)
412);
413
414/*
415 *  _CPU_ISR_install_raw_handler
416 *
417 *  This routine installs a "raw" interrupt handler directly into the
418 *  processor's vector table.
419 */
420 
421void _CPU_ISR_install_raw_handler(
422  unsigned32  vector,
423  proc_ptr    new_handler,
424  proc_ptr   *old_handler
425);
426
427/*
428 *  _CPU_ISR_install_vector
429 *
430 *  This routine installs an interrupt vector.
431 */
432
433void _CPU_ISR_install_vector(
434  unsigned32       vector,
435  proc_ptr         new_handler,
436  proc_ptr        *old_handler
437);
438
439/*
440 *  _CPU_Install_interrupt_stack
441 *
442 *  This routine installs the hardware interrupt stack pointer.
443 */
444
445void _CPU_Install_interrupt_stack( void );
446
447/*
448 *  _CPU_Context_switch
449 *
450 *  This routine switches from the run context to the heir context.
451 */
452
453void _CPU_Context_switch(
454  Context_Control  *run,
455  Context_Control  *heir
456);
457
458/*
459 *  _CPU_Context_save_fp
460 *
461 *  This routine saves the floating point context passed to it.
462 */
463
464void _CPU_Context_restore_fp(
465  void **fp_context_ptr
466);
467
468/*
469 *  _CPU_Context_restore_fp
470 *
471 *  This routine restores the floating point context passed to it.
472 */
473
474void _CPU_Context_save_fp(
475  void **fp_context_ptr
476);
477
478#ifdef __cplusplus
479}
480#endif
481
482#endif
483/* end of include file */
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