source: rtems/c/src/exec/score/cpu/m68k/cpu.h @ 5e9b32b

4.104.114.84.95
Last change on this file since 5e9b32b was 5e9b32b, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 26, 1995 at 7:27:15 PM

posix support initially added

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  If defined, this causes some of the macros to initialize their
26 *  variables to zero before doing inline assembly.  This gets rid
27 *  of compile time warnings at the cost of a little execution time
28 *  in some time critical routines.
29 */
30
31#define NO_UNINITIALIZED_WARNINGS
32
33#include <rtems/score/m68k.h>
34#ifndef ASM
35#include <rtems/score/m68ktypes.h>
36#endif
37
38/* conditional compilation parameters */
39
40#define CPU_INLINE_ENABLE_DISPATCH       TRUE
41#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
42
43/*
44 *  Use the m68k's hardware interrupt stack support and have the
45 *  interrupt manager allocate the memory for it.
46 *
47 *  NOTE:  The definitions when M68K_HAS_SEPARATE_STACKS is 0 should
48 *         change when the software interrupt stack support is implemented.
49 */
50
51#if ( M68K_HAS_SEPARATE_STACKS == 1)
52#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
53#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
54#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
55#else
56#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
57#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
58#define CPU_ALLOCATE_INTERRUPT_STACK     FALSE
59#endif
60
61/*
62 *  Some family members have no FP, some have an FPU such as the
63 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
64 */
65
66#if ( M68K_HAS_FPU == 1 )
67#define CPU_HARDWARE_FP     TRUE
68#else
69#define CPU_HARDWARE_FP     FALSE
70#endif
71
72/*
73 *  All tasks are not by default floating point tasks on this CPU.
74 *  The IDLE task does not have a floating point context on this CPU.
75 *  It is safe to use the deferred floating point context switch
76 *  algorithm on this CPU.
77 */
78
79#define CPU_ALL_TASKS_ARE_FP             FALSE
80#define CPU_IDLE_TASK_IS_FP              FALSE
81#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
82
83#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
84#define CPU_STACK_GROWS_UP               FALSE
85#define CPU_STRUCTURE_ALIGNMENT
86
87/* structures */
88
89/*
90 *  Basic integer context for the m68k family.
91 */
92
93typedef struct {
94  unsigned32  sr;                /* (sr) status register */
95  unsigned32  d2;                /* (d2) data register 2 */
96  unsigned32  d3;                /* (d3) data register 3 */
97  unsigned32  d4;                /* (d4) data register 4 */
98  unsigned32  d5;                /* (d5) data register 5 */
99  unsigned32  d6;                /* (d6) data register 6 */
100  unsigned32  d7;                /* (d7) data register 7 */
101  void       *a2;                /* (a2) address register 2 */
102  void       *a3;                /* (a3) address register 3 */
103  void       *a4;                /* (a4) address register 4 */
104  void       *a5;                /* (a5) address register 5 */
105  void       *a6;                /* (a6) address register 6 */
106  void       *a7_msp;            /* (a7) master stack pointer */
107}   Context_Control;
108
109/*
110 *  FP context save area for the M68881/M68882 numeric coprocessors.
111 */
112
113typedef struct {
114  unsigned8   fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
115                                    /*    96 bytes for FMOVEM FP0-7      */
116                                    /*    12 bytes for FMOVEM CREGS      */
117                                    /*     4 bytes for non-null flag     */
118} Context_Control_fp;
119
120/*
121 *  The following structure defines the set of information saved
122 *  on the current stack by RTEMS upon receipt of each interrupt.
123 */
124
125typedef struct {
126  unsigned32   TBD;   /* XXX Fix for this CPU */
127} CPU_Interrupt_frame;
128
129/*
130 *  The following table contains the information required to configure
131 *  the m68k specific parameters.
132 */
133
134typedef struct {
135  void       (*pretasking_hook)( void );
136  void       (*predriver_hook)( void );
137  void       (*postdriver_hook)( void );
138  void       (*idle_task)( void );
139  boolean      do_zero_of_workspace;
140  unsigned32   interrupt_stack_size;
141  unsigned32   extra_system_initialization_stack;
142  m68k_isr    *interrupt_vector_table;
143}   rtems_cpu_table;
144
145/* variables */
146
147EXTERN void               *_CPU_Interrupt_stack_low;
148EXTERN void               *_CPU_Interrupt_stack_high;
149      /* points to jsr-exception-table in targets wo/ VBR register */
150extern char               _VBR[]; 
151
152/* constants */
153
154/*
155 *  This defines the number of levels and the mask used to pick those
156 *  bits out of a thread mode.
157 */
158
159#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
160#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
161
162/*
163 *  context size area for floating point
164 */
165
166#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
167
168/*
169 *  extra stack required by system initialization thread
170 */
171
172#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 1024
173
174/*
175 *  m68k family supports 256 distinct vectors.
176 */
177
178#define CPU_INTERRUPT_NUMBER_OF_VECTORS  256
179
180/*
181 *  Minimum size of a thread's stack.
182 */
183
184#define CPU_STACK_MINIMUM_SIZE           1024
185
186/*
187 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
188 */
189
190#define CPU_ALIGNMENT                    4
191#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
192#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
193
194/*
195 *  On m68k thread stacks require no further alignment after allocation
196 *  from the Workspace.
197 */
198
199#define CPU_STACK_ALIGNMENT        0
200
201/* macros */
202
203/*
204 *  ISR handler macros
205 *
206 *  These macros perform the following functions:
207 *     + disable all maskable CPU interrupts
208 *     + restore previous interrupt level (enable)
209 *     + temporarily restore interrupts (flash)
210 *     + set a particular level
211 */
212
213#define _CPU_ISR_Disable( _level ) \
214  m68k_disable_interrupts( _level )
215
216#define _CPU_ISR_Enable( _level ) \
217  m68k_enable_interrupts( _level )
218
219#define _CPU_ISR_Flash( _level ) \
220  m68k_flash_interrupts( _level )
221
222#define _CPU_ISR_Set_level( _newlevel ) \
223   m68k_set_interrupt_level( _newlevel )
224
225unsigned32 _CPU_ISR_Get_level( void );
226
227/* end of ISR handler macros */
228
229/*
230 *  Context handler macros
231 *
232 *  These macros perform the following functions:
233 *     + initialize a context area
234 *     + restart the current thread
235 *     + calculate the initial pointer into a FP context area
236 *     + initialize an FP context area
237 */
238
239#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
240                                 _isr, _entry_point ) \
241   do { \
242     void   *_stack; \
243     \
244     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
245     _stack                  = (void *)(_stack_base) + (_size) - 4; \
246     (_the_context)->a7_msp  = _stack; \
247     *(void **)_stack = (_entry_point); \
248   } while ( 0 )
249
250#define _CPU_Context_Restart_self( _the_context ) \
251  { asm volatile( "movew %0,%%sr ; " \
252                  "moval %1,%%a7 ; " \
253                  "rts"  \
254        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
255        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
256  }
257
258#define _CPU_Context_Fp_start( _base, _offset ) \
259   ((void *) \
260     _Addresses_Add_offset( \
261        (_base), \
262        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
263     ) \
264   )
265
266#define _CPU_Context_Initialize_fp( _fp_area ) \
267   { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
268     \
269     *(--(_fp_context)) = 0; \
270     *(_fp_area) = (unsigned8 *)(_fp_context); \
271   }
272
273/* end of Context handler macros */
274
275/*
276 *  Fatal Error manager macros
277 *
278 *  These macros perform the following functions:
279 *    + disable interrupts and halt the CPU
280 */
281
282#define _CPU_Fatal_halt( _error ) \
283  { asm volatile( "movl  %0,%%d0; " \
284                  "orw   #0x0700,%%sr; " \
285                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
286  }
287
288/* end of Fatal Error manager macros */
289
290/*
291 *  Bitfield handler macros
292 *
293 *  These macros perform the following functions:
294 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
295 *
296 *  NOTE:
297 *
298 *    It appears that on the M68020 bitfield are always 32 bits wide
299 *    when in a register.  This code forces the bitfield to be in
300 *    memory (it really always is anyway). This allows us to
301 *    have a real 16 bit wide bitfield which operates "correctly."
302 */
303
304#if ( M68K_HAS_BFFFO == 1 )
305#ifdef NO_UNINITIALIZED_WARNINGS
306
307#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
308  { \
309    register void *__base = (void *)&(_value); \
310    \
311    (_output) = 0;  /* avoids warnings */ \
312    asm volatile( "bfffo (%0),#0,#16,%1" \
313                   : "=a" (__base), "=d" ((_output)) \
314                   : "0"  (__base), "1" ((_output))  ) ; \
315  }
316#else
317#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
318  { \
319    register void *__base = (void *)&(_value); \
320    \
321    asm volatile( "bfffo (%0),#0,#16,%1" \
322                   : "=a" (__base), "=d" ((_output)) \
323                   : "0"  (__base), "1" ((_output))  ) ; \
324  }
325#endif
326
327#else
328
329/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
330   _CPU_Priority_Bits_index is not needed), handles the 0 case, and
331   does not molest _value -- jsg */
332#ifndef m68000
333#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
334  { \
335    extern const unsigned char __BFFFOtable[256]; \
336    register int dumby; \
337    \
338    asm volatile ( "   move.w  %2,%1\n"        \
339       "   lsr.w   #8,%1\n"        \
340       "   beq.s   1f\n"           \
341       "   move.b  (%3,%1.w),%0\n" \
342       "   extb.l  %0\n"           \
343       "   bra.s   0f\n"           \
344       "1: moveq.l #8,%0\n"        \
345       "   add.b   (%3,%2.w),%0\n" \
346       "0:\n"                      \
347       : "=&d" ((_output)), "=&d" ((dumby)) \
348       : "d" ((_value)), "ao" ((__BFFFOtable)) \
349       : "cc" ) ; \
350  }
351#else
352#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
353  { \
354    extern const unsigned char __BFFFOtable[256]; \
355    register int dumby; \
356    \
357    asm volatile ( "   move.w  %2,%1\n"        \
358       "   lsr.w   #8,%1\n"        \
359       "   beq.s   1f\n"           \
360       "   move.b  (%3,%1.w),%0\n" \
361       "   and.l   #0x000000ff,%0\n"\
362       "   bra.s   0f\n"           \
363       "1: moveq.l #8,%0\n"        \
364       "   add.b   (%3,%2.w),%0\n" \
365       "0:\n"                      \
366       : "=&d" ((_output)), "=&d" ((dumby)) \
367       : "d" ((_value)), "ao" ((__BFFFOtable)) \
368       : "cc" ) ; \
369  }
370#endif /* m68000 */
371
372#endif
373
374/* end of Bitfield handler macros */
375
376/*
377 *  Priority handler macros
378 *
379 *  These macros perform the following functions:
380 *    + return a mask with the bit for this major/minor portion of
381 *      of thread priority set.
382 *    + translate the bit number returned by "Bitfield_find_first_bit"
383 *      into an index into the thread ready chain bit maps
384 */
385
386#define _CPU_Priority_Mask( _bit_number ) \
387  ( 0x8000 >> (_bit_number) )
388
389#define _CPU_Priority_Bits_index( _priority ) \
390  (_priority)
391
392/* end of Priority handler macros */
393
394/* functions */
395
396/*
397 *  _CPU_Initialize
398 *
399 *  This routine performs CPU dependent initialization.
400 */
401
402void _CPU_Initialize(
403  rtems_cpu_table  *cpu_table,
404  void      (*thread_dispatch)
405);
406
407/*
408 *  _CPU_ISR_install_raw_handler
409 *
410 *  This routine installs a "raw" interrupt handler directly into the
411 *  processor's vector table.
412 */
413 
414void _CPU_ISR_install_raw_handler(
415  unsigned32  vector,
416  proc_ptr    new_handler,
417  proc_ptr   *old_handler
418);
419
420/*
421 *  _CPU_ISR_install_vector
422 *
423 *  This routine installs an interrupt vector.
424 */
425
426void _CPU_ISR_install_vector(
427  unsigned32       vector,
428  proc_ptr         new_handler,
429  proc_ptr        *old_handler
430);
431
432/*
433 *  _CPU_Install_interrupt_stack
434 *
435 *  This routine installs the hardware interrupt stack pointer.
436 */
437
438void _CPU_Install_interrupt_stack( void );
439
440/*
441 *  _CPU_Context_switch
442 *
443 *  This routine switches from the run context to the heir context.
444 */
445
446void _CPU_Context_switch(
447  Context_Control  *run,
448  Context_Control  *heir
449);
450
451/*
452 *  _CPU_Context_save_fp
453 *
454 *  This routine saves the floating point context passed to it.
455 */
456
457void _CPU_Context_restore_fp(
458  void **fp_context_ptr
459);
460
461/*
462 *  _CPU_Context_restore_fp
463 *
464 *  This routine restores the floating point context passed to it.
465 */
466
467void _CPU_Context_save_fp(
468  void **fp_context_ptr
469);
470
471#ifdef __cplusplus
472}
473#endif
474
475#endif
476/* end of include file */
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