1 | /* cpu.h |
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2 | * |
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3 | * This include file contains information pertaining to the Motorola |
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4 | * m68xxx processor family. |
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5 | * |
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6 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * All rights assigned to U.S. Government, 1994. |
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9 | * |
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10 | * This material may be reproduced by or for the U.S. Government pursuant |
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11 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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12 | * notice must appear in all copies of this file and its derivatives. |
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13 | * |
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14 | * $Id$ |
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15 | */ |
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16 | |
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17 | #ifndef __CPU_h |
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18 | #define __CPU_h |
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19 | |
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20 | #ifdef __cplusplus |
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21 | extern "C" { |
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22 | #endif |
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23 | |
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24 | #include <rtems/score/m68k.h> /* pick up machine definitions */ |
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25 | #ifndef ASM |
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26 | #include <rtems/score/m68ktypes.h> |
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27 | #endif |
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28 | |
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29 | /* conditional compilation parameters */ |
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30 | |
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31 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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32 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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33 | |
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34 | /* |
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35 | * Use the m68k's hardware interrupt stack support and have the |
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36 | * interrupt manager allocate the memory for it. |
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37 | * |
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38 | * NOTE: The definitions when M68K_HAS_SEPARATE_STACKS is 0 should |
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39 | * change when the software interrupt stack support is implemented. |
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40 | */ |
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41 | |
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42 | #if ( M68K_HAS_SEPARATE_STACKS == 1) |
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43 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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44 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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45 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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46 | #else |
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47 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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48 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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49 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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50 | #endif |
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51 | |
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52 | /* |
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53 | * Some family members have no FP, some have an FPU such as the |
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54 | * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). |
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55 | */ |
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56 | |
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57 | #if ( M68K_HAS_FPU == 1 ) |
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58 | #define CPU_HARDWARE_FP TRUE |
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59 | #else |
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60 | #define CPU_HARDWARE_FP FALSE |
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61 | #endif |
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62 | |
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63 | /* |
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64 | * All tasks are not by default floating point tasks on this CPU. |
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65 | * The IDLE task does not have a floating point context on this CPU. |
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66 | * It is safe to use the deferred floating point context switch |
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67 | * algorithm on this CPU. |
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68 | */ |
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69 | |
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70 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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71 | #define CPU_IDLE_TASK_IS_FP FALSE |
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72 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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73 | |
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74 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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75 | #define CPU_STACK_GROWS_UP FALSE |
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76 | #define CPU_STRUCTURE_ALIGNMENT |
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77 | |
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78 | /* |
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79 | * Define what is required to specify how the network to host conversion |
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80 | * routines are handled. |
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81 | */ |
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82 | |
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83 | #define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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84 | #define CPU_BIG_ENDIAN TRUE |
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85 | #define CPU_LITTLE_ENDIAN FALSE |
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86 | |
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87 | #ifndef ASM |
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88 | /* structures */ |
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89 | |
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90 | /* |
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91 | * Basic integer context for the m68k family. |
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92 | */ |
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93 | |
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94 | typedef struct { |
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95 | unsigned32 sr; /* (sr) status register */ |
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96 | unsigned32 d2; /* (d2) data register 2 */ |
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97 | unsigned32 d3; /* (d3) data register 3 */ |
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98 | unsigned32 d4; /* (d4) data register 4 */ |
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99 | unsigned32 d5; /* (d5) data register 5 */ |
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100 | unsigned32 d6; /* (d6) data register 6 */ |
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101 | unsigned32 d7; /* (d7) data register 7 */ |
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102 | void *a2; /* (a2) address register 2 */ |
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103 | void *a3; /* (a3) address register 3 */ |
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104 | void *a4; /* (a4) address register 4 */ |
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105 | void *a5; /* (a5) address register 5 */ |
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106 | void *a6; /* (a6) address register 6 */ |
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107 | void *a7_msp; /* (a7) master stack pointer */ |
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108 | } Context_Control; |
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109 | |
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110 | /* |
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111 | * FP context save area for the M68881/M68882 numeric coprocessors. |
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112 | */ |
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113 | |
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114 | typedef struct { |
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115 | unsigned8 fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */ |
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116 | /* 96 bytes for FMOVEM FP0-7 */ |
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117 | /* 12 bytes for FMOVEM CREGS */ |
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118 | /* 4 bytes for non-null flag */ |
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119 | } Context_Control_fp; |
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120 | |
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121 | /* |
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122 | * The following structure defines the set of information saved |
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123 | * on the current stack by RTEMS upon receipt of each interrupt. |
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124 | */ |
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125 | |
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126 | typedef struct { |
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127 | unsigned32 TBD; /* XXX Fix for this CPU */ |
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128 | } CPU_Interrupt_frame; |
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129 | |
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130 | /* |
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131 | * The following table contains the information required to configure |
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132 | * the m68k specific parameters. |
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133 | */ |
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134 | |
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135 | typedef struct { |
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136 | void (*pretasking_hook)( void ); |
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137 | void (*predriver_hook)( void ); |
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138 | void (*postdriver_hook)( void ); |
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139 | void (*idle_task)( void ); |
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140 | boolean do_zero_of_workspace; |
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141 | unsigned32 interrupt_stack_size; |
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142 | unsigned32 extra_mpci_receive_server_stack; |
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143 | void * (*stack_allocate_hook)( unsigned32 ); |
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144 | void (*stack_free_hook)( void* ); |
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145 | /* end of fields required on all CPUs */ |
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146 | |
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147 | m68k_isr *interrupt_vector_table; |
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148 | } rtems_cpu_table; |
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149 | |
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150 | /* variables */ |
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151 | |
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152 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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153 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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154 | |
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155 | extern char _VBR[]; |
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156 | |
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157 | #if ( M68K_HAS_VBR == 0 ) |
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158 | |
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159 | /* |
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160 | * Table of ISR handler entries that resides in RAM. The FORMAT/ID is |
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161 | * pushed onto the stack. This is not is the same order as VBR processors. |
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162 | * The ISR handler takes the format and uses it for dispatching the user |
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163 | * handler. |
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164 | * |
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165 | * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS |
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166 | * |
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167 | */ |
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168 | |
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169 | typedef struct { |
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170 | unsigned16 move_a7; /* move #FORMAT_ID,%a7@- */ |
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171 | unsigned16 format_id; |
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172 | unsigned16 jmp; /* jmp _ISR_Handlers */ |
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173 | unsigned32 isr_handler; |
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174 | } _CPU_ISR_handler_entry; |
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175 | |
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176 | #define M68K_MOVE_A7 0x3F3C |
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177 | #define M68K_JMP 0x4EF9 |
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178 | |
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179 | /* points to jsr-exception-table in targets wo/ VBR register */ |
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180 | SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; |
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181 | |
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182 | #endif /* M68K_HAS_VBR */ |
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183 | #endif /* ASM */ |
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184 | |
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185 | /* constants */ |
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186 | |
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187 | /* |
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188 | * This defines the number of levels and the mask used to pick those |
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189 | * bits out of a thread mode. |
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190 | */ |
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191 | |
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192 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ |
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193 | #define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ |
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194 | |
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195 | /* |
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196 | * context size area for floating point |
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197 | */ |
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198 | |
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199 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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200 | |
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201 | /* |
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202 | * extra stack required by the MPCI receive server thread |
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203 | */ |
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204 | |
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205 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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206 | |
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207 | /* |
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208 | * m68k family supports 256 distinct vectors. |
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209 | */ |
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210 | |
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211 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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212 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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213 | |
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214 | /* |
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215 | * Minimum size of a thread's stack. |
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216 | */ |
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217 | |
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218 | #define CPU_STACK_MINIMUM_SIZE 2048 |
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219 | |
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220 | /* |
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221 | * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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222 | */ |
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223 | |
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224 | #define CPU_ALIGNMENT 4 |
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225 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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226 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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227 | |
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228 | /* |
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229 | * On m68k thread stacks require no further alignment after allocation |
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230 | * from the Workspace. |
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231 | */ |
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232 | |
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233 | #define CPU_STACK_ALIGNMENT 0 |
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234 | |
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235 | #ifndef ASM |
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236 | |
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237 | /* macros */ |
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238 | |
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239 | /* |
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240 | * ISR handler macros |
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241 | * |
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242 | * These macros perform the following functions: |
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243 | * + disable all maskable CPU interrupts |
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244 | * + restore previous interrupt level (enable) |
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245 | * + temporarily restore interrupts (flash) |
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246 | * + set a particular level |
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247 | */ |
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248 | |
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249 | #define _CPU_ISR_Disable( _level ) \ |
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250 | m68k_disable_interrupts( _level ) |
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251 | |
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252 | #define _CPU_ISR_Enable( _level ) \ |
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253 | m68k_enable_interrupts( _level ) |
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254 | |
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255 | #define _CPU_ISR_Flash( _level ) \ |
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256 | m68k_flash_interrupts( _level ) |
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257 | |
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258 | #define _CPU_ISR_Set_level( _newlevel ) \ |
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259 | m68k_set_interrupt_level( _newlevel ) |
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260 | |
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261 | unsigned32 _CPU_ISR_Get_level( void ); |
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262 | |
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263 | /* end of ISR handler macros */ |
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264 | |
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265 | /* |
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266 | * Context handler macros |
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267 | * |
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268 | * These macros perform the following functions: |
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269 | * + initialize a context area |
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270 | * + restart the current thread |
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271 | * + calculate the initial pointer into a FP context area |
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272 | * + initialize an FP context area |
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273 | */ |
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274 | |
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275 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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276 | _isr, _entry_point, _is_fp ) \ |
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277 | do { \ |
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278 | unsigned32 _stack; \ |
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279 | \ |
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280 | (_the_context)->sr = 0x3000 | ((_isr) << 8); \ |
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281 | _stack = (unsigned32)(_stack_base) + (_size) - 4; \ |
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282 | (_the_context)->a7_msp = (void *)_stack; \ |
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283 | *(void **)_stack = (void *)(_entry_point); \ |
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284 | } while ( 0 ) |
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285 | |
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286 | #define _CPU_Context_Restart_self( _the_context ) \ |
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287 | { asm volatile( "movew %0,%%sr ; " \ |
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288 | "moval %1,%%a7 ; " \ |
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289 | "rts" \ |
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290 | : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \ |
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291 | : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \ |
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292 | } |
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293 | |
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294 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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295 | ((void *) \ |
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296 | _Addresses_Add_offset( \ |
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297 | (_base), \ |
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298 | (_offset) + CPU_CONTEXT_FP_SIZE - 4 \ |
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299 | ) \ |
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300 | ) |
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301 | |
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302 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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303 | { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \ |
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304 | \ |
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305 | *(--(_fp_context)) = 0; \ |
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306 | *(_fp_area) = (unsigned8 *)(_fp_context); \ |
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307 | } |
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308 | |
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309 | /* end of Context handler macros */ |
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310 | |
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311 | /* |
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312 | * Fatal Error manager macros |
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313 | * |
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314 | * These macros perform the following functions: |
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315 | * + disable interrupts and halt the CPU |
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316 | */ |
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317 | |
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318 | #define _CPU_Fatal_halt( _error ) \ |
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319 | { asm volatile( "movl %0,%%d0; " \ |
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320 | "orw #0x0700,%%sr; " \ |
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321 | "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ |
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322 | } |
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323 | |
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324 | /* end of Fatal Error manager macros */ |
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325 | |
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326 | /* |
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327 | * Bitfield handler macros |
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328 | * |
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329 | * These macros perform the following functions: |
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330 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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331 | * |
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332 | * NOTE: |
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333 | * |
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334 | * It appears that on the M68020 bitfield are always 32 bits wide |
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335 | * when in a register. This code forces the bitfield to be in |
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336 | * memory (it really always is anyway). This allows us to |
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337 | * have a real 16 bit wide bitfield which operates "correctly." |
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338 | */ |
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339 | |
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340 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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341 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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342 | |
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343 | #if ( M68K_HAS_BFFFO == 1 ) |
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344 | |
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345 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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346 | asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); |
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347 | #else |
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348 | |
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349 | /* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in |
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350 | _CPU_Priority_bits_index is not needed), handles the 0 case, and |
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351 | does not molest _value -- jsg */ |
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352 | #if ( M68K_HAS_EXTB_L == 1 ) |
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353 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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354 | { \ |
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355 | extern const unsigned char __BFFFOtable[256]; \ |
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356 | register int dumby; \ |
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357 | \ |
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358 | asm volatile ( " move.w %2,%1\n" \ |
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359 | " lsr.w #8,%1\n" \ |
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360 | " beq.s 1f\n" \ |
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361 | " move.b (%3,%1.w),%0\n" \ |
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362 | " extb.l %0\n" \ |
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363 | " bra.s 0f\n" \ |
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364 | "1: moveq.l #8,%0\n" \ |
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365 | " add.b (%3,%2.w),%0\n" \ |
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366 | "0:\n" \ |
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367 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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368 | : "d" ((_value)), "ao" ((__BFFFOtable)) \ |
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369 | : "cc" ) ; \ |
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370 | } |
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371 | #else |
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372 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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373 | { \ |
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374 | extern const unsigned char __BFFFOtable[256]; \ |
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375 | register int dumby; \ |
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376 | \ |
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377 | asm volatile ( " move.w %2,%1\n" \ |
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378 | " lsr.w #8,%1\n" \ |
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379 | " beq.s 1f\n" \ |
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380 | " move.b (%3,%1.w),%0\n" \ |
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381 | " and.l #0x000000ff,%0\n"\ |
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382 | " bra.s 0f\n" \ |
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383 | "1: moveq.l #8,%0\n" \ |
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384 | " add.b (%3,%2.w),%0\n" \ |
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385 | "0:\n" \ |
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386 | : "=&d" ((_output)), "=&d" ((dumby)) \ |
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387 | : "d" ((_value)), "ao" ((__BFFFOtable)) \ |
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388 | : "cc" ) ; \ |
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389 | } |
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390 | #endif /* M68K_HAS_EXTB_L */ |
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391 | |
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392 | #endif |
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393 | |
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394 | /* end of Bitfield handler macros */ |
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395 | |
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396 | /* |
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397 | * Priority handler macros |
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398 | * |
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399 | * These macros perform the following functions: |
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400 | * + return a mask with the bit for this major/minor portion of |
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401 | * of thread priority set. |
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402 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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403 | * into an index into the thread ready chain bit maps |
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404 | */ |
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405 | |
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406 | #define _CPU_Priority_Mask( _bit_number ) \ |
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407 | ( 0x8000 >> (_bit_number) ) |
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408 | |
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409 | #define _CPU_Priority_bits_index( _priority ) \ |
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410 | (_priority) |
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411 | |
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412 | /* end of Priority handler macros */ |
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413 | |
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414 | /* functions */ |
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415 | |
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416 | /* |
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417 | * _CPU_Initialize |
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418 | * |
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419 | * This routine performs CPU dependent initialization. |
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420 | */ |
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421 | |
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422 | void _CPU_Initialize( |
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423 | rtems_cpu_table *cpu_table, |
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424 | void (*thread_dispatch) |
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425 | ); |
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426 | |
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427 | /* |
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428 | * _CPU_ISR_install_raw_handler |
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429 | * |
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430 | * This routine installs a "raw" interrupt handler directly into the |
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431 | * processor's vector table. |
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432 | */ |
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433 | |
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434 | void _CPU_ISR_install_raw_handler( |
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435 | unsigned32 vector, |
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436 | proc_ptr new_handler, |
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437 | proc_ptr *old_handler |
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438 | ); |
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439 | |
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440 | /* |
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441 | * _CPU_ISR_install_vector |
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442 | * |
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443 | * This routine installs an interrupt vector. |
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444 | */ |
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445 | |
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446 | void _CPU_ISR_install_vector( |
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447 | unsigned32 vector, |
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448 | proc_ptr new_handler, |
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449 | proc_ptr *old_handler |
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450 | ); |
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451 | |
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452 | /* |
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453 | * _CPU_Install_interrupt_stack |
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454 | * |
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455 | * This routine installs the hardware interrupt stack pointer. |
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456 | */ |
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457 | |
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458 | void _CPU_Install_interrupt_stack( void ); |
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459 | |
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460 | /* |
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461 | * _CPU_Context_switch |
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462 | * |
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463 | * This routine switches from the run context to the heir context. |
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464 | */ |
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465 | |
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466 | void _CPU_Context_switch( |
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467 | Context_Control *run, |
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468 | Context_Control *heir |
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469 | ); |
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470 | |
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471 | /* |
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472 | * _CPU_Context_save_fp |
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473 | * |
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474 | * This routine saves the floating point context passed to it. |
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475 | */ |
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476 | |
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477 | void _CPU_Context_save_fp( |
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478 | void **fp_context_ptr |
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479 | ); |
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480 | |
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481 | /* |
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482 | * _CPU_Context_restore_fp |
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483 | * |
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484 | * This routine restores the floating point context passed to it. |
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485 | */ |
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486 | |
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487 | void _CPU_Context_restore_fp( |
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488 | void **fp_context_ptr |
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489 | ); |
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490 | |
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491 | #if (M68K_HAS_FPSP_PACKAGE == 1) |
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492 | /* |
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493 | * Hooks for the Floating Point Support Package (FPSP) provided by Motorola |
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494 | * |
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495 | * NOTES: |
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496 | * |
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497 | * Motorola 68k family CPU's before the 68040 used a coprocessor |
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498 | * (68881 or 68882) to handle floating point. The 68040 has internal |
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499 | * floating point support -- but *not* the complete support provided by |
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500 | * the 68881 or 68882. The leftover functions are taken care of by the |
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501 | * M68040 Floating Point Support Package. Quoting from the MC68040 |
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502 | * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040): |
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503 | * |
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504 | * "When used with the M68040FPSP, the MC68040 FPU is fully |
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505 | * compliant with IEEE floating-point standards." |
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506 | * |
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507 | * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and |
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508 | * is invoked early in the application code to insure that proper FP |
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509 | * behavior is installed. This is not left to the BSP to call, since |
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510 | * this would force all applications using that BSP to use FPSP which |
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511 | * is not necessarily desirable. |
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512 | * |
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513 | * There is a similar package for the 68060 but RTEMS does not yet |
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514 | * support the 68060. |
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515 | */ |
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516 | |
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517 | void M68KFPSPInstallExceptionHandlers (void); |
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518 | |
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519 | SCORE_EXTERN int (*_FPSP_install_raw_handler)( |
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520 | unsigned32 vector, |
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521 | proc_ptr new_handler, |
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522 | proc_ptr *old_handler |
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523 | ); |
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524 | |
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525 | #endif |
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526 | |
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527 | |
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528 | #endif |
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529 | |
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530 | #ifdef __cplusplus |
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531 | } |
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532 | #endif |
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533 | |
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534 | #endif |
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535 | /* end of include file */ |
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