source: rtems/c/src/exec/score/cpu/m68k/cpu.h @ 3652ad35

4.104.114.84.95
Last change on this file since 3652ad35 was 3652ad35, checked in by Joel Sherrill <joel.sherrill@…>, on 09/19/95 at 14:53:29

Minor bug fixes to get all targets compilable and running. The
single biggest changes were the expansion of the workspace size
macro to include other types of objects and the increase in the
minimum stack size for most CPUs.

  • Property mode set to 100644
File size: 11.9 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  If defined, this causes some of the macros to initialize their
26 *  variables to zero before doing inline assembly.  This gets rid
27 *  of compile time warnings at the cost of a little execution time
28 *  in some time critical routines.
29 */
30
31#define NO_UNINITIALIZED_WARNINGS
32
33#include <rtems/core/m68k.h>
34#ifndef ASM
35#include <rtems/core/m68ktypes.h>
36#endif
37
38/* conditional compilation parameters */
39
40#define CPU_INLINE_ENABLE_DISPATCH       TRUE
41#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
42
43/*
44 *  Use the m68k's hardware interrupt stack support and have the
45 *  interrupt manager allocate the memory for it.
46 *
47 *  NOTE:  The definitions when M68K_HAS_SEPARATE_STACKS is 0 should
48 *         change when the software interrupt stack support is implemented.
49 */
50
51#if ( M68K_HAS_SEPARATE_STACKS == 1)
52#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
53#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
54#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
55#else
56#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
57#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
58#define CPU_ALLOCATE_INTERRUPT_STACK     FALSE
59#endif
60
61/*
62 *  Some family members have no FP, some have an FPU such as the
63 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
64 */
65
66#if ( M68K_HAS_FPU == 1 )
67#define CPU_HARDWARE_FP     TRUE
68#else
69#define CPU_HARDWARE_FP     FALSE
70#endif
71
72/*
73 *  All tasks are not by default floating point tasks on this CPU.
74 *  The IDLE task does not have a floating point context on this CPU.
75 *  It is safe to use the deferred floating point context switch
76 *  algorithm on this CPU.
77 */
78
79#define CPU_ALL_TASKS_ARE_FP             FALSE
80#define CPU_IDLE_TASK_IS_FP              FALSE
81#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
82
83#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
84#define CPU_STACK_GROWS_UP               FALSE
85#define CPU_STRUCTURE_ALIGNMENT
86
87/* structures */
88
89/*
90 *  Basic integer context for the m68k family.
91 */
92
93typedef struct {
94  unsigned32  sr;                /* (sr) status register */
95  unsigned32  d2;                /* (d2) data register 2 */
96  unsigned32  d3;                /* (d3) data register 3 */
97  unsigned32  d4;                /* (d4) data register 4 */
98  unsigned32  d5;                /* (d5) data register 5 */
99  unsigned32  d6;                /* (d6) data register 6 */
100  unsigned32  d7;                /* (d7) data register 7 */
101  void       *a2;                /* (a2) address register 2 */
102  void       *a3;                /* (a3) address register 3 */
103  void       *a4;                /* (a4) address register 4 */
104  void       *a5;                /* (a5) address register 5 */
105  void       *a6;                /* (a6) address register 6 */
106  void       *a7_msp;            /* (a7) master stack pointer */
107}   Context_Control;
108
109/*
110 *  FP context save area for the M68881/M68882 numeric coprocessors.
111 */
112
113typedef struct {
114  unsigned8   fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
115                                    /*    96 bytes for FMOVEM FP0-7      */
116                                    /*    12 bytes for FMOVEM CREGS      */
117                                    /*     4 bytes for non-null flag     */
118} Context_Control_fp;
119
120/*
121 *  The following structure defines the set of information saved
122 *  on the current stack by RTEMS upon receipt of each interrupt.
123 */
124
125typedef struct {
126  unsigned32   TBD;   /* XXX Fix for this CPU */
127} CPU_Interrupt_frame;
128
129/*
130 *  The following table contains the information required to configure
131 *  the m68k specific parameters.
132 */
133
134typedef struct {
135  void       (*pretasking_hook)( void );
136  void       (*predriver_hook)( void );
137  void       (*postdriver_hook)( void );
138  void       (*idle_task)( void );
139  boolean      do_zero_of_workspace;
140  unsigned32   interrupt_stack_size;
141  unsigned32   extra_system_initialization_stack;
142  m68k_isr    *interrupt_vector_table;
143}   rtems_cpu_table;
144
145/* variables */
146
147EXTERN void               *_CPU_Interrupt_stack_low;
148EXTERN void               *_CPU_Interrupt_stack_high;
149
150/* constants */
151
152/*
153 *  This defines the number of levels and the mask used to pick those
154 *  bits out of a thread mode.
155 */
156
157#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
158#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
159
160/*
161 *  context size area for floating point
162 */
163
164#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
165
166/*
167 *  extra stack required by system initialization thread
168 */
169
170#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 1024
171
172/*
173 *  m68k family supports 256 distinct vectors.
174 */
175
176#define CPU_INTERRUPT_NUMBER_OF_VECTORS  256
177
178/*
179 *  Minimum size of a thread's stack.
180 */
181
182#define CPU_STACK_MINIMUM_SIZE           1024
183
184/*
185 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
186 */
187
188#define CPU_ALIGNMENT                    4
189#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
190#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
191
192/*
193 *  On m68k thread stacks require no further alignment after allocation
194 *  from the Workspace.
195 */
196
197#define CPU_STACK_ALIGNMENT        0
198
199/* macros */
200
201/*
202 *  ISR handler macros
203 *
204 *  These macros perform the following functions:
205 *     + disable all maskable CPU interrupts
206 *     + restore previous interrupt level (enable)
207 *     + temporarily restore interrupts (flash)
208 *     + set a particular level
209 */
210
211#define _CPU_ISR_Disable( _level ) \
212  m68k_disable_interrupts( _level )
213
214#define _CPU_ISR_Enable( _level ) \
215  m68k_enable_interrupts( _level )
216
217#define _CPU_ISR_Flash( _level ) \
218  m68k_flash_interrupts( _level )
219
220#define _CPU_ISR_Set_level( _newlevel ) \
221   m68k_set_interrupt_level( _newlevel )
222
223unsigned32 _CPU_ISR_Get_level( void );
224
225/* end of ISR handler macros */
226
227/*
228 *  Context handler macros
229 *
230 *  These macros perform the following functions:
231 *     + initialize a context area
232 *     + restart the current thread
233 *     + calculate the initial pointer into a FP context area
234 *     + initialize an FP context area
235 */
236
237#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
238                                 _isr, _entry_point ) \
239   do { \
240     void   *_stack; \
241     \
242     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
243     _stack                  = (void *)(_stack_base) + (_size) - 4; \
244     (_the_context)->a7_msp  = _stack; \
245     *(void **)_stack = (_entry_point); \
246   } while ( 0 )
247
248#define _CPU_Context_Restart_self( _the_context ) \
249  { asm volatile( "movew %0,%%sr ; " \
250                  "moval %1,%%a7 ; " \
251                  "rts"  \
252        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
253        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
254  }
255
256#define _CPU_Context_Fp_start( _base, _offset ) \
257   ((void *) \
258     _Addresses_Add_offset( \
259        (_base), \
260        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
261     ) \
262   )
263
264#define _CPU_Context_Initialize_fp( _fp_area ) \
265   { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
266     \
267     *(--(_fp_context)) = 0; \
268     *(_fp_area) = (unsigned8 *)(_fp_context); \
269   }
270
271/* end of Context handler macros */
272
273/*
274 *  Fatal Error manager macros
275 *
276 *  These macros perform the following functions:
277 *    + disable interrupts and halt the CPU
278 */
279
280#define _CPU_Fatal_halt( _error ) \
281  { asm volatile( "movl  %0,%%d0; " \
282                  "orw   #0x0700,%%sr; " \
283                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
284  }
285
286/* end of Fatal Error manager macros */
287
288/*
289 *  Bitfield handler macros
290 *
291 *  These macros perform the following functions:
292 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
293 *
294 *  NOTE:
295 *
296 *    It appears that on the M68020 bitfield are always 32 bits wide
297 *    when in a register.  This code forces the bitfield to be in
298 *    memory (it really always is anyway). This allows us to
299 *    have a real 16 bit wide bitfield which operates "correctly."
300 */
301
302#if ( M68K_HAS_BFFFO == 1 )
303#ifdef NO_UNINITIALIZED_WARNINGS
304
305#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
306  { \
307    register void *__base = (void *)&(_value); \
308    \
309    (_output) = 0;  /* avoids warnings */ \
310    asm volatile( "bfffo (%0),#0,#16,%1" \
311                   : "=a" (__base), "=d" ((_output)) \
312                   : "0"  (__base), "1" ((_output))  ) ; \
313  }
314#else
315#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
316  { \
317    register void *__base = (void *)&(_value); \
318    \
319    asm volatile( "bfffo (%0),#0,#16,%1" \
320                   : "=a" (__base), "=d" ((_output)) \
321                   : "0"  (__base), "1" ((_output))  ) ; \
322  }
323#endif
324
325#else
326
327#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
328  { \
329    extern const unsigned char __log2table[256]; \
330    \
331    asm     ( "   tst.b   %1\n"           /* check for bits in ls byte */ \
332              "   beq.s   0f\n"           /* branch if no bits set */ \
333              "   moveq.l #0,%0\n"        /* set up for bits 0..7 */ \
334              "   andi.w  #0x00ff,%1\n"   /* clear ms byte for add inst */ \
335              "   bra.s   1f\n"           /* go add */ \
336              "0: moveq.l #8,%0\n"        /* set up for bits 8..15 */ \
337              "   lsr.w   #8,%1\n"        /* shift ms byte to ls byte, */ \
338                                          /*   filling ms byte with 0s */ \
339              "1: add.b   (%2,%1.w),%0\n" /* add offset for bit pattern */ \
340               : "=&d" ((_output)) \
341               : "d" ((_value)), "ao" (__log2table) \
342               : "cc" ) ; \
343  }
344
345#endif
346
347/* end of Bitfield handler macros */
348
349/*
350 *  Priority handler macros
351 *
352 *  These macros perform the following functions:
353 *    + return a mask with the bit for this major/minor portion of
354 *      of thread priority set.
355 *    + translate the bit number returned by "Bitfield_find_first_bit"
356 *      into an index into the thread ready chain bit maps
357 */
358
359#define _CPU_Priority_Mask( _bit_number ) \
360  ( 0x8000 >> (_bit_number) )
361
362#if ( M68K_HAS_BFFFO == 1 )
363#define _CPU_Priority_Bits_index( _priority ) \
364  (_priority)
365#else
366#define _CPU_Priority_Bits_index( _priority ) \
367  (15 - (_priority))
368#endif
369
370/* end of Priority handler macros */
371
372/* functions */
373
374/*
375 *  _CPU_Initialize
376 *
377 *  This routine performs CPU dependent initialization.
378 */
379
380void _CPU_Initialize(
381  rtems_cpu_table  *cpu_table,
382  void      (*thread_dispatch)
383);
384
385/*
386 *  _CPU_ISR_install_raw_handler
387 *
388 *  This routine installs a "raw" interrupt handler directly into the
389 *  processor's vector table.
390 */
391 
392void _CPU_ISR_install_raw_handler(
393  unsigned32  vector,
394  proc_ptr    new_handler,
395  proc_ptr   *old_handler
396);
397
398/*
399 *  _CPU_ISR_install_vector
400 *
401 *  This routine installs an interrupt vector.
402 */
403
404void _CPU_ISR_install_vector(
405  unsigned32       vector,
406  proc_ptr         new_handler,
407  proc_ptr        *old_handler
408);
409
410/*
411 *  _CPU_Install_interrupt_stack
412 *
413 *  This routine installs the hardware interrupt stack pointer.
414 */
415
416void _CPU_Install_interrupt_stack( void );
417
418/*
419 *  _CPU_Context_switch
420 *
421 *  This routine switches from the run context to the heir context.
422 */
423
424void _CPU_Context_switch(
425  Context_Control  *run,
426  Context_Control  *heir
427);
428
429/*
430 *  _CPU_Context_save_fp
431 *
432 *  This routine saves the floating point context passed to it.
433 */
434
435void _CPU_Context_restore_fp(
436  void **fp_context_ptr
437);
438
439/*
440 *  _CPU_Context_restore_fp
441 *
442 *  This routine restores the floating point context passed to it.
443 */
444
445void _CPU_Context_save_fp(
446  void **fp_context_ptr
447);
448
449#ifdef __cplusplus
450}
451#endif
452
453#endif
454/* end of include file */
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