[ac7d5ef0] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the Motorola |
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| 4 | * m68xxx processor family. |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * All rights assigned to U.S. Government, 1994. |
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| 9 | * |
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| 10 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 11 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 12 | * notice must appear in all copies of this file and its derivatives. |
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| 13 | * |
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| 14 | * $Id$ |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef __CPU_h |
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| 18 | #define __CPU_h |
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| 19 | |
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| 20 | #ifdef __cplusplus |
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| 21 | extern "C" { |
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| 22 | #endif |
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| 23 | |
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| 24 | /* |
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| 25 | * If defined, this causes some of the macros to initialize their |
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| 26 | * variables to zero before doing inline assembly. This gets rid |
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| 27 | * of compile time warnings at the cost of a little execution time |
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| 28 | * in some time critical routines. |
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| 29 | */ |
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| 30 | |
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| 31 | #define NO_UNINITIALIZED_WARNINGS |
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| 32 | |
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[88d594a] | 33 | #include <rtems/m68k.h> |
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| 34 | #ifndef ASM |
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| 35 | #include <rtems/m68ktypes.h> |
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| 36 | #endif |
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[ac7d5ef0] | 37 | |
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| 38 | /* conditional compilation parameters */ |
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| 39 | |
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| 40 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 41 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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| 42 | |
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| 43 | /* |
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| 44 | * Use the m68k's hardware interrupt stack support and have the |
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| 45 | * interrupt manager allocate the memory for it. |
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| 46 | */ |
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| 47 | |
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| 48 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 49 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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| 50 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 51 | |
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| 52 | /* |
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| 53 | * Some family members have no FP, some have an FPU such as the |
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| 54 | * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). |
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| 55 | */ |
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| 56 | |
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| 57 | #if ( M68K_HAS_FPU == 1 ) |
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| 58 | #define CPU_HARDWARE_FP TRUE |
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| 59 | #else |
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| 60 | #define CPU_HARDWARE_FP FALSE |
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| 61 | #endif |
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| 62 | |
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| 63 | /* |
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| 64 | * All tasks are not by default floating point tasks on this CPU. |
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| 65 | * The IDLE task does not have a floating point context on this CPU. |
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| 66 | * It is safe to use the deferred floating point context switch |
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| 67 | * algorithm on this CPU. |
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| 68 | */ |
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| 69 | |
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| 70 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 71 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 72 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 73 | |
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| 74 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 75 | #define CPU_STACK_GROWS_UP FALSE |
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| 76 | #define CPU_STRUCTURE_ALIGNMENT |
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| 77 | |
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| 78 | /* structures */ |
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| 79 | |
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| 80 | /* |
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| 81 | * Basic integer context for the m68k family. |
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| 82 | */ |
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| 83 | |
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| 84 | typedef struct { |
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| 85 | unsigned32 sr; /* (sr) status register */ |
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| 86 | unsigned32 d2; /* (d2) data register 2 */ |
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| 87 | unsigned32 d3; /* (d3) data register 3 */ |
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| 88 | unsigned32 d4; /* (d4) data register 4 */ |
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| 89 | unsigned32 d5; /* (d5) data register 5 */ |
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| 90 | unsigned32 d6; /* (d6) data register 6 */ |
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| 91 | unsigned32 d7; /* (d7) data register 7 */ |
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| 92 | void *a2; /* (a2) address register 2 */ |
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| 93 | void *a3; /* (a3) address register 3 */ |
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| 94 | void *a4; /* (a4) address register 4 */ |
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| 95 | void *a5; /* (a5) address register 5 */ |
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| 96 | void *a6; /* (a6) address register 6 */ |
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| 97 | void *a7_msp; /* (a7) master stack pointer */ |
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| 98 | } Context_Control; |
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| 99 | |
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| 100 | /* |
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| 101 | * FP context save area for the M68881/M68882 numeric coprocessors. |
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| 102 | */ |
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| 103 | |
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| 104 | typedef struct { |
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| 105 | unsigned8 fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */ |
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| 106 | /* 96 bytes for FMOVEM FP0-7 */ |
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| 107 | /* 12 bytes for FMOVEM CREGS */ |
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| 108 | /* 4 bytes for non-null flag */ |
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| 109 | } Context_Control_fp; |
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| 110 | |
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| 111 | /* |
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| 112 | * The following structure defines the set of information saved |
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| 113 | * on the current stack by RTEMS upon receipt of each interrupt. |
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| 114 | */ |
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| 115 | |
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| 116 | typedef struct { |
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| 117 | unsigned32 TBD; /* XXX Fix for this CPU */ |
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| 118 | } CPU_Interrupt_frame; |
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| 119 | |
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| 120 | /* |
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| 121 | * The following table contains the information required to configure |
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| 122 | * the m68k specific parameters. |
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| 123 | */ |
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| 124 | |
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| 125 | typedef struct { |
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| 126 | void (*pretasking_hook)( void ); |
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| 127 | void (*predriver_hook)( void ); |
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| 128 | void (*postdriver_hook)( void ); |
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| 129 | void (*idle_task)( void ); |
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| 130 | boolean do_zero_of_workspace; |
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| 131 | unsigned32 interrupt_stack_size; |
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| 132 | unsigned32 extra_system_initialization_stack; |
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| 133 | m68k_isr *interrupt_vector_table; |
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| 134 | } rtems_cpu_table; |
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| 135 | |
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| 136 | /* variables */ |
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| 137 | |
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| 138 | EXTERN void *_CPU_Interrupt_stack_low; |
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| 139 | EXTERN void *_CPU_Interrupt_stack_high; |
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| 140 | |
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| 141 | /* constants */ |
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| 142 | |
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| 143 | /* |
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| 144 | * This defines the number of levels and the mask used to pick those |
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| 145 | * bits out of a thread mode. |
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| 146 | */ |
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| 147 | |
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| 148 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ |
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| 149 | #define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ |
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| 150 | |
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| 151 | /* |
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| 152 | * context size area for floating point |
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| 153 | */ |
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| 154 | |
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| 155 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 156 | |
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| 157 | /* |
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| 158 | * extra stack required by system initialization thread |
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| 159 | */ |
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| 160 | |
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| 161 | #define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 1024 |
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| 162 | |
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| 163 | /* |
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| 164 | * m68k family supports 256 distinct vectors. |
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| 165 | */ |
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| 166 | |
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| 167 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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| 168 | |
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| 169 | /* |
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| 170 | * Minimum size of a thread's stack. |
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| 171 | * |
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| 172 | * NOTE: 256 bytes is probably too low in most cases. |
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| 173 | */ |
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| 174 | |
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| 175 | #define CPU_STACK_MINIMUM_SIZE 256 |
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| 176 | |
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| 177 | /* |
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| 178 | * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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| 179 | */ |
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| 180 | |
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| 181 | #define CPU_ALIGNMENT 4 |
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| 182 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 183 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 184 | |
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| 185 | /* |
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| 186 | * On m68k thread stacks require no further alignment after allocation |
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| 187 | * from the Workspace. |
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| 188 | */ |
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| 189 | |
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| 190 | #define CPU_STACK_ALIGNMENT 0 |
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| 191 | |
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| 192 | /* macros */ |
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| 193 | |
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| 194 | /* |
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| 195 | * ISR handler macros |
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| 196 | * |
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| 197 | * These macros perform the following functions: |
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| 198 | * + disable all maskable CPU interrupts |
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| 199 | * + restore previous interrupt level (enable) |
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| 200 | * + temporarily restore interrupts (flash) |
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| 201 | * + set a particular level |
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| 202 | */ |
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| 203 | |
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| 204 | #define _CPU_ISR_Disable( _level ) \ |
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| 205 | m68k_disable_interrupts( _level ) |
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| 206 | |
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| 207 | #define _CPU_ISR_Enable( _level ) \ |
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| 208 | m68k_enable_interrupts( _level ) |
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| 209 | |
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| 210 | #define _CPU_ISR_Flash( _level ) \ |
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| 211 | m68k_flash_interrupts( _level ) |
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| 212 | |
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| 213 | #define _CPU_ISR_Set_level( _newlevel ) \ |
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| 214 | m68k_set_interrupt_level( _newlevel ) |
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| 215 | |
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| 216 | /* end of ISR handler macros */ |
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| 217 | |
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| 218 | /* |
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| 219 | * Context handler macros |
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| 220 | * |
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| 221 | * These macros perform the following functions: |
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| 222 | * + initialize a context area |
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| 223 | * + restart the current thread |
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| 224 | * + calculate the initial pointer into a FP context area |
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| 225 | * + initialize an FP context area |
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| 226 | */ |
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| 227 | |
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| 228 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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| 229 | _isr, _entry_point ) \ |
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| 230 | do { \ |
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| 231 | void *_stack; \ |
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| 232 | \ |
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| 233 | (_the_context)->sr = 0x3000 | ((_isr) << 8); \ |
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| 234 | _stack = (void *)(_stack_base) + (_size) - 4; \ |
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| 235 | (_the_context)->a7_msp = _stack; \ |
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| 236 | *(void **)_stack = (_entry_point); \ |
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| 237 | } while ( 0 ) |
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| 238 | |
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| 239 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 240 | { asm volatile( "movew %0,%%sr ; " \ |
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| 241 | "moval %1,%%a7 ; " \ |
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| 242 | "rts" \ |
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| 243 | : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \ |
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| 244 | : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \ |
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| 245 | } |
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| 246 | |
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| 247 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 248 | ((void *) \ |
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| 249 | _Addresses_Add_offset( \ |
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| 250 | (_base), \ |
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| 251 | (_offset) + CPU_CONTEXT_FP_SIZE - 4 \ |
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| 252 | ) \ |
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| 253 | ) |
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| 254 | |
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| 255 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 256 | { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \ |
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| 257 | \ |
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| 258 | *(--(_fp_context)) = 0; \ |
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| 259 | *(_fp_area) = (unsigned8 *)(_fp_context); \ |
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| 260 | } |
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| 261 | |
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| 262 | /* end of Context handler macros */ |
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| 263 | |
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| 264 | /* |
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| 265 | * Fatal Error manager macros |
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| 266 | * |
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| 267 | * These macros perform the following functions: |
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| 268 | * + disable interrupts and halt the CPU |
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| 269 | */ |
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| 270 | |
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| 271 | #define _CPU_Fatal_halt( _error ) \ |
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| 272 | { asm volatile( "movl %0,%%d0; " \ |
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| 273 | "orw #0x0700,%%sr; " \ |
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| 274 | "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ |
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| 275 | } |
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| 276 | |
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| 277 | /* end of Fatal Error manager macros */ |
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| 278 | |
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| 279 | /* |
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| 280 | * Bitfield handler macros |
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| 281 | * |
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| 282 | * These macros perform the following functions: |
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| 283 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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| 284 | * |
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| 285 | * NOTE: |
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| 286 | * |
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| 287 | * It appears that on the M68020 bitfield are always 32 bits wide |
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| 288 | * when in a register. This code forces the bitfield to be in |
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| 289 | * memory (it really always is anyway). This allows us to |
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| 290 | * have a real 16 bit wide bitfield which operates "correctly." |
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| 291 | */ |
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| 292 | |
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| 293 | #if ( M68K_HAS_BFFFO == 1 ) |
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| 294 | #ifdef NO_UNINITIALIZED_WARNINGS |
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| 295 | |
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| 296 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 297 | { \ |
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| 298 | register void *__base = (void *)&(_value); \ |
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| 299 | \ |
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| 300 | (_output) = 0; /* avoids warnings */ \ |
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| 301 | asm volatile( "bfffo (%0),#0,#16,%1" \ |
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| 302 | : "=a" (__base), "=d" ((_output)) \ |
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| 303 | : "0" (__base), "1" ((_output)) ) ; \ |
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| 304 | } |
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| 305 | #else |
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| 306 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 307 | { \ |
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| 308 | register void *__base = (void *)&(_value); \ |
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| 309 | \ |
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| 310 | asm volatile( "bfffo (%0),#0,#16,%1" \ |
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| 311 | : "=a" (__base), "=d" ((_output)) \ |
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| 312 | : "0" (__base), "1" ((_output)) ) ; \ |
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| 313 | } |
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| 314 | #endif |
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| 315 | |
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| 316 | #else |
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| 317 | |
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| 318 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 319 | (_output) = 0 /* avoids warnings */ |
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| 320 | |
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| 321 | #warning "FIX ME... NEEDS A SOFTWARE BFFFO IMPLEMENTATION" |
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| 322 | #warning "SEE no_cpu/cpu.h FOR POSSIBLE ALGORITHMS" |
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| 323 | |
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| 324 | #endif |
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| 325 | |
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| 326 | /* end of Bitfield handler macros */ |
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| 327 | |
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| 328 | /* |
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| 329 | * Priority handler macros |
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| 330 | * |
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| 331 | * These macros perform the following functions: |
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| 332 | * + return a mask with the bit for this major/minor portion of |
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| 333 | * of thread priority set. |
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| 334 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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| 335 | * into an index into the thread ready chain bit maps |
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| 336 | */ |
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| 337 | |
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| 338 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 339 | ( 0x8000 >> (_bit_number) ) |
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| 340 | |
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| 341 | #define _CPU_Priority_Bits_index( _priority ) \ |
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| 342 | (_priority) |
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| 343 | |
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| 344 | /* end of Priority handler macros */ |
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| 345 | |
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| 346 | /* functions */ |
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| 347 | |
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| 348 | /* |
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| 349 | * _CPU_Initialize |
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| 350 | * |
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| 351 | * This routine performs CPU dependent initialization. |
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| 352 | */ |
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| 353 | |
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| 354 | void _CPU_Initialize( |
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| 355 | rtems_cpu_table *cpu_table, |
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| 356 | void (*thread_dispatch) |
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| 357 | ); |
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| 358 | |
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| 359 | /* |
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| 360 | * _CPU_ISR_install_vector |
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| 361 | * |
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| 362 | * This routine installs an interrupt vector. |
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| 363 | */ |
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| 364 | |
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| 365 | void _CPU_ISR_install_vector( |
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| 366 | unsigned32 vector, |
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| 367 | proc_ptr new_handler, |
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| 368 | proc_ptr *old_handler |
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| 369 | ); |
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| 370 | |
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| 371 | /* |
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| 372 | * _CPU_Install_interrupt_stack |
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| 373 | * |
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| 374 | * This routine installs the hardware interrupt stack pointer. |
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| 375 | */ |
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| 376 | |
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| 377 | void _CPU_Install_interrupt_stack( void ); |
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| 378 | |
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| 379 | /* |
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| 380 | * _CPU_Context_switch |
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| 381 | * |
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| 382 | * This routine switches from the run context to the heir context. |
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| 383 | */ |
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| 384 | |
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| 385 | void _CPU_Context_switch( |
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| 386 | Context_Control *run, |
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| 387 | Context_Control *heir |
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| 388 | ); |
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| 389 | |
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| 390 | /* |
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| 391 | * _CPU_Context_save_fp |
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| 392 | * |
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| 393 | * This routine saves the floating point context passed to it. |
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| 394 | */ |
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| 395 | |
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| 396 | void _CPU_Context_restore_fp( |
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| 397 | void **fp_context_ptr |
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| 398 | ); |
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| 399 | |
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| 400 | /* |
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| 401 | * _CPU_Context_restore_fp |
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| 402 | * |
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| 403 | * This routine restores the floating point context passed to it. |
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| 404 | */ |
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| 405 | |
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| 406 | void _CPU_Context_save_fp( |
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| 407 | void **fp_context_ptr |
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| 408 | ); |
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| 409 | |
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| 410 | #ifdef __cplusplus |
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| 411 | } |
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| 412 | #endif |
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| 413 | |
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| 414 | #endif |
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| 415 | /* end of include file */ |
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