source: rtems/c/src/exec/score/cpu/i960/rtems/score/i960.h @ d392168

4.104.114.84.9
Last change on this file since d392168 was d392168, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 26, 1999 at 9:14:20 PM

Typo causing compilation failure spotted by Ralf Corsepius and
fixed by Joel.

  • Property mode set to 100644
File size: 12.1 KB
Line 
1/*  i960.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __i960_h
18#define __i960_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  This file contains the information required to build
26 *  RTEMS for a particular member of the Intel i960
27 *  family.  It does this by setting variables to indicate
28 *  which implementation dependent features are present
29 *  in a particular member of the family.
30 *
31 *  NOTE: For now i960 support is for models without an FPU.
32 *        The stubs for FP routines are in  place so only need to be filled in.
33 *
34 *  NOTE: RTEMS defines a canonical name for each cpu model.
35 */
36
37#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
38
39#define CPU_MODEL_NAME  "i960ca"
40#define __RTEMS_I960CA__
41#define I960_HAS_FPU 0
42
43#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
44
45#define CPU_MODEL_NAME  "i960ha"
46#define __RTEMS_I960HA__
47#define I960_HAS_FPU 0
48
49#else
50
51#error "Unsupported CPU Model"
52
53#endif
54
55/*
56 *  Define the name of the CPU family.
57 */
58
59#define CPU_NAME "Intel i960"
60
61#ifndef ASM
62
63/*
64 * XXX    should have an ifdef here and have stuff for the other
65 * XXX    family members...
66 */
67 
68#if defined(__RTEMS_I960CA__)
69 
70/* i960CA control structures */
71 
72/* Intel i960CA Control Table */
73 
74typedef struct {
75                            /* Control Group 0 */
76  unsigned int ipb0;              /* IP breakpoint 0 */
77  unsigned int ipb1;              /* IP breakpoint 1 */
78  unsigned int dab0;              /* data address breakpoint 0 */
79  unsigned int dab1;              /* data address breakpoint 1 */
80                            /* Control Group 1 */
81  unsigned int imap0;             /* interrupt map 0 */
82  unsigned int imap1;             /* interrupt map 1 */
83  unsigned int imap2;             /* interrupt map 2 */
84  unsigned int icon;              /* interrupt control */
85                            /* Control Group 2 */
86  unsigned int mcon0;             /* memory region 0 configuration */
87  unsigned int mcon1;             /* memory region 1 configuration */
88  unsigned int mcon2;             /* memory region 2 configuration */
89  unsigned int mcon3;             /* memory region 3 configuration */
90                            /* Control Group 3 */
91  unsigned int mcon4;             /* memory region 4 configuration */
92  unsigned int mcon5;             /* memory region 5 configuration */
93  unsigned int mcon6;             /* memory region 6 configuration */
94  unsigned int mcon7;             /* memory region 7 configuration */
95                            /* Control Group 4 */
96  unsigned int mcon8;             /* memory region 8 configuration */
97  unsigned int mcon9;             /* memory region 9 configuration */
98  unsigned int mcon10;            /* memory region 10 configuration */
99  unsigned int mcon11;            /* memory region 11 configuration */
100                            /* Control Group 5 */
101  unsigned int mcon12;            /* memory region 12 configuration */
102  unsigned int mcon13;            /* memory region 13 configuration */
103  unsigned int mcon14;            /* memory region 14 configuration */
104  unsigned int mcon15;            /* memory region 15 configuration */
105                            /* Control Group 6 */
106  unsigned int reserved;          /* reserved */
107  unsigned int bpcon;             /* breakpoint control */
108  unsigned int tc;                /* trace control */
109  unsigned int bcon;              /* bus configuration control */
110}   i960ca_control_table;
111 
112/* Intel i960CA Processor Control Block */
113 
114typedef struct {
115  unsigned int    *fault_tbl;     /* fault table base address */
116  i960ca_control_table
117                  *control_tbl;   /* control table base address */
118  unsigned int     initial_ac;    /* AC register initial value */
119  unsigned int     fault_config;  /* fault configuration word */
120  void           **intr_tbl;      /* interrupt table base address */
121  void            *sys_proc_tbl;  /* system procedure table
122                                     base address */
123  unsigned int     reserved;      /* reserved */
124  unsigned int    *intr_stack;    /* interrupt stack pointer */
125  unsigned int     ins_cache_cfg; /* instruction cache
126                                     configuration word */
127  unsigned int     reg_cache_cfg; /* register cache configuration word */
128}   i960ca_PRCB;
129
130typedef i960ca_control_table i960_control_table;
131typedef i960ca_PRCB i960_PRCB;
132
133#elif defined(__RTEMS_I960HA__)
134
135/* i960HA control structures */
136
137/* Intel i960HA Control Table */
138
139typedef struct {
140                            /* Control Group 0 */
141  unsigned int ipb0;              /* IP breakpoint 0 */
142  unsigned int ipb1;              /* IP breakpoint 1 */
143  unsigned int dab0;              /* data address breakpoint 0 */
144  unsigned int dab1;              /* data address breakpoint 1 */
145                            /* Control Group 1 */
146  unsigned int imap0;             /* interrupt map 0 */
147  unsigned int imap1;             /* interrupt map 1 */
148  unsigned int imap2;             /* interrupt map 2 */
149  unsigned int icon;              /* interrupt control */
150                            /* Control Group 2 */
151  unsigned int mcon0;             /* memory region 0 configuration */
152  unsigned int mcon1;             /* memory region 1 configuration */
153  unsigned int mcon2;             /* memory region 2 configuration */
154  unsigned int mcon3;             /* memory region 3 configuration */
155                            /* Control Group 3 */
156  unsigned int mcon4;             /* memory region 4 configuration */
157  unsigned int mcon5;             /* memory region 5 configuration */
158  unsigned int mcon6;             /* memory region 6 configuration */
159  unsigned int mcon7;             /* memory region 7 configuration */
160                            /* Control Group 4 */
161  unsigned int mcon8;             /* memory region 8 configuration */
162  unsigned int mcon9;             /* memory region 9 configuration */
163  unsigned int mcon10;            /* memory region 10 configuration */
164  unsigned int mcon11;            /* memory region 11 configuration */
165                            /* Control Group 5 */
166  unsigned int mcon12;            /* memory region 12 configuration */
167  unsigned int mcon13;            /* memory region 13 configuration */
168  unsigned int mcon14;            /* memory region 14 configuration */
169  unsigned int mcon15;            /* memory region 15 configuration */
170                            /* Control Group 6 */
171  unsigned int reserved;          /* reserved */
172  unsigned int bpcon;             /* breakpoint control */
173  unsigned int tc;                /* trace control */
174  unsigned int bcon;              /* bus configuration control */
175}   i960ha_control_table;
176
177/* Intel i960HA Processor Control Block */
178
179typedef struct {
180  unsigned int    *fault_tbl;     /* fault table base address */
181  i960ha_control_table
182                  *control_tbl;   /* control table base address */
183  unsigned int     initial_ac;    /* AC register initial value */
184  unsigned int     fault_config;  /* fault configuration word */
185  void           **intr_tbl;      /* interrupt table base address */
186  void            *sys_proc_tbl;  /* system procedure table
187                                     base address */
188  unsigned int     reserved;      /* reserved */
189  unsigned int    *intr_stack;    /* interrupt stack pointer */
190  unsigned int     ins_cache_cfg; /* instruction cache
191                                     configuration word */
192  unsigned int     reg_cache_cfg; /* register cache configuration word */
193}   i960ha_PRCB;
194
195typedef i960ha_control_table i960_control_table;
196typedef i960ha_PRCB i960_PRCB;
197
198#endif
199
200/*
201 *  Interrupt Level Routines
202 */
203
204#define i960_disable_interrupts( oldlevel ) \
205  { (oldlevel) = 0x1f0000; \
206    asm volatile ( "modpc   0,%1,%1" \
207                       : "=d" ((oldlevel)) \
208                       : "0"  ((oldlevel)) ); \
209  }
210
211#define i960_enable_interrupts( oldlevel ) \
212  { unsigned int _mask = 0x1f0000; \
213    asm volatile ( "modpc   0,%0,%1" \
214                       : "=d" (_mask), "=d" ((oldlevel)) \
215                       : "0"  (_mask), "1"  ((oldlevel)) ); \
216  }
217
218#define i960_flash_interrupts( oldlevel ) \
219  { unsigned int _mask = 0x1f0000; \
220    asm volatile ( "modpc   0,%0,%1 ; \
221                    mov     %0,%1 ; \
222                    modpc   0,%0,%1"  \
223                       : "=d" (_mask), "=d" ((oldlevel)) \
224                       : "0"  (_mask), "1"  ((oldlevel)) ); \
225  }
226
227#define i960_get_interrupt_level( _level ) \
228  { \
229    i960_disable_interrupts( _level ); \
230    i960_enable_interrupts( _level ); \
231    (_level) = ((_level) & 0x1f0000) >> 16; \
232  } while ( 0 )
233
234#define i960_atomic_modify( mask, addr, prev ) \
235 { register unsigned int  _mask = (mask); \
236   register unsigned int *_addr = (unsigned int *)(addr); \
237   asm volatile( "atmod  %0,%1,%1" \
238                  : "=d" (_addr), "=d" (_mask) \
239                  : "0"  (_addr), "1"  (_mask) ); \
240   (prev) = _mask; \
241 }
242
243
244#define atomic_modify( _mask, _address, _previous ) \
245  i960_atomic_modify( _mask, _address, _previous )
246
247#define i960_enable_tracing() \
248 { register unsigned int _pc = 0x1; \
249   asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
250 }
251
252#define i960_unmask_intr( xint ) \
253 { register unsigned int _mask= (1<<(xint)); \
254   asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
255 }
256
257#define i960_mask_intr( xint ) \
258 { register unsigned int _mask= (1<<(xint)); \
259   asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
260 }
261
262#define i960_clear_intr( xint ) \
263 { register unsigned int _xint=(xint); \
264asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
265                  bbs    %0,sf0, loop_til_cleared" \
266                  : "=d" (_xint) : "0" (_xint) ); \
267 }
268
269#define i960_reload_ctl_group( group ) \
270 { register int _cmd = ((group)|0x400) ; \
271   asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
272 }
273
274#define i960_cause_intr( intr ) \
275 { register int _intr = (intr); \
276   asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
277 }
278
279#define i960_soft_reset( prcb ) \
280 { register i960ca_PRCB *_prcb = (prcb); \
281   register unsigned int         *_next=0; \
282   register unsigned int          _cmd  = 0x30000; \
283   asm volatile( "lda    next,%1; \
284                  sysctl %0,%1,%2; \
285            next: mov    g0,g0" \
286                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
287                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
288 }
289
290static inline unsigned int i960_pend_intrs()
291{ register unsigned int _intr=0;
292  asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
293  return ( _intr );
294}
295
296static inline unsigned int i960_mask_intrs()
297{ register unsigned int _intr=0;
298  asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
299  return( _intr );
300}
301
302static inline unsigned int i960_get_fp()
303{ register unsigned int _fp=0;
304  asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
305  return ( _fp );
306}
307
308/*
309 *  The following routine swaps the endian format of an unsigned int.
310 *  It must be static because it is referenced indirectly.
311 *
312 *  This version is based on code presented in Vol. 4, No. 4 of
313 *  Insight 960.  It is certainly something you wouldn't think
314 *  of on your own.
315 */
316
317static inline unsigned int CPU_swap_u32(
318  unsigned int value
319)
320{
321  register unsigned int to_swap = value;
322  register unsigned int temp    = 0xFF00FF00;
323  register unsigned int swapped = 0;
324
325                                            /*  to_swap      swapped  */
326  asm volatile ( "rotate  16,%0,%2 ;"       /* 0x12345678  0x56781234 */
327                 "modify  %1,%0,%2 ;"       /* 0x12345678  0x12785634 */
328                 "rotate  8,%2,%2"          /* 0x12345678  0x78563412 */
329                 : "=r" (to_swap), "=r" (temp), "=r" (swapped)
330                 : "0" (to_swap), "1" (temp), "2" (swapped)
331               );
332  return( swapped );
333}
334
335#define CPU_swap_u16( value ) \
336  (((value&0xff) << 8) | ((value >> 8)&0xff))
337
338#ifdef __cplusplus
339}
340#endif
341
342#endif /* !ASM */
343
344#endif
345/* end of include file */
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