source: rtems/c/src/exec/score/cpu/i960/rtems/score/i960.h @ bc85fd5a

4.104.114.84.95
Last change on this file since bc85fd5a was bc85fd5a, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 11, 2000 at 7:31:04 PM

Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.

  • Property mode set to 100644
File size: 5.1 KB
Line 
1/*  i960.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __i960_h
17#define __i960_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/*
24 *  This file contains the information required to build
25 *  RTEMS for a particular member of the Intel i960
26 *  family.  It does this by setting variables to indicate
27 *  which implementation dependent features are present
28 *  in a particular member of the family.
29 *
30 *  NOTE: For now i960 support is for models without an FPU.
31 *        The stubs for FP routines are in  place so only need to be filled in.
32 *
33 *  NOTE: RTEMS defines a canonical name for each cpu model.
34 */
35
36/*
37 *  Define the name of the CPU family.
38 */
39
40#define CPU_NAME "Intel i960"
41
42/*
43 *  This should work since most i960 models do not have FPUs. The logic is:
44 *
45 *    + If the user specifically asks for soft-float, give it to them
46 *      regardless of hardware availability.
47 *    + If the CPU has hardware FPU, then use it.
48 *    + Otherwise, we have to use soft float.
49 */
50
51#if defined(_SOFT_FLOAT)
52#define I960_HAS_FPU 0
53#elif defined(_i960_KB__) || defined(_i960_SB__) || defined(_i960_SB__) || \
54      defined(_i960_JF__) || defined(_i960_MC__) || defined(_i960_CC__)
55#define I960_HAS_FPU 1
56#else
57#define I960_HAS_FPU 0
58#endif
59
60/*
61 *  Some of the CPU models may have better performance with
62 *  alignment of 8 or 16 but we don't know what model we are
63 *  being compiled for based solely on the information provided
64 *  when multilibbing.
65 */
66
67#define I960_CPU_ALIGNMENT 4
68
69/*
70 *  This is not the perfect CPU model name but it is adequate and
71 *  reflects what we know from multilib.
72 */
73
74#if I960_HAS_FPU
75#define CPU_MODEL_NAME "i960 w/FPU"
76#else
77#define CPU_MODEL_NAME "i960 w/soft-float"
78#endif
79#ifndef ASM
80
81
82/*
83 *  Miscellaneous Support Routines
84 */
85
86#define i960_reload_ctl_group( group ) \
87 { register int _cmd = ((group)|0x400) ; \
88   asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
89 }
90
91#define i960_atomic_modify( mask, addr, prev ) \
92 { register unsigned int  _mask = (mask); \
93   register unsigned int *_addr = (unsigned int *)(addr); \
94   asm volatile( "atmod  %0,%1,%1" \
95                  : "=d" (_addr), "=d" (_mask) \
96                  : "0"  (_addr), "1"  (_mask) ); \
97   (prev) = _mask; \
98 }
99
100#define atomic_modify( _mask, _address, _previous ) \
101  i960_atomic_modify( _mask, _address, _previous )
102
103#define i960_enable_tracing() \
104 { register unsigned int _pc = 0x1; \
105   asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
106 }
107
108/*
109 *  Interrupt Level Routines
110 */
111
112#define i960_disable_interrupts( oldlevel ) \
113  { (oldlevel) = 0x1f0000; \
114    asm volatile ( "modpc   0,%1,%1" \
115                       : "=d" ((oldlevel)) \
116                       : "0"  ((oldlevel)) ); \
117  }
118
119#define i960_enable_interrupts( oldlevel ) \
120  { unsigned int _mask = 0x1f0000; \
121    asm volatile ( "modpc   0,%0,%1" \
122                       : "=d" (_mask), "=d" ((oldlevel)) \
123                       : "0"  (_mask), "1"  ((oldlevel)) ); \
124  }
125
126#define i960_flash_interrupts( oldlevel ) \
127  { unsigned int _mask = 0x1f0000; \
128    asm volatile ( "modpc   0,%0,%1 ; \
129                    mov     %0,%1 ; \
130                    modpc   0,%0,%1"  \
131                       : "=d" (_mask), "=d" ((oldlevel)) \
132                       : "0"  (_mask), "1"  ((oldlevel)) ); \
133  }
134
135#define i960_get_interrupt_level( _level ) \
136  { \
137    i960_disable_interrupts( _level ); \
138    i960_enable_interrupts( _level ); \
139    (_level) = ((_level) & 0x1f0000) >> 16; \
140  } while ( 0 )
141
142#define i960_cause_intr( intr ) \
143 { register int _intr = (intr); \
144   asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
145 }
146
147/*
148 *  Interrupt Masking Routines
149 */
150
151static inline unsigned int i960_get_fp()
152{ register unsigned int _fp=0;
153  asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
154  return ( _fp );
155}
156
157/*
158 *  The following routine swaps the endian format of an unsigned int.
159 *  It must be static because it is referenced indirectly.
160 *
161 *  This version is based on code presented in Vol. 4, No. 4 of
162 *  Insight 960.  It is certainly something you wouldn't think
163 *  of on your own.
164 */
165
166static inline unsigned int CPU_swap_u32(
167  unsigned int value
168)
169{
170  register unsigned int to_swap = value;
171  register unsigned int temp    = 0xFF00FF00;
172  register unsigned int swapped = 0;
173
174                                            /*  to_swap      swapped  */
175  asm volatile ( "rotate  16,%0,%2 ;"       /* 0x12345678  0x56781234 */
176                 "modify  %1,%0,%2 ;"       /* 0x12345678  0x12785634 */
177                 "rotate  8,%2,%2"          /* 0x12345678  0x78563412 */
178                 : "=r" (to_swap), "=r" (temp), "=r" (swapped)
179                 : "0" (to_swap), "1" (temp), "2" (swapped)
180               );
181  return( swapped );
182}
183
184#define CPU_swap_u16( value ) \
185  (((value&0xff) << 8) | ((value >> 8)&0xff))
186
187#ifdef __cplusplus
188}
189#endif
190
191#endif /* !ASM */
192
193#endif
194/* end of include file */
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