source: rtems/c/src/exec/score/cpu/i960/rtems/score/i960.h @ 702c5f5

4.104.114.84.9
Last change on this file since 702c5f5 was 702c5f5, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 27, 1999 at 3:29:18 PM

The rxgen960 BSP and i960 RPM support was submitted by Mark Bronson
<mark@…> of RAMIX.

  • Property mode set to 100644
File size: 17.4 KB
Line 
1/*  i960.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __i960_h
18#define __i960_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  This file contains the information required to build
26 *  RTEMS for a particular member of the Intel i960
27 *  family.  It does this by setting variables to indicate
28 *  which implementation dependent features are present
29 *  in a particular member of the family.
30 *
31 *  NOTE: For now i960 support is for models without an FPU.
32 *        The stubs for FP routines are in  place so only need to be filled in.
33 *
34 *  NOTE: RTEMS defines a canonical name for each cpu model.
35 */
36
37#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
38
39#define CPU_MODEL_NAME  "i960ca"
40#define __RTEMS_I960CA__
41
42#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
43
44#define CPU_MODEL_NAME  "i960ha"
45#define __RTEMS_I960HA__
46
47#elif defined(__i960RP__)
48
49#include <i960RP.h>
50#define CPU_MODEL_NAME  "i960rp"
51#define __RTEMS_I960RP__
52#define I960_CPU_ALIGNMENT 8
53#define I960_SOFT_RESET_COMMAND 0x300
54
55#else
56
57#error "Unsupported CPU Model"
58
59#endif
60
61/*
62 *  Now default some CPU model variation parameters
63 */
64
65#ifndef I960_HAS_FPU
66#define I960_HAS_FPU 0
67#endif
68
69#ifndef I960_CPU_ALIGNMENT
70#define I960_CPU_ALIGNMENT 4
71#endif
72
73#ifndef I960_SOFT_RESET_COMMAND
74#define I960_SOFT_RESET_COMMAND 0x30000
75#endif
76
77/*
78 *  Define the name of the CPU family.
79 */
80
81#define CPU_NAME "Intel i960"
82
83#ifndef ASM
84
85/*
86 * XXX    should have an ifdef here and have stuff for the other
87 * XXX    family members...
88 */
89 
90#if defined(__RTEMS_I960CA__)
91/*
92 *  Now default some CPU model variation parameters
93 */
94
95#ifndef I960_HAS_FPU
96#define I960_HAS_FPU 0
97#endif
98
99#ifndef I960_CPU_ALIGNMENT
100#define I960_CPU_ALIGNMENT 4
101#endif
102
103 
104/* i960CA control structures */
105 
106/* Intel i960CA Control Table */
107 
108typedef struct {
109                            /* Control Group 0 */
110  unsigned int ipb0;              /* IP breakpoint 0 */
111  unsigned int ipb1;              /* IP breakpoint 1 */
112  unsigned int dab0;              /* data address breakpoint 0 */
113  unsigned int dab1;              /* data address breakpoint 1 */
114                            /* Control Group 1 */
115  unsigned int imap0;             /* interrupt map 0 */
116  unsigned int imap1;             /* interrupt map 1 */
117  unsigned int imap2;             /* interrupt map 2 */
118  unsigned int icon;              /* interrupt control */
119                            /* Control Group 2 */
120  unsigned int mcon0;             /* memory region 0 configuration */
121  unsigned int mcon1;             /* memory region 1 configuration */
122  unsigned int mcon2;             /* memory region 2 configuration */
123  unsigned int mcon3;             /* memory region 3 configuration */
124                            /* Control Group 3 */
125  unsigned int mcon4;             /* memory region 4 configuration */
126  unsigned int mcon5;             /* memory region 5 configuration */
127  unsigned int mcon6;             /* memory region 6 configuration */
128  unsigned int mcon7;             /* memory region 7 configuration */
129                            /* Control Group 4 */
130  unsigned int mcon8;             /* memory region 8 configuration */
131  unsigned int mcon9;             /* memory region 9 configuration */
132  unsigned int mcon10;            /* memory region 10 configuration */
133  unsigned int mcon11;            /* memory region 11 configuration */
134                            /* Control Group 5 */
135  unsigned int mcon12;            /* memory region 12 configuration */
136  unsigned int mcon13;            /* memory region 13 configuration */
137  unsigned int mcon14;            /* memory region 14 configuration */
138  unsigned int mcon15;            /* memory region 15 configuration */
139                            /* Control Group 6 */
140  unsigned int reserved;          /* reserved */
141  unsigned int bpcon;             /* breakpoint control */
142  unsigned int tc;                /* trace control */
143  unsigned int bcon;              /* bus configuration control */
144}   i960ca_control_table;
145 
146/* Intel i960CA Processor Control Block */
147 
148typedef struct {
149  unsigned int    *fault_tbl;     /* fault table base address */
150  i960ca_control_table
151                  *control_tbl;   /* control table base address */
152  unsigned int     initial_ac;    /* AC register initial value */
153  unsigned int     fault_config;  /* fault configuration word */
154  void           **intr_tbl;      /* interrupt table base address */
155  void            *sys_proc_tbl;  /* system procedure table
156                                     base address */
157  unsigned int     reserved;      /* reserved */
158  unsigned int    *intr_stack;    /* interrupt stack pointer */
159  unsigned int     ins_cache_cfg; /* instruction cache
160                                     configuration word */
161  unsigned int     reg_cache_cfg; /* register cache configuration word */
162}   i960ca_PRCB;
163
164typedef i960ca_control_table i960_control_table;
165typedef i960ca_PRCB i960_PRCB;
166
167#elif defined(__RTEMS_I960HA__)
168
169/* i960HA control structures */
170
171/* Intel i960HA Control Table */
172
173typedef struct {
174                            /* Control Group 0 */
175  unsigned int ipb0;              /* IP breakpoint 0 */
176  unsigned int ipb1;              /* IP breakpoint 1 */
177  unsigned int dab0;              /* data address breakpoint 0 */
178  unsigned int dab1;              /* data address breakpoint 1 */
179                            /* Control Group 1 */
180  unsigned int imap0;             /* interrupt map 0 */
181  unsigned int imap1;             /* interrupt map 1 */
182  unsigned int imap2;             /* interrupt map 2 */
183  unsigned int icon;              /* interrupt control */
184                            /* Control Group 2 */
185  unsigned int mcon0;             /* memory region 0 configuration */
186  unsigned int mcon1;             /* memory region 1 configuration */
187  unsigned int mcon2;             /* memory region 2 configuration */
188  unsigned int mcon3;             /* memory region 3 configuration */
189                            /* Control Group 3 */
190  unsigned int mcon4;             /* memory region 4 configuration */
191  unsigned int mcon5;             /* memory region 5 configuration */
192  unsigned int mcon6;             /* memory region 6 configuration */
193  unsigned int mcon7;             /* memory region 7 configuration */
194                            /* Control Group 4 */
195  unsigned int mcon8;             /* memory region 8 configuration */
196  unsigned int mcon9;             /* memory region 9 configuration */
197  unsigned int mcon10;            /* memory region 10 configuration */
198  unsigned int mcon11;            /* memory region 11 configuration */
199                            /* Control Group 5 */
200  unsigned int mcon12;            /* memory region 12 configuration */
201  unsigned int mcon13;            /* memory region 13 configuration */
202  unsigned int mcon14;            /* memory region 14 configuration */
203  unsigned int mcon15;            /* memory region 15 configuration */
204                            /* Control Group 6 */
205  unsigned int reserved;          /* reserved */
206  unsigned int bpcon;             /* breakpoint control */
207  unsigned int tc;                /* trace control */
208  unsigned int bcon;              /* bus configuration control */
209}   i960ha_control_table;
210
211/* Intel i960HA Processor Control Block */
212
213typedef struct {
214  unsigned int    *fault_tbl;     /* fault table base address */
215  i960ha_control_table
216                  *control_tbl;   /* control table base address */
217  unsigned int     initial_ac;    /* AC register initial value */
218  unsigned int     fault_config;  /* fault configuration word */
219  void           **intr_tbl;      /* interrupt table base address */
220  void            *sys_proc_tbl;  /* system procedure table
221                                     base address */
222  unsigned int     reserved;      /* reserved */
223  unsigned int    *intr_stack;    /* interrupt stack pointer */
224  unsigned int     ins_cache_cfg; /* instruction cache
225                                     configuration word */
226  unsigned int     reg_cache_cfg; /* register cache configuration word */
227}   i960ha_PRCB;
228
229typedef i960ha_control_table i960_control_table;
230typedef i960ha_PRCB i960_PRCB;
231
232#elif defined(__RTEMS_I960RP__)
233
234/* i960RP control structures */
235
236/* Intel i960RP Control Table */
237
238typedef struct {
239                            /* Control Group 0 */
240  unsigned int rsvd00;
241  unsigned int rsvd01;
242  unsigned int rsvd02;
243  unsigned int rsvd03;
244                            /* Control Group 1 */
245  unsigned int imap0;             /* interrupt map 0 */
246  unsigned int imap1;             /* interrupt map 1 */
247  unsigned int imap2;             /* interrupt map 2 */
248  unsigned int icon;              /* interrupt control */
249                            /* Control Group 2 */
250  unsigned int pmcon0;            /* memory region 0 configuration */
251  unsigned int rsvd1;
252  unsigned int pmcon2;            /* memory region 2 configuration */
253  unsigned int rsvd2;
254                            /* Control Group 3 */
255  unsigned int pmcon4;            /* memory region 4 configuration */
256  unsigned int rsvd3;
257  unsigned int pmcon6;            /* memory region 6 configuration */
258  unsigned int rsvd4;
259                            /* Control Group 4 */
260  unsigned int pmcon8;            /* memory region 8 configuration */
261  unsigned int rsvd5;
262  unsigned int pmcon10;           /* memory region 10 configuration */
263  unsigned int rsvd6;
264                            /* Control Group 5 */
265  unsigned int pmcon12;           /* memory region 12 configuration */
266  unsigned int rsvd7;
267  unsigned int pmcon14;           /* memory region 14 configuration */
268  unsigned int rsvd8;
269                            /* Control Group 6 */
270  unsigned int rsvd9;
271  unsigned int rsvd10;
272  unsigned int tc;                /* trace control */
273  unsigned int bcon;              /* bus configuration control */
274}   i960rp_control_table;
275
276/* Intel i960RP Processor Control Block */
277
278typedef struct {
279  unsigned int    *fault_tbl;     /* fault table base address */
280  i960rp_control_table
281                  *control_tbl;   /* control table base address */
282  unsigned int     initial_ac;    /* AC register initial value */
283  unsigned int     fault_config;  /* fault configuration word */
284  void           **intr_tbl;      /* interrupt table base address */
285  void            *sys_proc_tbl;  /* system procedure table
286                                     base address */
287  unsigned int     reserved;      /* reserved */
288  unsigned int    *intr_stack;    /* interrupt stack pointer */
289  unsigned int     ins_cache_cfg; /* instruction cache
290                                     configuration word */
291  unsigned int     reg_cache_cfg; /* register cache configuration word */
292}   i960rp_PRCB;
293
294typedef i960rp_control_table i960_control_table;
295typedef i960rp_PRCB i960_PRCB;
296
297#else
298#error "invalid processor selection!"
299#endif
300
301/*
302 *  Miscellaneous Support Routines
303 */
304
305#define i960_reload_ctl_group( group ) \
306 { register int _cmd = ((group)|0x400) ; \
307   asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
308 }
309
310#define i960_atomic_modify( mask, addr, prev ) \
311 { register unsigned int  _mask = (mask); \
312   register unsigned int *_addr = (unsigned int *)(addr); \
313   asm volatile( "atmod  %0,%1,%1" \
314                  : "=d" (_addr), "=d" (_mask) \
315                  : "0"  (_addr), "1"  (_mask) ); \
316   (prev) = _mask; \
317 }
318
319#define atomic_modify( _mask, _address, _previous ) \
320  i960_atomic_modify( _mask, _address, _previous )
321
322#define i960_enable_tracing() \
323 { register unsigned int _pc = 0x1; \
324   asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
325 }
326
327/*
328 *  Interrupt Level Routines
329 */
330
331#define i960_disable_interrupts( oldlevel ) \
332  { (oldlevel) = 0x1f0000; \
333    asm volatile ( "modpc   0,%1,%1" \
334                       : "=d" ((oldlevel)) \
335                       : "0"  ((oldlevel)) ); \
336  }
337
338#define i960_enable_interrupts( oldlevel ) \
339  { unsigned int _mask = 0x1f0000; \
340    asm volatile ( "modpc   0,%0,%1" \
341                       : "=d" (_mask), "=d" ((oldlevel)) \
342                       : "0"  (_mask), "1"  ((oldlevel)) ); \
343  }
344
345#define i960_flash_interrupts( oldlevel ) \
346  { unsigned int _mask = 0x1f0000; \
347    asm volatile ( "modpc   0,%0,%1 ; \
348                    mov     %0,%1 ; \
349                    modpc   0,%0,%1"  \
350                       : "=d" (_mask), "=d" ((oldlevel)) \
351                       : "0"  (_mask), "1"  ((oldlevel)) ); \
352  }
353
354#define i960_get_interrupt_level( _level ) \
355  { \
356    i960_disable_interrupts( _level ); \
357    i960_enable_interrupts( _level ); \
358    (_level) = ((_level) & 0x1f0000) >> 16; \
359  } while ( 0 )
360
361#define i960_cause_intr( intr ) \
362 { register int _intr = (intr); \
363   asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
364 }
365
366/*
367 *  Interrupt Masking Routines
368 */
369
370#if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__)
371
372#define i960_unmask_intr( xint ) \
373 { register unsigned int _mask= (1<<(xint)); \
374   asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
375 }
376
377#define i960_mask_intr( xint ) \
378 { register unsigned int _mask= (1<<(xint)); \
379   asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
380 }
381
382#define i960_clear_intr( xint ) \
383 { register unsigned int _xint=(xint); \
384asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
385                  bbs    %0,sf0, loop_til_cleared" \
386                  : "=d" (_xint) : "0" (_xint) ); \
387 }
388
389static inline unsigned int i960_pend_intrs()
390{ register unsigned int _intr=0;
391  asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
392  return ( _intr );
393}
394
395static inline unsigned int i960_mask_intrs()
396{ register unsigned int _intr=0;
397  asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
398  return( _intr );
399}
400
401#elif defined(__RTEMS_I960RP__)
402
403#define i960_unmask_intr( xint ) \
404 { register unsigned int _mask= (1<<(xint)); \
405   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
406   register unsigned int _val= *_imsk; \
407   asm volatile( "or %0,%2,%0; \
408                  st %0,(%1)" \
409                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
410                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
411 }
412
413#define i960_mask_intr( xint ) \
414 { register unsigned int _mask= (1<<(xint)); \
415   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
416   register unsigned int _val = *_imsk; \
417   asm volatile( "andnot %2,%0,%0; \
418                  st %0,(%1)" \
419                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
420                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
421 }
422#define i960_clear_intr( xint ) \
423 { register unsigned int _xint=xint; \
424   register unsigned int _mask=(1<<(xint)); \
425   register unsigned int *_ipnd = (int * ) IPND_ADDR; \
426   register unsigned int          _rslt = 0; \
427asm volatile( "loop_til_cleared: mov 0, %0; \
428                  atmod %1, %2, %0; \
429                  bbs    %3,%0, loop_til_cleared" \
430                  : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
431                  : "0"  (_rslt), "1"  (_ipnd), "2"  (_mask), "3"  (_xint) ); \
432 }
433
434static inline unsigned int i960_pend_intrs()
435{ register unsigned int _intr= *(unsigned int *) IPND_ADDR;
436  /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
437   asm volatile( "mov (%0),%1" \
438                    : "=d" (_ipnd), "=d" (_mask) \
439                    : "0" (_ipnd), "1" (_mask) ); \ */
440  return ( _intr );
441}
442
443static inline unsigned int i960_mask_intrs()
444{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
445  /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
446  return( _intr );
447}
448#endif
449
450static inline unsigned int i960_get_fp()
451{ register unsigned int _fp=0;
452  asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
453  return ( _fp );
454}
455
456/*
457 *  Soft Reset
458 */
459
460#if defined(I960_SOFT_RESET_COMMAND)
461
462#define i960_soft_reset( prcb ) \
463 { register i960_PRCB    *_prcb = (prcb); \
464   register unsigned int *_next=0; \
465   register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
466   asm volatile( "lda    next,%1; \
467                  sysctl %0,%1,%2; \
468            next: mov    g0,g0" \
469                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
470                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
471 }
472
473#else
474#warning "I960_SOFT_RESET_COMMAND is not defined"
475#endif
476
477/*
478 *  The following routine swaps the endian format of an unsigned int.
479 *  It must be static because it is referenced indirectly.
480 *
481 *  This version is based on code presented in Vol. 4, No. 4 of
482 *  Insight 960.  It is certainly something you wouldn't think
483 *  of on your own.
484 */
485
486static inline unsigned int CPU_swap_u32(
487  unsigned int value
488)
489{
490  register unsigned int to_swap = value;
491  register unsigned int temp    = 0xFF00FF00;
492  register unsigned int swapped = 0;
493
494                                            /*  to_swap      swapped  */
495  asm volatile ( "rotate  16,%0,%2 ;"       /* 0x12345678  0x56781234 */
496                 "modify  %1,%0,%2 ;"       /* 0x12345678  0x12785634 */
497                 "rotate  8,%2,%2"          /* 0x12345678  0x78563412 */
498                 : "=r" (to_swap), "=r" (temp), "=r" (swapped)
499                 : "0" (to_swap), "1" (temp), "2" (swapped)
500               );
501  return( swapped );
502}
503
504#define CPU_swap_u16( value ) \
505  (((value&0xff) << 8) | ((value >> 8)&0xff))
506
507#ifdef __cplusplus
508}
509#endif
510
511#endif /* !ASM */
512
513#endif
514/* end of include file */
Note: See TracBrowser for help on using the repository browser.