source: rtems/c/src/exec/score/cpu/i960/rtems/score/i960.h @ 63cf252f

Last change on this file since 63cf252f was 08311cc3, checked in by Joel Sherrill <joel.sherrill@…>, on 11/17/99 at 17:51:34

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1/*  i960.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __i960_h
17#define __i960_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/*
24 *  This file contains the information required to build
25 *  RTEMS for a particular member of the Intel i960
26 *  family.  It does this by setting variables to indicate
27 *  which implementation dependent features are present
28 *  in a particular member of the family.
29 *
30 *  NOTE: For now i960 support is for models without an FPU.
31 *        The stubs for FP routines are in  place so only need to be filled in.
32 *
33 *  NOTE: RTEMS defines a canonical name for each cpu model.
34 */
35
36#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
37
38#define CPU_MODEL_NAME  "i960ca"
39#define __RTEMS_I960CA__
40
41#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
42
43#define CPU_MODEL_NAME  "i960ha"
44#define __RTEMS_I960HA__
45
46#elif defined(__i960RP__)
47
48#include <i960RP.h>
49#define CPU_MODEL_NAME  "i960rp"
50#define __RTEMS_I960RP__
51#define I960_CPU_ALIGNMENT 8
52#define I960_SOFT_RESET_COMMAND 0x300
53
54#else
55
56#error "Unsupported CPU Model"
57
58#endif
59
60/*
61 *  Now default some CPU model variation parameters
62 */
63
64#ifndef I960_HAS_FPU
65#define I960_HAS_FPU 0
66#endif
67
68#ifndef I960_CPU_ALIGNMENT
69#define I960_CPU_ALIGNMENT 4
70#endif
71
72#ifndef I960_SOFT_RESET_COMMAND
73#define I960_SOFT_RESET_COMMAND 0x30000
74#endif
75
76/*
77 *  Define the name of the CPU family.
78 */
79
80#define CPU_NAME "Intel i960"
81
82#ifndef ASM
83
84/*
85 * XXX    should have an ifdef here and have stuff for the other
86 * XXX    family members...
87 */
88 
89#if defined(__RTEMS_I960CA__)
90/*
91 *  Now default some CPU model variation parameters
92 */
93
94#ifndef I960_HAS_FPU
95#define I960_HAS_FPU 0
96#endif
97
98#ifndef I960_CPU_ALIGNMENT
99#define I960_CPU_ALIGNMENT 4
100#endif
101
102 
103/* i960CA control structures */
104 
105/* Intel i960CA Control Table */
106 
107typedef struct {
108                            /* Control Group 0 */
109  unsigned int ipb0;              /* IP breakpoint 0 */
110  unsigned int ipb1;              /* IP breakpoint 1 */
111  unsigned int dab0;              /* data address breakpoint 0 */
112  unsigned int dab1;              /* data address breakpoint 1 */
113                            /* Control Group 1 */
114  unsigned int imap0;             /* interrupt map 0 */
115  unsigned int imap1;             /* interrupt map 1 */
116  unsigned int imap2;             /* interrupt map 2 */
117  unsigned int icon;              /* interrupt control */
118                            /* Control Group 2 */
119  unsigned int mcon0;             /* memory region 0 configuration */
120  unsigned int mcon1;             /* memory region 1 configuration */
121  unsigned int mcon2;             /* memory region 2 configuration */
122  unsigned int mcon3;             /* memory region 3 configuration */
123                            /* Control Group 3 */
124  unsigned int mcon4;             /* memory region 4 configuration */
125  unsigned int mcon5;             /* memory region 5 configuration */
126  unsigned int mcon6;             /* memory region 6 configuration */
127  unsigned int mcon7;             /* memory region 7 configuration */
128                            /* Control Group 4 */
129  unsigned int mcon8;             /* memory region 8 configuration */
130  unsigned int mcon9;             /* memory region 9 configuration */
131  unsigned int mcon10;            /* memory region 10 configuration */
132  unsigned int mcon11;            /* memory region 11 configuration */
133                            /* Control Group 5 */
134  unsigned int mcon12;            /* memory region 12 configuration */
135  unsigned int mcon13;            /* memory region 13 configuration */
136  unsigned int mcon14;            /* memory region 14 configuration */
137  unsigned int mcon15;            /* memory region 15 configuration */
138                            /* Control Group 6 */
139  unsigned int reserved;          /* reserved */
140  unsigned int bpcon;             /* breakpoint control */
141  unsigned int tc;                /* trace control */
142  unsigned int bcon;              /* bus configuration control */
143}   i960ca_control_table;
144 
145/* Intel i960CA Processor Control Block */
146 
147typedef struct {
148  unsigned int    *fault_tbl;     /* fault table base address */
149  i960ca_control_table
150                  *control_tbl;   /* control table base address */
151  unsigned int     initial_ac;    /* AC register initial value */
152  unsigned int     fault_config;  /* fault configuration word */
153  void           **intr_tbl;      /* interrupt table base address */
154  void            *sys_proc_tbl;  /* system procedure table
155                                     base address */
156  unsigned int     reserved;      /* reserved */
157  unsigned int    *intr_stack;    /* interrupt stack pointer */
158  unsigned int     ins_cache_cfg; /* instruction cache
159                                     configuration word */
160  unsigned int     reg_cache_cfg; /* register cache configuration word */
161}   i960ca_PRCB;
162
163typedef i960ca_control_table i960_control_table;
164typedef i960ca_PRCB i960_PRCB;
165
166#elif defined(__RTEMS_I960HA__)
167
168/* i960HA control structures */
169
170/* Intel i960HA Control Table */
171
172typedef struct {
173                            /* Control Group 0 */
174  unsigned int ipb0;              /* IP breakpoint 0 */
175  unsigned int ipb1;              /* IP breakpoint 1 */
176  unsigned int dab0;              /* data address breakpoint 0 */
177  unsigned int dab1;              /* data address breakpoint 1 */
178                            /* Control Group 1 */
179  unsigned int imap0;             /* interrupt map 0 */
180  unsigned int imap1;             /* interrupt map 1 */
181  unsigned int imap2;             /* interrupt map 2 */
182  unsigned int icon;              /* interrupt control */
183                            /* Control Group 2 */
184  unsigned int mcon0;             /* memory region 0 configuration */
185  unsigned int mcon1;             /* memory region 1 configuration */
186  unsigned int mcon2;             /* memory region 2 configuration */
187  unsigned int mcon3;             /* memory region 3 configuration */
188                            /* Control Group 3 */
189  unsigned int mcon4;             /* memory region 4 configuration */
190  unsigned int mcon5;             /* memory region 5 configuration */
191  unsigned int mcon6;             /* memory region 6 configuration */
192  unsigned int mcon7;             /* memory region 7 configuration */
193                            /* Control Group 4 */
194  unsigned int mcon8;             /* memory region 8 configuration */
195  unsigned int mcon9;             /* memory region 9 configuration */
196  unsigned int mcon10;            /* memory region 10 configuration */
197  unsigned int mcon11;            /* memory region 11 configuration */
198                            /* Control Group 5 */
199  unsigned int mcon12;            /* memory region 12 configuration */
200  unsigned int mcon13;            /* memory region 13 configuration */
201  unsigned int mcon14;            /* memory region 14 configuration */
202  unsigned int mcon15;            /* memory region 15 configuration */
203                            /* Control Group 6 */
204  unsigned int reserved;          /* reserved */
205  unsigned int bpcon;             /* breakpoint control */
206  unsigned int tc;                /* trace control */
207  unsigned int bcon;              /* bus configuration control */
208}   i960ha_control_table;
209
210/* Intel i960HA Processor Control Block */
211
212typedef struct {
213  unsigned int    *fault_tbl;     /* fault table base address */
214  i960ha_control_table
215                  *control_tbl;   /* control table base address */
216  unsigned int     initial_ac;    /* AC register initial value */
217  unsigned int     fault_config;  /* fault configuration word */
218  void           **intr_tbl;      /* interrupt table base address */
219  void            *sys_proc_tbl;  /* system procedure table
220                                     base address */
221  unsigned int     reserved;      /* reserved */
222  unsigned int    *intr_stack;    /* interrupt stack pointer */
223  unsigned int     ins_cache_cfg; /* instruction cache
224                                     configuration word */
225  unsigned int     reg_cache_cfg; /* register cache configuration word */
226}   i960ha_PRCB;
227
228typedef i960ha_control_table i960_control_table;
229typedef i960ha_PRCB i960_PRCB;
230
231#elif defined(__RTEMS_I960RP__)
232
233/* i960RP control structures */
234
235/* Intel i960RP Control Table */
236
237typedef struct {
238                            /* Control Group 0 */
239  unsigned int rsvd00;
240  unsigned int rsvd01;
241  unsigned int rsvd02;
242  unsigned int rsvd03;
243                            /* Control Group 1 */
244  unsigned int imap0;             /* interrupt map 0 */
245  unsigned int imap1;             /* interrupt map 1 */
246  unsigned int imap2;             /* interrupt map 2 */
247  unsigned int icon;              /* interrupt control */
248                            /* Control Group 2 */
249  unsigned int pmcon0;            /* memory region 0 configuration */
250  unsigned int rsvd1;
251  unsigned int pmcon2;            /* memory region 2 configuration */
252  unsigned int rsvd2;
253                            /* Control Group 3 */
254  unsigned int pmcon4;            /* memory region 4 configuration */
255  unsigned int rsvd3;
256  unsigned int pmcon6;            /* memory region 6 configuration */
257  unsigned int rsvd4;
258                            /* Control Group 4 */
259  unsigned int pmcon8;            /* memory region 8 configuration */
260  unsigned int rsvd5;
261  unsigned int pmcon10;           /* memory region 10 configuration */
262  unsigned int rsvd6;
263                            /* Control Group 5 */
264  unsigned int pmcon12;           /* memory region 12 configuration */
265  unsigned int rsvd7;
266  unsigned int pmcon14;           /* memory region 14 configuration */
267  unsigned int rsvd8;
268                            /* Control Group 6 */
269  unsigned int rsvd9;
270  unsigned int rsvd10;
271  unsigned int tc;                /* trace control */
272  unsigned int bcon;              /* bus configuration control */
273}   i960rp_control_table;
274
275/* Intel i960RP Processor Control Block */
276
277typedef struct {
278  unsigned int    *fault_tbl;     /* fault table base address */
279  i960rp_control_table
280                  *control_tbl;   /* control table base address */
281  unsigned int     initial_ac;    /* AC register initial value */
282  unsigned int     fault_config;  /* fault configuration word */
283  void           **intr_tbl;      /* interrupt table base address */
284  void            *sys_proc_tbl;  /* system procedure table
285                                     base address */
286  unsigned int     reserved;      /* reserved */
287  unsigned int    *intr_stack;    /* interrupt stack pointer */
288  unsigned int     ins_cache_cfg; /* instruction cache
289                                     configuration word */
290  unsigned int     reg_cache_cfg; /* register cache configuration word */
291}   i960rp_PRCB;
292
293typedef i960rp_control_table i960_control_table;
294typedef i960rp_PRCB i960_PRCB;
295
296#else
297#error "invalid processor selection!"
298#endif
299
300/*
301 *  Miscellaneous Support Routines
302 */
303
304#define i960_reload_ctl_group( group ) \
305 { register int _cmd = ((group)|0x400) ; \
306   asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
307 }
308
309#define i960_atomic_modify( mask, addr, prev ) \
310 { register unsigned int  _mask = (mask); \
311   register unsigned int *_addr = (unsigned int *)(addr); \
312   asm volatile( "atmod  %0,%1,%1" \
313                  : "=d" (_addr), "=d" (_mask) \
314                  : "0"  (_addr), "1"  (_mask) ); \
315   (prev) = _mask; \
316 }
317
318#define atomic_modify( _mask, _address, _previous ) \
319  i960_atomic_modify( _mask, _address, _previous )
320
321#define i960_enable_tracing() \
322 { register unsigned int _pc = 0x1; \
323   asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
324 }
325
326/*
327 *  Interrupt Level Routines
328 */
329
330#define i960_disable_interrupts( oldlevel ) \
331  { (oldlevel) = 0x1f0000; \
332    asm volatile ( "modpc   0,%1,%1" \
333                       : "=d" ((oldlevel)) \
334                       : "0"  ((oldlevel)) ); \
335  }
336
337#define i960_enable_interrupts( oldlevel ) \
338  { unsigned int _mask = 0x1f0000; \
339    asm volatile ( "modpc   0,%0,%1" \
340                       : "=d" (_mask), "=d" ((oldlevel)) \
341                       : "0"  (_mask), "1"  ((oldlevel)) ); \
342  }
343
344#define i960_flash_interrupts( oldlevel ) \
345  { unsigned int _mask = 0x1f0000; \
346    asm volatile ( "modpc   0,%0,%1 ; \
347                    mov     %0,%1 ; \
348                    modpc   0,%0,%1"  \
349                       : "=d" (_mask), "=d" ((oldlevel)) \
350                       : "0"  (_mask), "1"  ((oldlevel)) ); \
351  }
352
353#define i960_get_interrupt_level( _level ) \
354  { \
355    i960_disable_interrupts( _level ); \
356    i960_enable_interrupts( _level ); \
357    (_level) = ((_level) & 0x1f0000) >> 16; \
358  } while ( 0 )
359
360#define i960_cause_intr( intr ) \
361 { register int _intr = (intr); \
362   asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
363 }
364
365/*
366 *  Interrupt Masking Routines
367 */
368
369#if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__)
370
371#define i960_unmask_intr( xint ) \
372 { register unsigned int _mask= (1<<(xint)); \
373   asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
374 }
375
376#define i960_mask_intr( xint ) \
377 { register unsigned int _mask= (1<<(xint)); \
378   asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
379 }
380
381#define i960_clear_intr( xint ) \
382 { register unsigned int _xint=(xint); \
383asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
384                  bbs    %0,sf0, loop_til_cleared" \
385                  : "=d" (_xint) : "0" (_xint) ); \
386 }
387
388static inline unsigned int i960_pend_intrs()
389{ register unsigned int _intr=0;
390  asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
391  return ( _intr );
392}
393
394static inline unsigned int i960_mask_intrs()
395{ register unsigned int _intr=0;
396  asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
397  return( _intr );
398}
399
400#elif defined(__RTEMS_I960RP__)
401
402#define i960_unmask_intr( xint ) \
403 { register unsigned int _mask= (1<<(xint)); \
404   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
405   register unsigned int _val= *_imsk; \
406   asm volatile( "or %0,%2,%0; \
407                  st %0,(%1)" \
408                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
409                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
410 }
411
412#define i960_mask_intr( xint ) \
413 { register unsigned int _mask= (1<<(xint)); \
414   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
415   register unsigned int _val = *_imsk; \
416   asm volatile( "andnot %2,%0,%0; \
417                  st %0,(%1)" \
418                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
419                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
420 }
421#define i960_clear_intr( xint ) \
422 { register unsigned int _xint=xint; \
423   register unsigned int _mask=(1<<(xint)); \
424   register unsigned int *_ipnd = (int * ) IPND_ADDR; \
425   register unsigned int          _rslt = 0; \
426asm volatile( "loop_til_cleared: mov 0, %0; \
427                  atmod %1, %2, %0; \
428                  bbs    %3,%0, loop_til_cleared" \
429                  : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
430                  : "0"  (_rslt), "1"  (_ipnd), "2"  (_mask), "3"  (_xint) ); \
431 }
432
433static inline unsigned int i960_pend_intrs()
434{ register unsigned int _intr= *(unsigned int *) IPND_ADDR;
435  /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
436   asm volatile( "mov (%0),%1" \
437                    : "=d" (_ipnd), "=d" (_mask) \
438                    : "0" (_ipnd), "1" (_mask) ); \ */
439  return ( _intr );
440}
441
442static inline unsigned int i960_mask_intrs()
443{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
444  /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
445  return( _intr );
446}
447#endif
448
449static inline unsigned int i960_get_fp()
450{ register unsigned int _fp=0;
451  asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
452  return ( _fp );
453}
454
455/*
456 *  Soft Reset
457 */
458
459#if defined(I960_SOFT_RESET_COMMAND)
460
461#define i960_soft_reset( prcb ) \
462 { register i960_PRCB    *_prcb = (prcb); \
463   register unsigned int *_next=0; \
464   register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
465   asm volatile( "lda    next,%1; \
466                  sysctl %0,%1,%2; \
467            next: mov    g0,g0" \
468                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
469                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
470 }
471
472#else
473#warning "I960_SOFT_RESET_COMMAND is not defined"
474#endif
475
476/*
477 *  The following routine swaps the endian format of an unsigned int.
478 *  It must be static because it is referenced indirectly.
479 *
480 *  This version is based on code presented in Vol. 4, No. 4 of
481 *  Insight 960.  It is certainly something you wouldn't think
482 *  of on your own.
483 */
484
485static inline unsigned int CPU_swap_u32(
486  unsigned int value
487)
488{
489  register unsigned int to_swap = value;
490  register unsigned int temp    = 0xFF00FF00;
491  register unsigned int swapped = 0;
492
493                                            /*  to_swap      swapped  */
494  asm volatile ( "rotate  16,%0,%2 ;"       /* 0x12345678  0x56781234 */
495                 "modify  %1,%0,%2 ;"       /* 0x12345678  0x12785634 */
496                 "rotate  8,%2,%2"          /* 0x12345678  0x78563412 */
497                 : "=r" (to_swap), "=r" (temp), "=r" (swapped)
498                 : "0" (to_swap), "1" (temp), "2" (swapped)
499               );
500  return( swapped );
501}
502
503#define CPU_swap_u16( value ) \
504  (((value&0xff) << 8) | ((value >> 8)&0xff))
505
506#ifdef __cplusplus
507}
508#endif
509
510#endif /* !ASM */
511
512#endif
513/* end of include file */
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