source: rtems/c/src/exec/score/cpu/i960/rtems/score/i960.h @ 19c6e495

Last change on this file since 19c6e495 was a3f5b6b, checked in by Joel Sherrill <joel.sherrill@…>, on 05/28/00 at 20:14:45

Added a special CPU model of "rtems_multilib". This is the beginnings
of an experiment to determine what it will take to multilib most of
RTEMS per GNU multilib conventions. It is thought that only
interrupt processing and IO are not multlib-able. This means that
a BSP Kit should include IRQ processing from score/cpu, all peripheral
support (header files from score/cpu, libchip, and libcpu), and the
BSPs themselves. The rest of RTEMS should be multlib-able. But to do
this, all RTEMS CPU model feature flags must be derivable from gcc
cpp predefines. By configuring the bare bsp with the rtems_multilib
CPU model, you can try any combination of CPU CFLAGS and see well how the
logic in that section of the <CPU>.h works. Once all CPU multilib
variations can be built, then RTEMS proper can be multilib'ed and
separated from the BSPs.
  • Property mode set to 100644
File size: 17.6 KB
Line 
1/*  i960.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __i960_h
17#define __i960_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/*
24 *  This file contains the information required to build
25 *  RTEMS for a particular member of the Intel i960
26 *  family.  It does this by setting variables to indicate
27 *  which implementation dependent features are present
28 *  in a particular member of the family.
29 *
30 *  NOTE: For now i960 support is for models without an FPU.
31 *        The stubs for FP routines are in  place so only need to be filled in.
32 *
33 *  NOTE: RTEMS defines a canonical name for each cpu model.
34 */
35
36#if defined(rtems_multilib)
37/*
38 *  Figure out all CPU Model Feature Flags based upon compiler
39 *  predefines.
40 */
41
42#define CPU_MODEL_NAME  "rtems_multilib"
43#define I960_HAS_FPU 0
44#define I960_CPU_ALIGNMENT 4
45#define I960_SOFT_RESET_COMMAND 0x30000
46
47#elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
48
49#define CPU_MODEL_NAME  "i960ca"
50#define __RTEMS_I960CA__
51
52#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
53
54#define CPU_MODEL_NAME  "i960ha"
55#define __RTEMS_I960HA__
56
57#elif defined(__i960RP__)
58
59#include <i960RP.h>
60#define CPU_MODEL_NAME  "i960rp"
61#define __RTEMS_I960RP__
62#define I960_CPU_ALIGNMENT 8
63#define I960_SOFT_RESET_COMMAND 0x300
64
65#else
66
67#error "Unsupported CPU Model"
68
69#endif
70
71/*
72 *  Now default some CPU model variation parameters
73 */
74
75#ifndef I960_HAS_FPU
76#define I960_HAS_FPU 0
77#endif
78
79#ifndef I960_CPU_ALIGNMENT
80#define I960_CPU_ALIGNMENT 4
81#endif
82
83#ifndef I960_SOFT_RESET_COMMAND
84#define I960_SOFT_RESET_COMMAND 0x30000
85#endif
86
87/*
88 *  Define the name of the CPU family.
89 */
90
91#define CPU_NAME "Intel i960"
92
93#ifndef ASM
94
95/*
96 * XXX    should have an ifdef here and have stuff for the other
97 * XXX    family members...
98 */
99 
100#if defined(__RTEMS_I960CA__)
101/*
102 *  Now default some CPU model variation parameters
103 */
104
105#ifndef I960_HAS_FPU
106#define I960_HAS_FPU 0
107#endif
108
109#ifndef I960_CPU_ALIGNMENT
110#define I960_CPU_ALIGNMENT 4
111#endif
112
113 
114/* i960CA control structures */
115 
116/* Intel i960CA Control Table */
117 
118typedef struct {
119                            /* Control Group 0 */
120  unsigned int ipb0;              /* IP breakpoint 0 */
121  unsigned int ipb1;              /* IP breakpoint 1 */
122  unsigned int dab0;              /* data address breakpoint 0 */
123  unsigned int dab1;              /* data address breakpoint 1 */
124                            /* Control Group 1 */
125  unsigned int imap0;             /* interrupt map 0 */
126  unsigned int imap1;             /* interrupt map 1 */
127  unsigned int imap2;             /* interrupt map 2 */
128  unsigned int icon;              /* interrupt control */
129                            /* Control Group 2 */
130  unsigned int mcon0;             /* memory region 0 configuration */
131  unsigned int mcon1;             /* memory region 1 configuration */
132  unsigned int mcon2;             /* memory region 2 configuration */
133  unsigned int mcon3;             /* memory region 3 configuration */
134                            /* Control Group 3 */
135  unsigned int mcon4;             /* memory region 4 configuration */
136  unsigned int mcon5;             /* memory region 5 configuration */
137  unsigned int mcon6;             /* memory region 6 configuration */
138  unsigned int mcon7;             /* memory region 7 configuration */
139                            /* Control Group 4 */
140  unsigned int mcon8;             /* memory region 8 configuration */
141  unsigned int mcon9;             /* memory region 9 configuration */
142  unsigned int mcon10;            /* memory region 10 configuration */
143  unsigned int mcon11;            /* memory region 11 configuration */
144                            /* Control Group 5 */
145  unsigned int mcon12;            /* memory region 12 configuration */
146  unsigned int mcon13;            /* memory region 13 configuration */
147  unsigned int mcon14;            /* memory region 14 configuration */
148  unsigned int mcon15;            /* memory region 15 configuration */
149                            /* Control Group 6 */
150  unsigned int reserved;          /* reserved */
151  unsigned int bpcon;             /* breakpoint control */
152  unsigned int tc;                /* trace control */
153  unsigned int bcon;              /* bus configuration control */
154}   i960ca_control_table;
155 
156/* Intel i960CA Processor Control Block */
157 
158typedef struct {
159  unsigned int    *fault_tbl;     /* fault table base address */
160  i960ca_control_table
161                  *control_tbl;   /* control table base address */
162  unsigned int     initial_ac;    /* AC register initial value */
163  unsigned int     fault_config;  /* fault configuration word */
164  void           **intr_tbl;      /* interrupt table base address */
165  void            *sys_proc_tbl;  /* system procedure table
166                                     base address */
167  unsigned int     reserved;      /* reserved */
168  unsigned int    *intr_stack;    /* interrupt stack pointer */
169  unsigned int     ins_cache_cfg; /* instruction cache
170                                     configuration word */
171  unsigned int     reg_cache_cfg; /* register cache configuration word */
172}   i960ca_PRCB;
173
174typedef i960ca_control_table i960_control_table;
175typedef i960ca_PRCB i960_PRCB;
176
177#elif defined(__RTEMS_I960HA__)
178
179/* i960HA control structures */
180
181/* Intel i960HA Control Table */
182
183typedef struct {
184                            /* Control Group 0 */
185  unsigned int ipb0;              /* IP breakpoint 0 */
186  unsigned int ipb1;              /* IP breakpoint 1 */
187  unsigned int dab0;              /* data address breakpoint 0 */
188  unsigned int dab1;              /* data address breakpoint 1 */
189                            /* Control Group 1 */
190  unsigned int imap0;             /* interrupt map 0 */
191  unsigned int imap1;             /* interrupt map 1 */
192  unsigned int imap2;             /* interrupt map 2 */
193  unsigned int icon;              /* interrupt control */
194                            /* Control Group 2 */
195  unsigned int mcon0;             /* memory region 0 configuration */
196  unsigned int mcon1;             /* memory region 1 configuration */
197  unsigned int mcon2;             /* memory region 2 configuration */
198  unsigned int mcon3;             /* memory region 3 configuration */
199                            /* Control Group 3 */
200  unsigned int mcon4;             /* memory region 4 configuration */
201  unsigned int mcon5;             /* memory region 5 configuration */
202  unsigned int mcon6;             /* memory region 6 configuration */
203  unsigned int mcon7;             /* memory region 7 configuration */
204                            /* Control Group 4 */
205  unsigned int mcon8;             /* memory region 8 configuration */
206  unsigned int mcon9;             /* memory region 9 configuration */
207  unsigned int mcon10;            /* memory region 10 configuration */
208  unsigned int mcon11;            /* memory region 11 configuration */
209                            /* Control Group 5 */
210  unsigned int mcon12;            /* memory region 12 configuration */
211  unsigned int mcon13;            /* memory region 13 configuration */
212  unsigned int mcon14;            /* memory region 14 configuration */
213  unsigned int mcon15;            /* memory region 15 configuration */
214                            /* Control Group 6 */
215  unsigned int reserved;          /* reserved */
216  unsigned int bpcon;             /* breakpoint control */
217  unsigned int tc;                /* trace control */
218  unsigned int bcon;              /* bus configuration control */
219}   i960ha_control_table;
220
221/* Intel i960HA Processor Control Block */
222
223typedef struct {
224  unsigned int    *fault_tbl;     /* fault table base address */
225  i960ha_control_table
226                  *control_tbl;   /* control table base address */
227  unsigned int     initial_ac;    /* AC register initial value */
228  unsigned int     fault_config;  /* fault configuration word */
229  void           **intr_tbl;      /* interrupt table base address */
230  void            *sys_proc_tbl;  /* system procedure table
231                                     base address */
232  unsigned int     reserved;      /* reserved */
233  unsigned int    *intr_stack;    /* interrupt stack pointer */
234  unsigned int     ins_cache_cfg; /* instruction cache
235                                     configuration word */
236  unsigned int     reg_cache_cfg; /* register cache configuration word */
237}   i960ha_PRCB;
238
239typedef i960ha_control_table i960_control_table;
240typedef i960ha_PRCB i960_PRCB;
241
242#elif defined(__RTEMS_I960RP__)
243
244/* i960RP control structures */
245
246/* Intel i960RP Control Table */
247
248typedef struct {
249                            /* Control Group 0 */
250  unsigned int rsvd00;
251  unsigned int rsvd01;
252  unsigned int rsvd02;
253  unsigned int rsvd03;
254                            /* Control Group 1 */
255  unsigned int imap0;             /* interrupt map 0 */
256  unsigned int imap1;             /* interrupt map 1 */
257  unsigned int imap2;             /* interrupt map 2 */
258  unsigned int icon;              /* interrupt control */
259                            /* Control Group 2 */
260  unsigned int pmcon0;            /* memory region 0 configuration */
261  unsigned int rsvd1;
262  unsigned int pmcon2;            /* memory region 2 configuration */
263  unsigned int rsvd2;
264                            /* Control Group 3 */
265  unsigned int pmcon4;            /* memory region 4 configuration */
266  unsigned int rsvd3;
267  unsigned int pmcon6;            /* memory region 6 configuration */
268  unsigned int rsvd4;
269                            /* Control Group 4 */
270  unsigned int pmcon8;            /* memory region 8 configuration */
271  unsigned int rsvd5;
272  unsigned int pmcon10;           /* memory region 10 configuration */
273  unsigned int rsvd6;
274                            /* Control Group 5 */
275  unsigned int pmcon12;           /* memory region 12 configuration */
276  unsigned int rsvd7;
277  unsigned int pmcon14;           /* memory region 14 configuration */
278  unsigned int rsvd8;
279                            /* Control Group 6 */
280  unsigned int rsvd9;
281  unsigned int rsvd10;
282  unsigned int tc;                /* trace control */
283  unsigned int bcon;              /* bus configuration control */
284}   i960rp_control_table;
285
286/* Intel i960RP Processor Control Block */
287
288typedef struct {
289  unsigned int    *fault_tbl;     /* fault table base address */
290  i960rp_control_table
291                  *control_tbl;   /* control table base address */
292  unsigned int     initial_ac;    /* AC register initial value */
293  unsigned int     fault_config;  /* fault configuration word */
294  void           **intr_tbl;      /* interrupt table base address */
295  void            *sys_proc_tbl;  /* system procedure table
296                                     base address */
297  unsigned int     reserved;      /* reserved */
298  unsigned int    *intr_stack;    /* interrupt stack pointer */
299  unsigned int     ins_cache_cfg; /* instruction cache
300                                     configuration word */
301  unsigned int     reg_cache_cfg; /* register cache configuration word */
302}   i960rp_PRCB;
303
304typedef i960rp_control_table i960_control_table;
305typedef i960rp_PRCB i960_PRCB;
306
307#else
308#error "invalid processor selection!"
309#endif
310
311/*
312 *  Miscellaneous Support Routines
313 */
314
315#define i960_reload_ctl_group( group ) \
316 { register int _cmd = ((group)|0x400) ; \
317   asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
318 }
319
320#define i960_atomic_modify( mask, addr, prev ) \
321 { register unsigned int  _mask = (mask); \
322   register unsigned int *_addr = (unsigned int *)(addr); \
323   asm volatile( "atmod  %0,%1,%1" \
324                  : "=d" (_addr), "=d" (_mask) \
325                  : "0"  (_addr), "1"  (_mask) ); \
326   (prev) = _mask; \
327 }
328
329#define atomic_modify( _mask, _address, _previous ) \
330  i960_atomic_modify( _mask, _address, _previous )
331
332#define i960_enable_tracing() \
333 { register unsigned int _pc = 0x1; \
334   asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
335 }
336
337/*
338 *  Interrupt Level Routines
339 */
340
341#define i960_disable_interrupts( oldlevel ) \
342  { (oldlevel) = 0x1f0000; \
343    asm volatile ( "modpc   0,%1,%1" \
344                       : "=d" ((oldlevel)) \
345                       : "0"  ((oldlevel)) ); \
346  }
347
348#define i960_enable_interrupts( oldlevel ) \
349  { unsigned int _mask = 0x1f0000; \
350    asm volatile ( "modpc   0,%0,%1" \
351                       : "=d" (_mask), "=d" ((oldlevel)) \
352                       : "0"  (_mask), "1"  ((oldlevel)) ); \
353  }
354
355#define i960_flash_interrupts( oldlevel ) \
356  { unsigned int _mask = 0x1f0000; \
357    asm volatile ( "modpc   0,%0,%1 ; \
358                    mov     %0,%1 ; \
359                    modpc   0,%0,%1"  \
360                       : "=d" (_mask), "=d" ((oldlevel)) \
361                       : "0"  (_mask), "1"  ((oldlevel)) ); \
362  }
363
364#define i960_get_interrupt_level( _level ) \
365  { \
366    i960_disable_interrupts( _level ); \
367    i960_enable_interrupts( _level ); \
368    (_level) = ((_level) & 0x1f0000) >> 16; \
369  } while ( 0 )
370
371#define i960_cause_intr( intr ) \
372 { register int _intr = (intr); \
373   asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
374 }
375
376/*
377 *  Interrupt Masking Routines
378 */
379
380#if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__)
381
382#define i960_unmask_intr( xint ) \
383 { register unsigned int _mask= (1<<(xint)); \
384   asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
385 }
386
387#define i960_mask_intr( xint ) \
388 { register unsigned int _mask= (1<<(xint)); \
389   asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
390 }
391
392#define i960_clear_intr( xint ) \
393 { register unsigned int _xint=(xint); \
394asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
395                  bbs    %0,sf0, loop_til_cleared" \
396                  : "=d" (_xint) : "0" (_xint) ); \
397 }
398
399static inline unsigned int i960_pend_intrs()
400{ register unsigned int _intr=0;
401  asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
402  return ( _intr );
403}
404
405static inline unsigned int i960_mask_intrs()
406{ register unsigned int _intr=0;
407  asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
408  return( _intr );
409}
410
411#elif defined(__RTEMS_I960RP__)
412
413#define i960_unmask_intr( xint ) \
414 { register unsigned int _mask= (1<<(xint)); \
415   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
416   register unsigned int _val= *_imsk; \
417   asm volatile( "or %0,%2,%0; \
418                  st %0,(%1)" \
419                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
420                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
421 }
422
423#define i960_mask_intr( xint ) \
424 { register unsigned int _mask= (1<<(xint)); \
425   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
426   register unsigned int _val = *_imsk; \
427   asm volatile( "andnot %2,%0,%0; \
428                  st %0,(%1)" \
429                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
430                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
431 }
432#define i960_clear_intr( xint ) \
433 { register unsigned int _xint=xint; \
434   register unsigned int _mask=(1<<(xint)); \
435   register unsigned int *_ipnd = (int * ) IPND_ADDR; \
436   register unsigned int          _rslt = 0; \
437asm volatile( "loop_til_cleared: mov 0, %0; \
438                  atmod %1, %2, %0; \
439                  bbs    %3,%0, loop_til_cleared" \
440                  : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
441                  : "0"  (_rslt), "1"  (_ipnd), "2"  (_mask), "3"  (_xint) ); \
442 }
443
444static inline unsigned int i960_pend_intrs()
445{ register unsigned int _intr= *(unsigned int *) IPND_ADDR;
446  /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
447   asm volatile( "mov (%0),%1" \
448                    : "=d" (_ipnd), "=d" (_mask) \
449                    : "0" (_ipnd), "1" (_mask) ); \ */
450  return ( _intr );
451}
452
453static inline unsigned int i960_mask_intrs()
454{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
455  /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
456  return( _intr );
457}
458#endif
459
460static inline unsigned int i960_get_fp()
461{ register unsigned int _fp=0;
462  asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
463  return ( _fp );
464}
465
466/*
467 *  Soft Reset
468 */
469
470#if defined(I960_SOFT_RESET_COMMAND)
471
472#define i960_soft_reset( prcb ) \
473 { register i960_PRCB    *_prcb = (prcb); \
474   register unsigned int *_next=0; \
475   register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
476   asm volatile( "lda    next,%1; \
477                  sysctl %0,%1,%2; \
478            next: mov    g0,g0" \
479                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
480                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
481 }
482
483#else
484#warning "I960_SOFT_RESET_COMMAND is not defined"
485#endif
486
487/*
488 *  The following routine swaps the endian format of an unsigned int.
489 *  It must be static because it is referenced indirectly.
490 *
491 *  This version is based on code presented in Vol. 4, No. 4 of
492 *  Insight 960.  It is certainly something you wouldn't think
493 *  of on your own.
494 */
495
496static inline unsigned int CPU_swap_u32(
497  unsigned int value
498)
499{
500  register unsigned int to_swap = value;
501  register unsigned int temp    = 0xFF00FF00;
502  register unsigned int swapped = 0;
503
504                                            /*  to_swap      swapped  */
505  asm volatile ( "rotate  16,%0,%2 ;"       /* 0x12345678  0x56781234 */
506                 "modify  %1,%0,%2 ;"       /* 0x12345678  0x12785634 */
507                 "rotate  8,%2,%2"          /* 0x12345678  0x78563412 */
508                 : "=r" (to_swap), "=r" (temp), "=r" (swapped)
509                 : "0" (to_swap), "1" (temp), "2" (swapped)
510               );
511  return( swapped );
512}
513
514#define CPU_swap_u16( value ) \
515  (((value&0xff) << 8) | ((value >> 8)&0xff))
516
517#ifdef __cplusplus
518}
519#endif
520
521#endif /* !ASM */
522
523#endif
524/* end of include file */
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