[7908ba5b] | 1 | /* i960.h |
---|
| 2 | * |
---|
| 3 | * This include file contains information pertaining to the Intel |
---|
| 4 | * i960 processor family. |
---|
| 5 | * |
---|
[08311cc3] | 6 | * COPYRIGHT (c) 1989-1999. |
---|
[7908ba5b] | 7 | * On-Line Applications Research Corporation (OAR). |
---|
| 8 | * |
---|
| 9 | * The license and distribution terms for this file may be |
---|
| 10 | * found in the file LICENSE in this distribution or at |
---|
| 11 | * http://www.OARcorp.com/rtems/license.html. |
---|
| 12 | * |
---|
| 13 | * $Id$ |
---|
| 14 | */ |
---|
| 15 | |
---|
| 16 | #ifndef __i960_h |
---|
| 17 | #define __i960_h |
---|
| 18 | |
---|
| 19 | #ifdef __cplusplus |
---|
| 20 | extern "C" { |
---|
| 21 | #endif |
---|
| 22 | |
---|
| 23 | /* |
---|
| 24 | * This file contains the information required to build |
---|
| 25 | * RTEMS for a particular member of the Intel i960 |
---|
| 26 | * family. It does this by setting variables to indicate |
---|
| 27 | * which implementation dependent features are present |
---|
| 28 | * in a particular member of the family. |
---|
| 29 | * |
---|
[e8367362] | 30 | * NOTE: For now i960 support is for models without an FPU. |
---|
| 31 | * The stubs for FP routines are in place so only need to be filled in. |
---|
| 32 | * |
---|
| 33 | * NOTE: RTEMS defines a canonical name for each cpu model. |
---|
[7908ba5b] | 34 | */ |
---|
| 35 | |
---|
[df49c60] | 36 | #if defined(rtems_multilib) |
---|
| 37 | /* |
---|
| 38 | * Figure out all CPU Model Feature Flags based upon compiler |
---|
| 39 | * predefines. |
---|
| 40 | */ |
---|
| 41 | |
---|
| 42 | #define CPU_MODEL_NAME "rtems_multilib" |
---|
| 43 | #define I960_HAS_FPU 0 |
---|
| 44 | #define I960_CPU_ALIGNMENT 4 |
---|
| 45 | #define I960_SOFT_RESET_COMMAND 0x30000 |
---|
| 46 | |
---|
| 47 | #elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
---|
[7908ba5b] | 48 | |
---|
| 49 | #define CPU_MODEL_NAME "i960ca" |
---|
[d392168] | 50 | #define __RTEMS_I960CA__ |
---|
[7908ba5b] | 51 | |
---|
[afd63b7] | 52 | #elif defined(__i960KA__) |
---|
| 53 | #define CPU_MODEL_NAME "i960ka" |
---|
| 54 | |
---|
[e8367362] | 55 | #elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA) |
---|
[c2463d9] | 56 | |
---|
| 57 | #define CPU_MODEL_NAME "i960ha" |
---|
[e8367362] | 58 | #define __RTEMS_I960HA__ |
---|
[702c5f5] | 59 | |
---|
| 60 | #elif defined(__i960RP__) |
---|
| 61 | |
---|
| 62 | #include <i960RP.h> |
---|
| 63 | #define CPU_MODEL_NAME "i960rp" |
---|
| 64 | #define __RTEMS_I960RP__ |
---|
| 65 | #define I960_CPU_ALIGNMENT 8 |
---|
| 66 | #define I960_SOFT_RESET_COMMAND 0x300 |
---|
[c2463d9] | 67 | |
---|
[7908ba5b] | 68 | #else |
---|
| 69 | |
---|
| 70 | #error "Unsupported CPU Model" |
---|
| 71 | |
---|
| 72 | #endif |
---|
| 73 | |
---|
[702c5f5] | 74 | /* |
---|
| 75 | * Now default some CPU model variation parameters |
---|
| 76 | */ |
---|
| 77 | |
---|
| 78 | #ifndef I960_HAS_FPU |
---|
| 79 | #define I960_HAS_FPU 0 |
---|
| 80 | #endif |
---|
| 81 | |
---|
| 82 | #ifndef I960_CPU_ALIGNMENT |
---|
| 83 | #define I960_CPU_ALIGNMENT 4 |
---|
| 84 | #endif |
---|
| 85 | |
---|
| 86 | #ifndef I960_SOFT_RESET_COMMAND |
---|
| 87 | #define I960_SOFT_RESET_COMMAND 0x30000 |
---|
| 88 | #endif |
---|
| 89 | |
---|
[7908ba5b] | 90 | /* |
---|
| 91 | * Define the name of the CPU family. |
---|
| 92 | */ |
---|
| 93 | |
---|
| 94 | #define CPU_NAME "Intel i960" |
---|
| 95 | |
---|
| 96 | #ifndef ASM |
---|
| 97 | |
---|
| 98 | /* |
---|
| 99 | * XXX should have an ifdef here and have stuff for the other |
---|
| 100 | * XXX family members... |
---|
| 101 | */ |
---|
| 102 | |
---|
[e8367362] | 103 | #if defined(__RTEMS_I960CA__) |
---|
[702c5f5] | 104 | /* |
---|
| 105 | * Now default some CPU model variation parameters |
---|
| 106 | */ |
---|
| 107 | |
---|
| 108 | #ifndef I960_HAS_FPU |
---|
| 109 | #define I960_HAS_FPU 0 |
---|
| 110 | #endif |
---|
| 111 | |
---|
| 112 | #ifndef I960_CPU_ALIGNMENT |
---|
| 113 | #define I960_CPU_ALIGNMENT 4 |
---|
| 114 | #endif |
---|
| 115 | |
---|
[7908ba5b] | 116 | |
---|
| 117 | /* i960CA control structures */ |
---|
| 118 | |
---|
| 119 | /* Intel i960CA Control Table */ |
---|
| 120 | |
---|
| 121 | typedef struct { |
---|
| 122 | /* Control Group 0 */ |
---|
| 123 | unsigned int ipb0; /* IP breakpoint 0 */ |
---|
| 124 | unsigned int ipb1; /* IP breakpoint 1 */ |
---|
| 125 | unsigned int dab0; /* data address breakpoint 0 */ |
---|
| 126 | unsigned int dab1; /* data address breakpoint 1 */ |
---|
| 127 | /* Control Group 1 */ |
---|
| 128 | unsigned int imap0; /* interrupt map 0 */ |
---|
| 129 | unsigned int imap1; /* interrupt map 1 */ |
---|
| 130 | unsigned int imap2; /* interrupt map 2 */ |
---|
| 131 | unsigned int icon; /* interrupt control */ |
---|
| 132 | /* Control Group 2 */ |
---|
| 133 | unsigned int mcon0; /* memory region 0 configuration */ |
---|
| 134 | unsigned int mcon1; /* memory region 1 configuration */ |
---|
| 135 | unsigned int mcon2; /* memory region 2 configuration */ |
---|
| 136 | unsigned int mcon3; /* memory region 3 configuration */ |
---|
| 137 | /* Control Group 3 */ |
---|
| 138 | unsigned int mcon4; /* memory region 4 configuration */ |
---|
| 139 | unsigned int mcon5; /* memory region 5 configuration */ |
---|
| 140 | unsigned int mcon6; /* memory region 6 configuration */ |
---|
| 141 | unsigned int mcon7; /* memory region 7 configuration */ |
---|
| 142 | /* Control Group 4 */ |
---|
| 143 | unsigned int mcon8; /* memory region 8 configuration */ |
---|
| 144 | unsigned int mcon9; /* memory region 9 configuration */ |
---|
| 145 | unsigned int mcon10; /* memory region 10 configuration */ |
---|
| 146 | unsigned int mcon11; /* memory region 11 configuration */ |
---|
| 147 | /* Control Group 5 */ |
---|
| 148 | unsigned int mcon12; /* memory region 12 configuration */ |
---|
| 149 | unsigned int mcon13; /* memory region 13 configuration */ |
---|
| 150 | unsigned int mcon14; /* memory region 14 configuration */ |
---|
| 151 | unsigned int mcon15; /* memory region 15 configuration */ |
---|
| 152 | /* Control Group 6 */ |
---|
[c2463d9] | 153 | unsigned int reserved; /* reserved */ |
---|
[7908ba5b] | 154 | unsigned int bpcon; /* breakpoint control */ |
---|
| 155 | unsigned int tc; /* trace control */ |
---|
| 156 | unsigned int bcon; /* bus configuration control */ |
---|
| 157 | } i960ca_control_table; |
---|
| 158 | |
---|
| 159 | /* Intel i960CA Processor Control Block */ |
---|
| 160 | |
---|
| 161 | typedef struct { |
---|
| 162 | unsigned int *fault_tbl; /* fault table base address */ |
---|
| 163 | i960ca_control_table |
---|
| 164 | *control_tbl; /* control table base address */ |
---|
| 165 | unsigned int initial_ac; /* AC register initial value */ |
---|
| 166 | unsigned int fault_config; /* fault configuration word */ |
---|
| 167 | void **intr_tbl; /* interrupt table base address */ |
---|
| 168 | void *sys_proc_tbl; /* system procedure table |
---|
| 169 | base address */ |
---|
| 170 | unsigned int reserved; /* reserved */ |
---|
| 171 | unsigned int *intr_stack; /* interrupt stack pointer */ |
---|
| 172 | unsigned int ins_cache_cfg; /* instruction cache |
---|
| 173 | configuration word */ |
---|
| 174 | unsigned int reg_cache_cfg; /* register cache configuration word */ |
---|
| 175 | } i960ca_PRCB; |
---|
[c2463d9] | 176 | |
---|
| 177 | typedef i960ca_control_table i960_control_table; |
---|
| 178 | typedef i960ca_PRCB i960_PRCB; |
---|
| 179 | |
---|
[e8367362] | 180 | #elif defined(__RTEMS_I960HA__) |
---|
[c2463d9] | 181 | |
---|
| 182 | /* i960HA control structures */ |
---|
| 183 | |
---|
| 184 | /* Intel i960HA Control Table */ |
---|
| 185 | |
---|
| 186 | typedef struct { |
---|
| 187 | /* Control Group 0 */ |
---|
| 188 | unsigned int ipb0; /* IP breakpoint 0 */ |
---|
| 189 | unsigned int ipb1; /* IP breakpoint 1 */ |
---|
| 190 | unsigned int dab0; /* data address breakpoint 0 */ |
---|
| 191 | unsigned int dab1; /* data address breakpoint 1 */ |
---|
| 192 | /* Control Group 1 */ |
---|
| 193 | unsigned int imap0; /* interrupt map 0 */ |
---|
| 194 | unsigned int imap1; /* interrupt map 1 */ |
---|
| 195 | unsigned int imap2; /* interrupt map 2 */ |
---|
| 196 | unsigned int icon; /* interrupt control */ |
---|
| 197 | /* Control Group 2 */ |
---|
| 198 | unsigned int mcon0; /* memory region 0 configuration */ |
---|
| 199 | unsigned int mcon1; /* memory region 1 configuration */ |
---|
| 200 | unsigned int mcon2; /* memory region 2 configuration */ |
---|
| 201 | unsigned int mcon3; /* memory region 3 configuration */ |
---|
| 202 | /* Control Group 3 */ |
---|
| 203 | unsigned int mcon4; /* memory region 4 configuration */ |
---|
| 204 | unsigned int mcon5; /* memory region 5 configuration */ |
---|
| 205 | unsigned int mcon6; /* memory region 6 configuration */ |
---|
| 206 | unsigned int mcon7; /* memory region 7 configuration */ |
---|
| 207 | /* Control Group 4 */ |
---|
| 208 | unsigned int mcon8; /* memory region 8 configuration */ |
---|
| 209 | unsigned int mcon9; /* memory region 9 configuration */ |
---|
| 210 | unsigned int mcon10; /* memory region 10 configuration */ |
---|
| 211 | unsigned int mcon11; /* memory region 11 configuration */ |
---|
| 212 | /* Control Group 5 */ |
---|
| 213 | unsigned int mcon12; /* memory region 12 configuration */ |
---|
| 214 | unsigned int mcon13; /* memory region 13 configuration */ |
---|
| 215 | unsigned int mcon14; /* memory region 14 configuration */ |
---|
| 216 | unsigned int mcon15; /* memory region 15 configuration */ |
---|
| 217 | /* Control Group 6 */ |
---|
| 218 | unsigned int reserved; /* reserved */ |
---|
| 219 | unsigned int bpcon; /* breakpoint control */ |
---|
| 220 | unsigned int tc; /* trace control */ |
---|
| 221 | unsigned int bcon; /* bus configuration control */ |
---|
| 222 | } i960ha_control_table; |
---|
| 223 | |
---|
| 224 | /* Intel i960HA Processor Control Block */ |
---|
| 225 | |
---|
| 226 | typedef struct { |
---|
| 227 | unsigned int *fault_tbl; /* fault table base address */ |
---|
| 228 | i960ha_control_table |
---|
| 229 | *control_tbl; /* control table base address */ |
---|
| 230 | unsigned int initial_ac; /* AC register initial value */ |
---|
| 231 | unsigned int fault_config; /* fault configuration word */ |
---|
| 232 | void **intr_tbl; /* interrupt table base address */ |
---|
| 233 | void *sys_proc_tbl; /* system procedure table |
---|
| 234 | base address */ |
---|
| 235 | unsigned int reserved; /* reserved */ |
---|
| 236 | unsigned int *intr_stack; /* interrupt stack pointer */ |
---|
| 237 | unsigned int ins_cache_cfg; /* instruction cache |
---|
| 238 | configuration word */ |
---|
| 239 | unsigned int reg_cache_cfg; /* register cache configuration word */ |
---|
| 240 | } i960ha_PRCB; |
---|
| 241 | |
---|
| 242 | typedef i960ha_control_table i960_control_table; |
---|
| 243 | typedef i960ha_PRCB i960_PRCB; |
---|
| 244 | |
---|
[702c5f5] | 245 | #elif defined(__RTEMS_I960RP__) |
---|
| 246 | |
---|
| 247 | /* i960RP control structures */ |
---|
| 248 | |
---|
| 249 | /* Intel i960RP Control Table */ |
---|
| 250 | |
---|
| 251 | typedef struct { |
---|
| 252 | /* Control Group 0 */ |
---|
| 253 | unsigned int rsvd00; |
---|
| 254 | unsigned int rsvd01; |
---|
| 255 | unsigned int rsvd02; |
---|
| 256 | unsigned int rsvd03; |
---|
| 257 | /* Control Group 1 */ |
---|
| 258 | unsigned int imap0; /* interrupt map 0 */ |
---|
| 259 | unsigned int imap1; /* interrupt map 1 */ |
---|
| 260 | unsigned int imap2; /* interrupt map 2 */ |
---|
| 261 | unsigned int icon; /* interrupt control */ |
---|
| 262 | /* Control Group 2 */ |
---|
| 263 | unsigned int pmcon0; /* memory region 0 configuration */ |
---|
| 264 | unsigned int rsvd1; |
---|
| 265 | unsigned int pmcon2; /* memory region 2 configuration */ |
---|
| 266 | unsigned int rsvd2; |
---|
| 267 | /* Control Group 3 */ |
---|
| 268 | unsigned int pmcon4; /* memory region 4 configuration */ |
---|
| 269 | unsigned int rsvd3; |
---|
| 270 | unsigned int pmcon6; /* memory region 6 configuration */ |
---|
| 271 | unsigned int rsvd4; |
---|
| 272 | /* Control Group 4 */ |
---|
| 273 | unsigned int pmcon8; /* memory region 8 configuration */ |
---|
| 274 | unsigned int rsvd5; |
---|
| 275 | unsigned int pmcon10; /* memory region 10 configuration */ |
---|
| 276 | unsigned int rsvd6; |
---|
| 277 | /* Control Group 5 */ |
---|
| 278 | unsigned int pmcon12; /* memory region 12 configuration */ |
---|
| 279 | unsigned int rsvd7; |
---|
| 280 | unsigned int pmcon14; /* memory region 14 configuration */ |
---|
| 281 | unsigned int rsvd8; |
---|
| 282 | /* Control Group 6 */ |
---|
| 283 | unsigned int rsvd9; |
---|
| 284 | unsigned int rsvd10; |
---|
| 285 | unsigned int tc; /* trace control */ |
---|
| 286 | unsigned int bcon; /* bus configuration control */ |
---|
| 287 | } i960rp_control_table; |
---|
| 288 | |
---|
| 289 | /* Intel i960RP Processor Control Block */ |
---|
| 290 | |
---|
| 291 | typedef struct { |
---|
| 292 | unsigned int *fault_tbl; /* fault table base address */ |
---|
| 293 | i960rp_control_table |
---|
| 294 | *control_tbl; /* control table base address */ |
---|
| 295 | unsigned int initial_ac; /* AC register initial value */ |
---|
| 296 | unsigned int fault_config; /* fault configuration word */ |
---|
| 297 | void **intr_tbl; /* interrupt table base address */ |
---|
| 298 | void *sys_proc_tbl; /* system procedure table |
---|
| 299 | base address */ |
---|
| 300 | unsigned int reserved; /* reserved */ |
---|
| 301 | unsigned int *intr_stack; /* interrupt stack pointer */ |
---|
| 302 | unsigned int ins_cache_cfg; /* instruction cache |
---|
| 303 | configuration word */ |
---|
| 304 | unsigned int reg_cache_cfg; /* register cache configuration word */ |
---|
| 305 | } i960rp_PRCB; |
---|
| 306 | |
---|
| 307 | typedef i960rp_control_table i960_control_table; |
---|
| 308 | typedef i960rp_PRCB i960_PRCB; |
---|
| 309 | |
---|
[afd63b7] | 310 | #elif defined(__i960KA__) |
---|
| 311 | |
---|
| 312 | /* i960KA control structures */ |
---|
| 313 | |
---|
| 314 | /* Intel i960KA Control Table */ |
---|
| 315 | |
---|
| 316 | typedef struct { |
---|
| 317 | int pad0; |
---|
| 318 | } i960ka_control_table; |
---|
| 319 | |
---|
| 320 | /* Intel i960KA Processor Control Block */ |
---|
| 321 | |
---|
| 322 | typedef struct { |
---|
| 323 | void **intr_tbl; /* interrupt table base address */ |
---|
| 324 | unsigned int *intr_stack; /* interrupt stack pointer */ |
---|
| 325 | } i960ka_PRCB; |
---|
| 326 | |
---|
| 327 | typedef i960ka_control_table i960_control_table; |
---|
| 328 | typedef i960ka_PRCB i960_PRCB; |
---|
| 329 | |
---|
[702c5f5] | 330 | #else |
---|
| 331 | #error "invalid processor selection!" |
---|
[7908ba5b] | 332 | #endif |
---|
| 333 | |
---|
[702c5f5] | 334 | /* |
---|
| 335 | * Miscellaneous Support Routines |
---|
| 336 | */ |
---|
| 337 | |
---|
[afd63b7] | 338 | #if !defined(__i960KA__) |
---|
[702c5f5] | 339 | #define i960_reload_ctl_group( group ) \ |
---|
| 340 | { register int _cmd = ((group)|0x400) ; \ |
---|
| 341 | asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \ |
---|
| 342 | } |
---|
[afd63b7] | 343 | #endif |
---|
[702c5f5] | 344 | |
---|
| 345 | #define i960_atomic_modify( mask, addr, prev ) \ |
---|
| 346 | { register unsigned int _mask = (mask); \ |
---|
| 347 | register unsigned int *_addr = (unsigned int *)(addr); \ |
---|
| 348 | asm volatile( "atmod %0,%1,%1" \ |
---|
| 349 | : "=d" (_addr), "=d" (_mask) \ |
---|
| 350 | : "0" (_addr), "1" (_mask) ); \ |
---|
| 351 | (prev) = _mask; \ |
---|
| 352 | } |
---|
| 353 | |
---|
| 354 | #define atomic_modify( _mask, _address, _previous ) \ |
---|
| 355 | i960_atomic_modify( _mask, _address, _previous ) |
---|
| 356 | |
---|
| 357 | #define i960_enable_tracing() \ |
---|
| 358 | { register unsigned int _pc = 0x1; \ |
---|
| 359 | asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \ |
---|
| 360 | } |
---|
| 361 | |
---|
[7908ba5b] | 362 | /* |
---|
| 363 | * Interrupt Level Routines |
---|
| 364 | */ |
---|
| 365 | |
---|
| 366 | #define i960_disable_interrupts( oldlevel ) \ |
---|
| 367 | { (oldlevel) = 0x1f0000; \ |
---|
| 368 | asm volatile ( "modpc 0,%1,%1" \ |
---|
| 369 | : "=d" ((oldlevel)) \ |
---|
| 370 | : "0" ((oldlevel)) ); \ |
---|
| 371 | } |
---|
| 372 | |
---|
| 373 | #define i960_enable_interrupts( oldlevel ) \ |
---|
| 374 | { unsigned int _mask = 0x1f0000; \ |
---|
| 375 | asm volatile ( "modpc 0,%0,%1" \ |
---|
| 376 | : "=d" (_mask), "=d" ((oldlevel)) \ |
---|
| 377 | : "0" (_mask), "1" ((oldlevel)) ); \ |
---|
| 378 | } |
---|
| 379 | |
---|
| 380 | #define i960_flash_interrupts( oldlevel ) \ |
---|
| 381 | { unsigned int _mask = 0x1f0000; \ |
---|
| 382 | asm volatile ( "modpc 0,%0,%1 ; \ |
---|
| 383 | mov %0,%1 ; \ |
---|
| 384 | modpc 0,%0,%1" \ |
---|
| 385 | : "=d" (_mask), "=d" ((oldlevel)) \ |
---|
| 386 | : "0" (_mask), "1" ((oldlevel)) ); \ |
---|
| 387 | } |
---|
| 388 | |
---|
| 389 | #define i960_get_interrupt_level( _level ) \ |
---|
| 390 | { \ |
---|
| 391 | i960_disable_interrupts( _level ); \ |
---|
| 392 | i960_enable_interrupts( _level ); \ |
---|
| 393 | (_level) = ((_level) & 0x1f0000) >> 16; \ |
---|
| 394 | } while ( 0 ) |
---|
| 395 | |
---|
[afd63b7] | 396 | #if !defined(__i960KA__) |
---|
[702c5f5] | 397 | #define i960_cause_intr( intr ) \ |
---|
| 398 | { register int _intr = (intr); \ |
---|
| 399 | asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \ |
---|
[7908ba5b] | 400 | } |
---|
[afd63b7] | 401 | #endif |
---|
[7908ba5b] | 402 | |
---|
[702c5f5] | 403 | /* |
---|
| 404 | * Interrupt Masking Routines |
---|
| 405 | */ |
---|
[7908ba5b] | 406 | |
---|
[702c5f5] | 407 | #if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__) |
---|
[7908ba5b] | 408 | |
---|
| 409 | #define i960_unmask_intr( xint ) \ |
---|
| 410 | { register unsigned int _mask= (1<<(xint)); \ |
---|
| 411 | asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \ |
---|
| 412 | } |
---|
| 413 | |
---|
| 414 | #define i960_mask_intr( xint ) \ |
---|
| 415 | { register unsigned int _mask= (1<<(xint)); \ |
---|
| 416 | asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \ |
---|
| 417 | } |
---|
| 418 | |
---|
| 419 | #define i960_clear_intr( xint ) \ |
---|
| 420 | { register unsigned int _xint=(xint); \ |
---|
| 421 | asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \ |
---|
| 422 | bbs %0,sf0, loop_til_cleared" \ |
---|
| 423 | : "=d" (_xint) : "0" (_xint) ); \ |
---|
| 424 | } |
---|
| 425 | |
---|
[702c5f5] | 426 | static inline unsigned int i960_pend_intrs() |
---|
| 427 | { register unsigned int _intr=0; |
---|
| 428 | asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) ); |
---|
| 429 | return ( _intr ); |
---|
| 430 | } |
---|
[7908ba5b] | 431 | |
---|
[702c5f5] | 432 | static inline unsigned int i960_mask_intrs() |
---|
| 433 | { register unsigned int _intr=0; |
---|
| 434 | asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) ); |
---|
| 435 | return( _intr ); |
---|
| 436 | } |
---|
| 437 | |
---|
| 438 | #elif defined(__RTEMS_I960RP__) |
---|
| 439 | |
---|
| 440 | #define i960_unmask_intr( xint ) \ |
---|
| 441 | { register unsigned int _mask= (1<<(xint)); \ |
---|
| 442 | register unsigned int *_imsk = (int * ) IMSK_ADDR; \ |
---|
| 443 | register unsigned int _val= *_imsk; \ |
---|
| 444 | asm volatile( "or %0,%2,%0; \ |
---|
| 445 | st %0,(%1)" \ |
---|
| 446 | : "=d" (_val), "=d" (_imsk), "=d" (_mask) \ |
---|
| 447 | : "0" (_val), "1" (_imsk), "2" (_mask) ); \ |
---|
[7908ba5b] | 448 | } |
---|
| 449 | |
---|
[702c5f5] | 450 | #define i960_mask_intr( xint ) \ |
---|
| 451 | { register unsigned int _mask= (1<<(xint)); \ |
---|
| 452 | register unsigned int *_imsk = (int * ) IMSK_ADDR; \ |
---|
| 453 | register unsigned int _val = *_imsk; \ |
---|
| 454 | asm volatile( "andnot %2,%0,%0; \ |
---|
| 455 | st %0,(%1)" \ |
---|
| 456 | : "=d" (_val), "=d" (_imsk), "=d" (_mask) \ |
---|
| 457 | : "0" (_val), "1" (_imsk), "2" (_mask) ); \ |
---|
| 458 | } |
---|
| 459 | #define i960_clear_intr( xint ) \ |
---|
| 460 | { register unsigned int _xint=xint; \ |
---|
| 461 | register unsigned int _mask=(1<<(xint)); \ |
---|
| 462 | register unsigned int *_ipnd = (int * ) IPND_ADDR; \ |
---|
| 463 | register unsigned int _rslt = 0; \ |
---|
| 464 | asm volatile( "loop_til_cleared: mov 0, %0; \ |
---|
| 465 | atmod %1, %2, %0; \ |
---|
| 466 | bbs %3,%0, loop_til_cleared" \ |
---|
| 467 | : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \ |
---|
| 468 | : "0" (_rslt), "1" (_ipnd), "2" (_mask), "3" (_xint) ); \ |
---|
[7908ba5b] | 469 | } |
---|
| 470 | |
---|
| 471 | static inline unsigned int i960_pend_intrs() |
---|
[702c5f5] | 472 | { register unsigned int _intr= *(unsigned int *) IPND_ADDR; |
---|
| 473 | /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \ |
---|
| 474 | asm volatile( "mov (%0),%1" \ |
---|
| 475 | : "=d" (_ipnd), "=d" (_mask) \ |
---|
| 476 | : "0" (_ipnd), "1" (_mask) ); \ */ |
---|
[7908ba5b] | 477 | return ( _intr ); |
---|
| 478 | } |
---|
| 479 | |
---|
| 480 | static inline unsigned int i960_mask_intrs() |
---|
[702c5f5] | 481 | { register unsigned int _intr= *(unsigned int *) IMSK_ADDR; |
---|
| 482 | /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/ |
---|
[7908ba5b] | 483 | return( _intr ); |
---|
| 484 | } |
---|
[702c5f5] | 485 | #endif |
---|
[7908ba5b] | 486 | |
---|
| 487 | static inline unsigned int i960_get_fp() |
---|
| 488 | { register unsigned int _fp=0; |
---|
| 489 | asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) ); |
---|
| 490 | return ( _fp ); |
---|
| 491 | } |
---|
| 492 | |
---|
[702c5f5] | 493 | /* |
---|
| 494 | * Soft Reset |
---|
| 495 | */ |
---|
| 496 | |
---|
| 497 | #if defined(I960_SOFT_RESET_COMMAND) |
---|
| 498 | #define i960_soft_reset( prcb ) \ |
---|
| 499 | { register i960_PRCB *_prcb = (prcb); \ |
---|
| 500 | register unsigned int *_next=0; \ |
---|
| 501 | register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \ |
---|
| 502 | asm volatile( "lda next,%1; \ |
---|
| 503 | sysctl %0,%1,%2; \ |
---|
| 504 | next: mov g0,g0" \ |
---|
| 505 | : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ |
---|
| 506 | : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ |
---|
| 507 | } |
---|
| 508 | |
---|
[afd63b7] | 509 | #elif !defined(__i960KA__) |
---|
[702c5f5] | 510 | #warning "I960_SOFT_RESET_COMMAND is not defined" |
---|
| 511 | #endif |
---|
| 512 | |
---|
[7908ba5b] | 513 | /* |
---|
| 514 | * The following routine swaps the endian format of an unsigned int. |
---|
| 515 | * It must be static because it is referenced indirectly. |
---|
| 516 | * |
---|
| 517 | * This version is based on code presented in Vol. 4, No. 4 of |
---|
| 518 | * Insight 960. It is certainly something you wouldn't think |
---|
| 519 | * of on your own. |
---|
| 520 | */ |
---|
| 521 | |
---|
| 522 | static inline unsigned int CPU_swap_u32( |
---|
| 523 | unsigned int value |
---|
| 524 | ) |
---|
| 525 | { |
---|
| 526 | register unsigned int to_swap = value; |
---|
| 527 | register unsigned int temp = 0xFF00FF00; |
---|
| 528 | register unsigned int swapped = 0; |
---|
| 529 | |
---|
| 530 | /* to_swap swapped */ |
---|
| 531 | asm volatile ( "rotate 16,%0,%2 ;" /* 0x12345678 0x56781234 */ |
---|
| 532 | "modify %1,%0,%2 ;" /* 0x12345678 0x12785634 */ |
---|
| 533 | "rotate 8,%2,%2" /* 0x12345678 0x78563412 */ |
---|
| 534 | : "=r" (to_swap), "=r" (temp), "=r" (swapped) |
---|
| 535 | : "0" (to_swap), "1" (temp), "2" (swapped) |
---|
| 536 | ); |
---|
| 537 | return( swapped ); |
---|
| 538 | } |
---|
| 539 | |
---|
| 540 | #define CPU_swap_u16( value ) \ |
---|
| 541 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 542 | |
---|
| 543 | #ifdef __cplusplus |
---|
| 544 | } |
---|
| 545 | #endif |
---|
| 546 | |
---|
| 547 | #endif /* !ASM */ |
---|
| 548 | |
---|
| 549 | #endif |
---|
| 550 | /* end of include file */ |
---|