source: rtems/c/src/exec/score/cpu/i960/rtems/score/cpu.h @ bc85fd5a

4.104.114.84.95
Last change on this file since bc85fd5a was bc85fd5a, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 11, 2000 at 7:31:04 PM

Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.

  • Property mode set to 100644
File size: 13.0 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __CPU_h
17#define __CPU_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include <rtems/score/i960.h>              /* pick up machine definitions */
24#ifndef ASM
25#include <rtems/score/i960types.h>
26#endif
27
28#define CPU_INLINE_ENABLE_DISPATCH       FALSE
29#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
30
31/*
32 *  Use the i960's hardware interrupt stack support and have the
33 *  interrupt manager allocate the memory for it.
34 */
35
36#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
37#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
38#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
39
40/*
41 *  Does the RTEMS invoke the user's ISR with the vector number and
42 *  a pointer to the saved interrupt frame (1) or just the vector
43 *  number (0)?
44 */
45
46#define CPU_ISR_PASSES_FRAME_POINTER 0
47
48/*
49 *  Some family members have no FP (SA/KA/CA/CF), others have it built in
50 *  (KB/MC/MX).  There does not appear to be an external coprocessor
51 *  for this family.
52 */
53
54#if ( I960_HAS_FPU == 1 )
55#define CPU_HARDWARE_FP     TRUE
56#error "Floating point support for i960 family has been implemented!!!"
57#else
58#define CPU_HARDWARE_FP     FALSE
59#endif
60
61#define CPU_ALL_TASKS_ARE_FP             FALSE
62#define CPU_IDLE_TASK_IS_FP              FALSE
63#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
64
65#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
66#define CPU_STACK_GROWS_UP               TRUE
67#define CPU_STRUCTURE_ALIGNMENT          /* __attribute__ ((aligned (16))) */
68
69/*
70 *  Define what is required to specify how the network to host conversion
71 *  routines are handled.
72 */
73
74#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
75#define CPU_BIG_ENDIAN                           TRUE
76#define CPU_LITTLE_ENDIAN                        FALSE
77
78
79/* structures */
80
81/*
82 *  Basic integer context for the i960 family.
83 */
84
85typedef struct {
86  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
87  void       *r1_sp;                  /* (r1)  Stack Pointer */
88  unsigned32  pc;                     /* (pc)  Processor Control */
89  void       *g8;                     /* (g8)  Global Register 8 */
90  void       *g9;                     /* (g9)  Global Register 9 */
91  void       *g10;                    /* (g10) Global Register 10 */
92  void       *g11;                    /* (g11) Global Register 11 */
93  void       *g12;                    /* (g12) Global Register 12 */
94  void       *g13;                    /* (g13) Global Register 13 */
95  unsigned32  g14;                    /* (g14) Global Register 14 */
96  void       *g15_fp;                 /* (g15) Frame Pointer */
97}   Context_Control;
98
99/*
100 *  FP context save area for the i960 Numeric Extension
101 */
102
103typedef struct {
104   unsigned32  fp0_1;                 /* (fp0) first word  */
105   unsigned32  fp0_2;                 /* (fp0) second word */
106   unsigned32  fp0_3;                 /* (fp0) third word  */
107   unsigned32  fp1_1;                 /* (fp1) first word  */
108   unsigned32  fp1_2;                 /* (fp1) second word */
109   unsigned32  fp1_3;                 /* (fp1) third word  */
110   unsigned32  fp2_1;                 /* (fp2) first word  */
111   unsigned32  fp2_2;                 /* (fp2) second word */
112   unsigned32  fp2_3;                 /* (fp2) third word  */
113   unsigned32  fp3_1;                 /* (fp3) first word  */
114   unsigned32  fp3_2;                 /* (fp3) second word */
115   unsigned32  fp3_3;                 /* (fp3) third word  */
116} Context_Control_fp;
117
118/*
119 *  The following structure defines the set of information saved
120 *  on the current stack by RTEMS upon receipt of each interrupt.
121 */
122
123typedef struct {
124  unsigned32   TBD;   /* XXX Fix for this CPU */
125} CPU_Interrupt_frame;
126
127/*
128 *  Call frame for the i960 family.
129 */
130
131typedef struct {
132  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
133  void       *r1_sp;                  /* (r1)  Stack Pointer */
134  void       *r2_rip;                 /* (r2)  Return Instruction Pointer */
135  void       *r3;                     /* (r3)  Local Register 3 */
136  void       *r4;                     /* (r4)  Local Register 4 */
137  void       *r5;                     /* (r5)  Local Register 5 */
138  void       *r6;                     /* (r6)  Local Register 6 */
139  void       *r7;                     /* (r7)  Local Register 7 */
140  void       *r8;                     /* (r8)  Local Register 8 */
141  void       *r9;                     /* (r9)  Local Register 9 */
142  void       *r10;                    /* (r10) Local Register 10 */
143  void       *r11;                    /* (r11) Local Register 11 */
144  void       *r12;                    /* (r12) Local Register 12 */
145  void       *r13;                    /* (r13) Local Register 13 */
146  void       *r14;                    /* (r14) Local Register 14 */
147  void       *r15;                    /* (r15) Local Register 15 */
148  /* XXX Looks like sometimes there is FP stuff here (MC manual)? */
149}   CPU_Call_frame;
150
151/*
152 *  The following table contains the information required to configure
153 *  the i960 specific parameters.
154 */
155
156typedef struct {
157  void       (*pretasking_hook)( void );
158  void       (*predriver_hook)( void );
159  void       (*postdriver_hook)( void );
160  void       (*idle_task)( void );
161  boolean      do_zero_of_workspace;
162  unsigned32   idle_task_stack_size;
163  unsigned32   interrupt_stack_size;
164  unsigned32   extra_mpci_receive_server_stack;
165  void *     (*stack_allocate_hook)( unsigned32 );
166  void       (*stack_free_hook)( void* );
167  /* end of fields required on all CPUs */
168}   rtems_cpu_table;
169
170/*
171 *  Macros to access required entires in the CPU Table are in
172 *  the file rtems/system.h.
173 */
174
175/*
176 *  Macros to access i960 specific additions to the CPU Table
177 *
178 *  NONE
179 */
180
181/* variables */
182
183SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
184SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
185
186/* constants */
187
188/*
189 *  This defines the number of levels and the mask used to pick those
190 *  bits out of a thread mode.
191 */
192
193#define CPU_MODES_INTERRUPT_LEVEL  0x0000001f  /* interrupt level in mode */
194#define CPU_MODES_INTERRUPT_MASK   0x0000001f  /* interrupt level in mode */
195
196/*
197 *  context size area for floating point
198 */
199
200#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
201
202/*
203 *  extra stack required by the MPCI receive server thread
204 */
205
206#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)
207
208/*
209 *  i960 family supports 256 distinct vectors.
210 */
211
212#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
213#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
214
215/*
216 *  Minimum size of a thread's stack.
217 *
218 *  NOTE:  See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK
219 */
220
221#define CPU_STACK_MINIMUM_SIZE          2048
222
223/*
224 *  i960 is pretty tolerant of alignment but some CPU models do
225 *  better with different default aligments so we use what the
226 *  CPU model selected in rtems/score/i960.h.
227 */
228
229#define CPU_ALIGNMENT                   I960_CPU_ALIGNMENT
230#define CPU_HEAP_ALIGNMENT              CPU_ALIGNMENT
231#define CPU_PARTITION_ALIGNMENT         CPU_ALIGNMENT
232
233/*
234 * i960ca stack requires 16 byte alignment
235 *
236 *  NOTE:  This factor may need to be family member dependent.
237 */
238
239#define CPU_STACK_ALIGNMENT        16
240
241/* macros */
242
243/*
244 *  ISR handler macros
245 *
246 *  These macros perform the following functions:
247 *     + disable all maskable CPU interrupts
248 *     + restore previous interrupt level (enable)
249 *     + temporarily restore interrupts (flash)
250 *     + set a particular level
251 */
252
253#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level )
254#define _CPU_ISR_Enable( _level )  i960_enable_interrupts( _level )
255#define _CPU_ISR_Flash( _level )   i960_flash_interrupts( _level )
256
257#define _CPU_ISR_Set_level( newlevel ) \
258  { \
259    unsigned32 _mask = 0; \
260    unsigned32 _level = (newlevel); \
261    \
262    __asm__ volatile ( "ldconst 0x1f0000,%0; \
263                    modpc   0,%0,%1"     : "=d" (_mask), "=d" (_level) \
264                                         : "0"  (_mask), "1" (_level) \
265    ); \
266  }
267
268unsigned32 _CPU_ISR_Get_level( void );
269
270/* ISR handler section macros */
271
272/*
273 *  Context handler macros
274 *
275 *  These macros perform the following functions:
276 *     + initialize a context area
277 *     + restart the current thread
278 *     + calculate the initial pointer into a FP context area
279 *     + initialize an FP context area
280 */
281
282#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
283                                  _isr, _entry, _is_fp ) \
284 { CPU_Call_frame *_texit_frame; \
285   unsigned32 _mask; \
286   unsigned32 _base_pc; \
287   unsigned32  _stack_tmp; \
288   void       *_stack; \
289   \
290  _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \
291  _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
292  _stack = (void *) _stack_tmp; \
293   \
294   __asm__ volatile ( "flushreg" : : );   /* flush register cache */ \
295   \
296   (_the_context)->r0_pfp = _stack; \
297   (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \
298   (_the_context)->r1_sp  = _stack + (2 * sizeof(CPU_Call_frame)); \
299   __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \
300                  "modpc   0,0,%1 ; " \
301                  "andnot  %0,%1,%1 ; " \
302                  : "=d" (_mask), "=d" (_base_pc) : ); \
303   (_the_context)->pc     = _base_pc | ((_isr) << 16); \
304   (_the_context)->g14    = 0; \
305   \
306   _texit_frame         = (CPU_Call_frame *)_stack; \
307   _texit_frame->r0_pfp = NULL; \
308   _texit_frame->r1_sp  = (_the_context)->g15_fp; \
309   _texit_frame->r2_rip = (_entry); \
310 }
311
312#define _CPU_Context_Restart_self( _the_context ) \
313   _CPU_Context_restore( (_the_context) );
314
315#define _CPU_Context_Fp_start( _base, _offset )         NULL
316
317#define _CPU_Context_Initialize_fp( _fp_area )
318
319/* end of Context handler macros */
320
321/*
322 *  Fatal Error manager macros
323 *
324 *  These macros perform the following functions:
325 *    + disable interrupts and halt the CPU
326 */
327
328#define _CPU_Fatal_halt( _errorcode ) \
329  { unsigned32 _mask, _level; \
330    unsigned32 _error = (_errorcode); \
331    \
332    __asm__ volatile ( "ldconst 0x1f0000,%0 ; \
333                    mov     %0,%1 ; \
334                    modpc   0,%0,%1 ; \
335                    mov     %2,g0 ; \
336            self:   b       self " \
337                    : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \
338  }
339
340/* end of Fatal Error Manager macros */
341
342/*
343 *  Bitfield handler macros
344 *
345 *  These macros perform the following functions:
346 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
347 */
348
349#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
350#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
351
352#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
353  { unsigned32 _search = (_value); \
354    \
355    (_output) = 0; /* to prevent warnings */ \
356    __asm__ volatile ( "scanbit   %0,%1  " \
357                    : "=d" (_search), "=d" (_output) \
358                    : "0"  (_search), "1"  (_output) ); \
359  }
360
361/* end of Bitfield handler macros */
362
363/*
364 *  Priority handler macros
365 *
366 *  These macros perform the following functions:
367 *    + return a mask with the bit for this major/minor portion of
368 *      of thread priority set.
369 *    + translate the bit number returned by "Bitfield_find_first_bit"
370 *      into an index into the thread ready chain bit maps
371 */
372
373#define _CPU_Priority_Mask( _bit_number ) \
374   ( 0x8000 >> (_bit_number) )
375
376#define _CPU_Priority_bits_index( _priority ) \
377   ( 15 - (_priority) )
378
379/* end of Priority handler macros */
380
381/* functions */
382
383/*
384 *  _CPU_Initialize
385 *
386 *  This routine performs CPU dependent initialization.
387 */
388
389void _CPU_Initialize(
390  rtems_cpu_table  *cpu_table,
391  void      (*thread_dispatch)
392);
393
394/*
395 *  _CPU_ISR_install_raw_handler
396 *
397 *  This routine installs a "raw" interrupt handler directly into the
398 *  processor's vector table.
399 */
400 
401void _CPU_ISR_install_raw_handler(
402  unsigned32  vector,
403  proc_ptr    new_handler,
404  proc_ptr   *old_handler
405);
406
407/*
408 *  _CPU_ISR_install_vector
409 *
410 *  This routine installs an interrupt vector.
411 */
412
413void _CPU_ISR_install_vector(
414  unsigned32  vector,
415  proc_ptr    new_handler,
416  proc_ptr   *old_handler
417);
418
419/*
420 *  _CPU_Install_interrupt_stack
421 *
422 *  This routine installs the hardware interrupt stack pointer.
423 */
424
425void _CPU_Install_interrupt_stack( void );
426
427/*
428 *  _CPU_Context_switch
429 *
430 *  This routine switches from the run context to the heir context.
431 */
432
433void _CPU_Context_switch(
434  Context_Control  *run,
435  Context_Control  *heir
436);
437
438/*
439 *  _CPU_Context_restore
440 *
441 *  This routine is generally used only to restart self in an
442 *  efficient manner and avoid stack conflicts.
443 */
444
445void _CPU_Context_restore(
446  Context_Control *new_context
447);
448
449/*
450 *  _CPU_Context_save_fp
451 *
452 *  This routine saves the floating point context passed to it.
453 */
454
455void _CPU_Context_save_fp(
456  void        **fp_context_ptr
457);
458
459/*
460 *  _CPU_Context_restore_fp
461 *
462 *  This routine restores the floating point context passed to it.
463 */
464
465void _CPU_Context_restore_fp(
466  void        **fp_context_ptr
467);
468
469#ifdef __cplusplus
470}
471#endif
472
473#endif
474/* end of include file */
Note: See TracBrowser for help on using the repository browser.